338 lines
9.8 KiB
C
338 lines
9.8 KiB
C
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/*
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* File: include/asm-blackfin/mach-bf527/mem_init.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
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#if (CONFIG_SCLK_HZ > 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_7
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#define SDRAM_tRAS_num 7
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_6
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#define SDRAM_tRAS_num 6
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_5
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#define SDRAM_tRAS_num 5
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_2
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#define SDRAM_tRAS_num 2
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ <= 29850746)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_1
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#define SDRAM_tRAS_num 1
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#endif
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#if (CONFIG_MEM_MT48LC16M16A2TG_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_MT48LC16M8A2TG_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_MT48LC32M8A2_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_GENERIC_BOARD)
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/*SDRAM INFORMATION: Modify this for your board */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_MT48LC32M16A2TG_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_SIZE == 128)
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#define SDRAM_SIZE EBSZ_128
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#endif
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#if (CONFIG_MEM_SIZE == 64)
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#define SDRAM_SIZE EBSZ_64
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#endif
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#if (CONFIG_MEM_SIZE == 32)
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#define SDRAM_SIZE EBSZ_32
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#endif
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#if (CONFIG_MEM_SIZE == 16)
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#define SDRAM_SIZE EBSZ_16
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 11)
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#define SDRAM_WIDTH EBCAW_11
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 10)
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#define SDRAM_WIDTH EBCAW_10
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 9)
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#define SDRAM_WIDTH EBCAW_9
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 8)
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#define SDRAM_WIDTH EBCAW_8
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#endif
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#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
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/* Equation from section 17 (p17-46) of BF533 HRM */
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#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
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/* Enable SCLK Out */
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#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
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#if defined CONFIG_CLKIN_HALF
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#define CLKIN_HALF 1
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#else
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#define CLKIN_HALF 0
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#endif
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#if defined CONFIG_PLL_BYPASS
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#define PLL_BYPASS 1
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#else
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#define PLL_BYPASS 0
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#endif
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/***************************************Currently Not Being Used *********************************/
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#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
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#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
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#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
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#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
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#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
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#if (flash_EBIU_AMBCTL_TT > 3)
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#define flash_EBIU_AMBCTL0_TT B0TT_4
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#endif
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#if (flash_EBIU_AMBCTL_TT == 3)
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#define flash_EBIU_AMBCTL0_TT B0TT_3
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#endif
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#if (flash_EBIU_AMBCTL_TT == 2)
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#define flash_EBIU_AMBCTL0_TT B0TT_2
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#endif
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#if (flash_EBIU_AMBCTL_TT < 2)
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#define flash_EBIU_AMBCTL0_TT B0TT_1
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#endif
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#if (flash_EBIU_AMBCTL_ST > 3)
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#define flash_EBIU_AMBCTL0_ST B0ST_4
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#endif
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#if (flash_EBIU_AMBCTL_ST == 3)
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#define flash_EBIU_AMBCTL0_ST B0ST_3
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#endif
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#if (flash_EBIU_AMBCTL_ST == 2)
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#define flash_EBIU_AMBCTL0_ST B0ST_2
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#endif
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#if (flash_EBIU_AMBCTL_ST < 2)
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#define flash_EBIU_AMBCTL0_ST B0ST_1
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#endif
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#if (flash_EBIU_AMBCTL_HT > 2)
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#define flash_EBIU_AMBCTL0_HT B0HT_3
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#endif
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#if (flash_EBIU_AMBCTL_HT == 2)
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#define flash_EBIU_AMBCTL0_HT B0HT_2
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#endif
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#if (flash_EBIU_AMBCTL_HT == 1)
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#define flash_EBIU_AMBCTL0_HT B0HT_1
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#endif
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#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
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#define flash_EBIU_AMBCTL0_HT B0HT_0
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#endif
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#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
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#define flash_EBIU_AMBCTL0_HT B0HT_1
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#endif
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#if (flash_EBIU_AMBCTL_WAT > 14)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_15
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 14)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_14
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 13)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_13
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 12)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_12
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 11)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_11
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 10)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_10
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 9)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_9
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 8)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_8
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 7)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_7
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 6)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_6
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 5)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_5
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 4)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_4
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 3)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_3
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 2)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_2
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#endif
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#if (flash_EBIU_AMBCTL_WAT == 1)
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#define flash_EBIU_AMBCTL0_WAT B0WAT_1
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#endif
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#if (flash_EBIU_AMBCTL_RAT > 14)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_15
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 14)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_14
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 13)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_13
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 12)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_12
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 11)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_11
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 10)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_10
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 9)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_9
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 8)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_8
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 7)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_7
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 6)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_6
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 5)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_5
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 4)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_4
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 3)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_3
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 2)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_2
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#endif
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#if (flash_EBIU_AMBCTL_RAT == 1)
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#define flash_EBIU_AMBCTL0_RAT B0RAT_1
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#endif
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#define flash_EBIU_AMBCTL0 \
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(flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
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flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
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