drm/amdgpu: use pp_feature member to store the mask
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1430,6 +1430,7 @@ enum amd_hw_ip_block_type {
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struct amd_powerplay {
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struct amd_powerplay {
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void *pp_handle;
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void *pp_handle;
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const struct amd_pm_funcs *pp_funcs;
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const struct amd_pm_funcs *pp_funcs;
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uint32_t pp_feature;
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};
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};
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#define AMDGPU_RESET_MAGIC_NUM 64
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#define AMDGPU_RESET_MAGIC_NUM 64
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@ -1545,6 +1545,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
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return -EAGAIN;
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return -EAGAIN;
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}
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}
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adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
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for (i = 0; i < adev->num_ip_blocks; i++) {
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
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if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
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DRM_ERROR("disabled ip block: %d <%s>\n",
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DRM_ERROR("disabled ip block: %d <%s>\n",
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@ -5903,7 +5903,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
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pi->pcie_dpm_key_disabled = 0;
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pi->pcie_dpm_key_disabled = 0;
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pi->thermal_sclk_dpm_enabled = 0;
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pi->thermal_sclk_dpm_enabled = 0;
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if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
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if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
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pi->caps_sclk_ds = true;
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pi->caps_sclk_ds = true;
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else
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else
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pi->caps_sclk_ds = false;
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pi->caps_sclk_ds = false;
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@ -2817,7 +2817,7 @@ static int kv_dpm_init(struct amdgpu_device *adev)
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pi->caps_tcp_ramping = true;
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pi->caps_tcp_ramping = true;
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}
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}
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if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
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if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
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pi->caps_sclk_ds = true;
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pi->caps_sclk_ds = true;
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else
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else
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pi->caps_sclk_ds = false;
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pi->caps_sclk_ds = false;
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@ -53,7 +53,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
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mutex_init(&hwmgr->smu_lock);
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mutex_init(&hwmgr->smu_lock);
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hwmgr->chip_family = adev->family;
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hwmgr->chip_family = adev->family;
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hwmgr->chip_id = adev->asic_type;
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hwmgr->chip_id = adev->asic_type;
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hwmgr->feature_mask = amdgpu_pp_feature_mask;
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hwmgr->feature_mask = adev->powerplay.pp_feature;
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hwmgr->display_config = &adev->pm.pm_display_cfg;
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hwmgr->display_config = &adev->pm.pm_display_cfg;
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adev->powerplay.pp_handle = hwmgr;
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adev->powerplay.pp_handle = hwmgr;
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adev->powerplay.pp_funcs = &pp_dpm_funcs;
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adev->powerplay.pp_funcs = &pp_dpm_funcs;
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