RDMA/efa: Add EFA device definitions
EFA PCIe device implements a single Admin Queue (AQ) and Admin Completion Queue (ACQ) pair to initialize and communicate configuration with the device. Through this pair, we run set/get commands for querying and configuring the device, create/modify/destroy queues, and IB specific commands like Address Handler (AH), Memory Registration (MR) and Protection Domains (PD). In addition to admin (AQ/ACQ), we have data path queues that get classified as Queue Pairs (QP) and Completion Queues (CQ). Signed-off-by: Gal Pressman <galpress@amazon.com> Reviewed-by: Shiraz Saleem <shiraz.saleem@intel.com> Reviewed-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Gal Pressman
Jason Gunthorpe
parent
f95be3d28d
commit
01edac3aa2
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/*
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* Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
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*/
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#ifndef _EFA_ADMIN_CMDS_H_
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#define _EFA_ADMIN_CMDS_H_
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#define EFA_ADMIN_API_VERSION_MAJOR 0
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#define EFA_ADMIN_API_VERSION_MINOR 1
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/* EFA admin queue opcodes */
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enum efa_admin_aq_opcode {
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EFA_ADMIN_CREATE_QP = 1,
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EFA_ADMIN_MODIFY_QP = 2,
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EFA_ADMIN_QUERY_QP = 3,
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EFA_ADMIN_DESTROY_QP = 4,
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EFA_ADMIN_CREATE_AH = 5,
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EFA_ADMIN_DESTROY_AH = 6,
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EFA_ADMIN_REG_MR = 7,
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EFA_ADMIN_DEREG_MR = 8,
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EFA_ADMIN_CREATE_CQ = 9,
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EFA_ADMIN_DESTROY_CQ = 10,
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EFA_ADMIN_GET_FEATURE = 11,
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EFA_ADMIN_SET_FEATURE = 12,
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EFA_ADMIN_GET_STATS = 13,
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EFA_ADMIN_ALLOC_PD = 14,
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EFA_ADMIN_DEALLOC_PD = 15,
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EFA_ADMIN_ALLOC_UAR = 16,
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EFA_ADMIN_DEALLOC_UAR = 17,
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EFA_ADMIN_MAX_OPCODE = 17,
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};
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enum efa_admin_aq_feature_id {
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EFA_ADMIN_DEVICE_ATTR = 1,
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EFA_ADMIN_AENQ_CONFIG = 2,
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EFA_ADMIN_NETWORK_ATTR = 3,
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EFA_ADMIN_QUEUE_ATTR = 4,
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EFA_ADMIN_HW_HINTS = 5,
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EFA_ADMIN_FEATURES_OPCODE_NUM = 8,
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};
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/* QP transport type */
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enum efa_admin_qp_type {
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/* Unreliable Datagram */
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EFA_ADMIN_QP_TYPE_UD = 1,
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/* Scalable Reliable Datagram */
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EFA_ADMIN_QP_TYPE_SRD = 2,
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};
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/* QP state */
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enum efa_admin_qp_state {
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EFA_ADMIN_QP_STATE_RESET = 0,
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EFA_ADMIN_QP_STATE_INIT = 1,
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EFA_ADMIN_QP_STATE_RTR = 2,
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EFA_ADMIN_QP_STATE_RTS = 3,
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EFA_ADMIN_QP_STATE_SQD = 4,
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EFA_ADMIN_QP_STATE_SQE = 5,
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EFA_ADMIN_QP_STATE_ERR = 6,
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};
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enum efa_admin_get_stats_type {
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EFA_ADMIN_GET_STATS_TYPE_BASIC = 0,
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};
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enum efa_admin_get_stats_scope {
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EFA_ADMIN_GET_STATS_SCOPE_ALL = 0,
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EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1,
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};
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enum efa_admin_modify_qp_mask_bits {
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EFA_ADMIN_QP_STATE_BIT = 0,
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EFA_ADMIN_CUR_QP_STATE_BIT = 1,
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EFA_ADMIN_QKEY_BIT = 2,
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EFA_ADMIN_SQ_PSN_BIT = 3,
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EFA_ADMIN_SQ_DRAINED_ASYNC_NOTIFY_BIT = 4,
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};
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/*
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* QP allocation sizes, converted by fabric QueuePair (QP) create command
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* from QP capabilities.
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*/
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struct efa_admin_qp_alloc_size {
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/* Send descriptor ring size in bytes */
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u32 send_queue_ring_size;
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/* Max number of WQEs that can be outstanding on send queue. */
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u32 send_queue_depth;
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/*
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* Recv descriptor ring size in bytes, sufficient for user-provided
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* number of WQEs
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*/
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u32 recv_queue_ring_size;
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/* Max number of WQEs that can be outstanding on recv queue */
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u32 recv_queue_depth;
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};
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struct efa_admin_create_qp_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* Protection Domain associated with this QP */
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u16 pd;
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/* QP type */
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u8 qp_type;
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/*
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* 0 : sq_virt - If set, SQ ring base address is
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* virtual (IOVA returned by MR registration)
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* 1 : rq_virt - If set, RQ ring base address is
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* virtual (IOVA returned by MR registration)
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* 7:2 : reserved - MBZ
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*/
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u8 flags;
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/*
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* Send queue (SQ) ring base physical address. This field is not
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* used if this is a Low Latency Queue(LLQ).
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*/
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u64 sq_base_addr;
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/* Receive queue (RQ) ring base address. */
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u64 rq_base_addr;
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/* Index of CQ to be associated with Send Queue completions */
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u32 send_cq_idx;
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/* Index of CQ to be associated with Recv Queue completions */
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u32 recv_cq_idx;
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/*
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* Memory registration key for the SQ ring, used only when not in
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* LLQ mode and base address is virtual
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*/
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u32 sq_l_key;
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/*
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* Memory registration key for the RQ ring, used only when base
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* address is virtual
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*/
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u32 rq_l_key;
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/* Requested QP allocation sizes */
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struct efa_admin_qp_alloc_size qp_alloc_size;
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/* UAR number */
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u16 uar;
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/* MBZ */
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u16 reserved;
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/* MBZ */
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u32 reserved2;
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};
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struct efa_admin_create_qp_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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/* Opaque handle to be used for consequent operations on the QP */
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u32 qp_handle;
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/* QP number in the given EFA virtual device */
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u16 qp_num;
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/* MBZ */
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u16 reserved;
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/* Index of sub-CQ for Send Queue completions */
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u16 send_sub_cq_idx;
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/* Index of sub-CQ for Receive Queue completions */
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u16 recv_sub_cq_idx;
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/* SQ doorbell address, as offset to PCIe DB BAR */
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u32 sq_db_offset;
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/* RQ doorbell address, as offset to PCIe DB BAR */
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u32 rq_db_offset;
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/*
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* low latency send queue ring base address as an offset to PCIe
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* MMIO LLQ_MEM BAR
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*/
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u32 llq_descriptors_offset;
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};
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struct efa_admin_modify_qp_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/*
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* Mask indicating which fields should be updated see enum
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* efa_admin_modify_qp_mask_bits
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*/
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u32 modify_mask;
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/* QP handle returned by create_qp command */
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u32 qp_handle;
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/* QP state */
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u32 qp_state;
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/* Override current QP state (before applying the transition) */
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u32 cur_qp_state;
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/* QKey */
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u32 qkey;
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/* SQ PSN */
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u32 sq_psn;
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/* Enable async notification when SQ is drained */
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u8 sq_drained_async_notify;
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/* MBZ */
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u8 reserved1;
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/* MBZ */
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u16 reserved2;
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};
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struct efa_admin_modify_qp_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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struct efa_admin_query_qp_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* QP handle returned by create_qp command */
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u32 qp_handle;
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};
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struct efa_admin_query_qp_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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/* QP state */
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u32 qp_state;
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/* QKey */
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u32 qkey;
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/* SQ PSN */
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u32 sq_psn;
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/* Indicates that draining is in progress */
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u8 sq_draining;
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/* MBZ */
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u8 reserved1;
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/* MBZ */
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u16 reserved2;
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};
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struct efa_admin_destroy_qp_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* QP handle returned by create_qp command */
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u32 qp_handle;
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};
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struct efa_admin_destroy_qp_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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/*
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* Create Address Handle command parameters. Must not be called more than
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* once for the same destination
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*/
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struct efa_admin_create_ah_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* Destination address in network byte order */
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u8 dest_addr[16];
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/* PD number */
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u16 pd;
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u16 reserved;
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};
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struct efa_admin_create_ah_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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/* Target interface address handle (opaque) */
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u16 ah;
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u16 reserved;
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};
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struct efa_admin_destroy_ah_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* Target interface address handle (opaque) */
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u16 ah;
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/* PD number */
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u16 pd;
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};
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struct efa_admin_destroy_ah_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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/*
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* Registration of MemoryRegion, required for QP working with Virtual
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* Addresses. In standard verbs semantics, region length is limited to 2GB
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* space, but EFA offers larger MR support for large memory space, to ease
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* on users working with very large datasets (i.e. full GPU memory mapping).
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*/
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struct efa_admin_reg_mr_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* Protection Domain */
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u16 pd;
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/* MBZ */
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u16 reserved16_w1;
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/* Physical Buffer List, each element is page-aligned. */
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union {
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/*
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* Inline array of guest-physical page addresses of user
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* memory pages (optimization for short region
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* registrations)
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*/
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u64 inline_pbl_array[4];
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/* points to PBL (direct or indirect, chained if needed) */
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struct efa_admin_ctrl_buff_info pbl;
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} pbl;
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/* Memory region length, in bytes. */
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u64 mr_length;
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/*
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* flags and page size
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* 4:0 : phys_page_size_shift - page size is (1 <<
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* phys_page_size_shift). Page size is used for
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* building the Virtual to Physical address mapping
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* 6:5 : reserved - MBZ
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* 7 : mem_addr_phy_mode_en - Enable bit for physical
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* memory registration (no translation), can be used
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* only by privileged clients. If set, PBL must
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* contain a single entry.
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*/
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u8 flags;
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/*
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* permissions
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* 0 : local_write_enable - Write permissions: value
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* of 1 needed for RQ buffers and for RDMA write
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* 7:1 : reserved1 - remote access flags, etc
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*/
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u8 permissions;
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u16 reserved16_w5;
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/* number of pages in PBL (redundant, could be calculated) */
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u32 page_num;
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/*
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* IO Virtual Address associated with this MR. If
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* mem_addr_phy_mode_en is set, contains the physical address of
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* the region.
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*/
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u64 iova;
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};
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struct efa_admin_reg_mr_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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/*
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* L_Key, to be used in conjunction with local buffer references in
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* SQ and RQ WQE, or with virtual RQ/CQ rings
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*/
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u32 l_key;
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/*
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* R_Key, to be used in RDMA messages to refer to remotely accessed
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* memory region
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*/
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u32 r_key;
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};
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struct efa_admin_dereg_mr_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* L_Key, memory region's l_key */
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u32 l_key;
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};
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struct efa_admin_dereg_mr_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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struct efa_admin_create_cq_cmd {
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struct efa_admin_aq_common_desc aq_common_desc;
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/*
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* 4:0 : reserved5
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* 5 : interrupt_mode_enabled - if set, cq operates
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* in interrupt mode (i.e. CQ events and MSI-X are
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* generated), otherwise - polling
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* 6 : virt - If set, ring base address is virtual
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* (IOVA returned by MR registration)
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* 7 : reserved6
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*/
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u8 cq_caps_1;
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/*
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* 4:0 : cq_entry_size_words - size of CQ entry in
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* 32-bit words, valid values: 4, 8.
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* 7:5 : reserved7
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*/
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u8 cq_caps_2;
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/* completion queue depth in # of entries. must be power of 2 */
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u16 cq_depth;
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/* msix vector assigned to this cq */
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u32 msix_vector_idx;
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/*
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* CQ ring base address, virtual or physical depending on 'virt'
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* flag
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*/
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struct efa_common_mem_addr cq_ba;
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/*
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* Memory registration key for the ring, used only when base
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* address is virtual
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*/
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u32 l_key;
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/*
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* number of sub cqs - must be equal to sub_cqs_per_cq of queue
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* attributes.
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*/
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u16 num_sub_cqs;
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/* UAR number */
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u16 uar;
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};
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struct efa_admin_create_cq_resp {
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struct efa_admin_acq_common_desc acq_common_desc;
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u16 cq_idx;
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/* actual cq depth in number of entries */
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u16 cq_actual_depth;
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};
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struct efa_admin_destroy_cq_cmd {
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struct efa_admin_aq_common_desc aq_common_desc;
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u16 cq_idx;
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u16 reserved1;
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};
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struct efa_admin_destroy_cq_resp {
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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/*
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* EFA AQ Get Statistics command. Extended statistics are placed in control
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* buffer pointed by AQ entry
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*/
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struct efa_admin_aq_get_stats_cmd {
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struct efa_admin_aq_common_desc aq_common_descriptor;
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union {
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/* command specific inline data */
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u32 inline_data_w1[3];
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struct efa_admin_ctrl_buff_info control_buffer;
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} u;
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/* stats type as defined in enum efa_admin_get_stats_type */
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u8 type;
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/* stats scope defined in enum efa_admin_get_stats_scope */
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u8 scope;
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u16 scope_modifier;
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};
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struct efa_admin_basic_stats {
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u64 tx_bytes;
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u64 tx_pkts;
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|
||||
u64 rx_bytes;
|
||||
|
||||
u64 rx_pkts;
|
||||
|
||||
u64 rx_drops;
|
||||
};
|
||||
|
||||
struct efa_admin_acq_get_stats_resp {
|
||||
struct efa_admin_acq_common_desc acq_common_desc;
|
||||
|
||||
struct efa_admin_basic_stats basic_stats;
|
||||
};
|
||||
|
||||
struct efa_admin_get_set_feature_common_desc {
|
||||
/*
|
||||
* 1:0 : select - 0x1 - current value; 0x3 - default
|
||||
* value
|
||||
* 7:3 : reserved3
|
||||
*/
|
||||
u8 flags;
|
||||
|
||||
/* as appears in efa_admin_aq_feature_id */
|
||||
u8 feature_id;
|
||||
|
||||
/* MBZ */
|
||||
u16 reserved16;
|
||||
};
|
||||
|
||||
struct efa_admin_feature_device_attr_desc {
|
||||
/* Bitmap of efa_admin_aq_feature_id */
|
||||
u64 supported_features;
|
||||
|
||||
/* Bitmap of supported page sizes in MR registrations */
|
||||
u64 page_size_cap;
|
||||
|
||||
u32 fw_version;
|
||||
|
||||
u32 admin_api_version;
|
||||
|
||||
u32 device_version;
|
||||
|
||||
/* Bar used for SQ and RQ doorbells */
|
||||
u16 db_bar;
|
||||
|
||||
/* Indicates how many bits are used physical address access */
|
||||
u8 phys_addr_width;
|
||||
|
||||
/* Indicates how many bits are used virtual address access */
|
||||
u8 virt_addr_width;
|
||||
};
|
||||
|
||||
struct efa_admin_feature_queue_attr_desc {
|
||||
/* The maximum number of queue pairs supported */
|
||||
u32 max_qp;
|
||||
|
||||
u32 max_sq_depth;
|
||||
|
||||
/* max send wr used in inline-buf */
|
||||
u32 inline_buf_size;
|
||||
|
||||
u32 max_rq_depth;
|
||||
|
||||
/* The maximum number of completion queues supported per VF */
|
||||
u32 max_cq;
|
||||
|
||||
u32 max_cq_depth;
|
||||
|
||||
/* Number of sub-CQs to be created for each CQ */
|
||||
u16 sub_cqs_per_cq;
|
||||
|
||||
u16 reserved;
|
||||
|
||||
/*
|
||||
* Maximum number of SGEs (buffs) allowed for a single send work
|
||||
* queue element (WQE)
|
||||
*/
|
||||
u16 max_wr_send_sges;
|
||||
|
||||
/* Maximum number of SGEs allowed for a single recv WQE */
|
||||
u16 max_wr_recv_sges;
|
||||
|
||||
/* The maximum number of memory regions supported */
|
||||
u32 max_mr;
|
||||
|
||||
/* The maximum number of pages can be registered */
|
||||
u32 max_mr_pages;
|
||||
|
||||
/* The maximum number of protection domains supported */
|
||||
u32 max_pd;
|
||||
|
||||
/* The maximum number of address handles supported */
|
||||
u32 max_ah;
|
||||
|
||||
/* The maximum size of LLQ in bytes */
|
||||
u32 max_llq_size;
|
||||
};
|
||||
|
||||
struct efa_admin_feature_aenq_desc {
|
||||
/* bitmask for AENQ groups the device can report */
|
||||
u32 supported_groups;
|
||||
|
||||
/* bitmask for AENQ groups to report */
|
||||
u32 enabled_groups;
|
||||
};
|
||||
|
||||
struct efa_admin_feature_network_attr_desc {
|
||||
/* Raw address data in network byte order */
|
||||
u8 addr[16];
|
||||
|
||||
u32 mtu;
|
||||
};
|
||||
|
||||
/*
|
||||
* When hint value is 0, hints capabilities are not supported or driver
|
||||
* should use its own predefined value
|
||||
*/
|
||||
struct efa_admin_hw_hints {
|
||||
/* value in ms */
|
||||
u16 mmio_read_timeout;
|
||||
|
||||
/* value in ms */
|
||||
u16 driver_watchdog_timeout;
|
||||
|
||||
/* value in ms */
|
||||
u16 admin_completion_timeout;
|
||||
|
||||
/* poll interval in ms */
|
||||
u16 poll_interval;
|
||||
};
|
||||
|
||||
struct efa_admin_get_feature_cmd {
|
||||
struct efa_admin_aq_common_desc aq_common_descriptor;
|
||||
|
||||
struct efa_admin_ctrl_buff_info control_buffer;
|
||||
|
||||
struct efa_admin_get_set_feature_common_desc feature_common;
|
||||
|
||||
u32 raw[11];
|
||||
};
|
||||
|
||||
struct efa_admin_get_feature_resp {
|
||||
struct efa_admin_acq_common_desc acq_common_desc;
|
||||
|
||||
union {
|
||||
u32 raw[14];
|
||||
|
||||
struct efa_admin_feature_device_attr_desc device_attr;
|
||||
|
||||
struct efa_admin_feature_aenq_desc aenq;
|
||||
|
||||
struct efa_admin_feature_network_attr_desc network_attr;
|
||||
|
||||
struct efa_admin_feature_queue_attr_desc queue_attr;
|
||||
|
||||
struct efa_admin_hw_hints hw_hints;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct efa_admin_set_feature_cmd {
|
||||
struct efa_admin_aq_common_desc aq_common_descriptor;
|
||||
|
||||
struct efa_admin_ctrl_buff_info control_buffer;
|
||||
|
||||
struct efa_admin_get_set_feature_common_desc feature_common;
|
||||
|
||||
union {
|
||||
u32 raw[11];
|
||||
|
||||
/* AENQ configuration */
|
||||
struct efa_admin_feature_aenq_desc aenq;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct efa_admin_set_feature_resp {
|
||||
struct efa_admin_acq_common_desc acq_common_desc;
|
||||
|
||||
union {
|
||||
u32 raw[14];
|
||||
} u;
|
||||
};
|
||||
|
||||
struct efa_admin_alloc_pd_cmd {
|
||||
struct efa_admin_aq_common_desc aq_common_descriptor;
|
||||
};
|
||||
|
||||
struct efa_admin_alloc_pd_resp {
|
||||
struct efa_admin_acq_common_desc acq_common_desc;
|
||||
|
||||
/* PD number */
|
||||
u16 pd;
|
||||
|
||||
/* MBZ */
|
||||
u16 reserved;
|
||||
};
|
||||
|
||||
struct efa_admin_dealloc_pd_cmd {
|
||||
struct efa_admin_aq_common_desc aq_common_descriptor;
|
||||
|
||||
/* PD number */
|
||||
u16 pd;
|
||||
|
||||
/* MBZ */
|
||||
u16 reserved;
|
||||
};
|
||||
|
||||
struct efa_admin_dealloc_pd_resp {
|
||||
struct efa_admin_acq_common_desc acq_common_desc;
|
||||
};
|
||||
|
||||
struct efa_admin_alloc_uar_cmd {
|
||||
struct efa_admin_aq_common_desc aq_common_descriptor;
|
||||
};
|
||||
|
||||
struct efa_admin_alloc_uar_resp {
|
||||
struct efa_admin_acq_common_desc acq_common_desc;
|
||||
|
||||
/* UAR number */
|
||||
u16 uar;
|
||||
|
||||
/* MBZ */
|
||||
u16 reserved;
|
||||
};
|
||||
|
||||
struct efa_admin_dealloc_uar_cmd {
|
||||
struct efa_admin_aq_common_desc aq_common_descriptor;
|
||||
|
||||
/* UAR number */
|
||||
u16 uar;
|
||||
|
||||
/* MBZ */
|
||||
u16 reserved;
|
||||
};
|
||||
|
||||
struct efa_admin_dealloc_uar_resp {
|
||||
struct efa_admin_acq_common_desc acq_common_desc;
|
||||
};
|
||||
|
||||
/* asynchronous event notification groups */
|
||||
enum efa_admin_aenq_group {
|
||||
EFA_ADMIN_FATAL_ERROR = 1,
|
||||
EFA_ADMIN_WARNING = 2,
|
||||
EFA_ADMIN_NOTIFICATION = 3,
|
||||
EFA_ADMIN_KEEP_ALIVE = 4,
|
||||
EFA_ADMIN_AENQ_GROUPS_NUM = 5,
|
||||
};
|
||||
|
||||
enum efa_admin_aenq_notification_syndrom {
|
||||
EFA_ADMIN_SUSPEND = 0,
|
||||
EFA_ADMIN_RESUME = 1,
|
||||
EFA_ADMIN_UPDATE_HINTS = 2,
|
||||
};
|
||||
|
||||
struct efa_admin_mmio_req_read_less_resp {
|
||||
u16 req_id;
|
||||
|
||||
u16 reg_off;
|
||||
|
||||
/* value is valid when poll is cleared */
|
||||
u32 reg_val;
|
||||
};
|
||||
|
||||
/* create_qp_cmd */
|
||||
#define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0)
|
||||
#define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_SHIFT 1
|
||||
#define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1)
|
||||
|
||||
/* reg_mr_cmd */
|
||||
#define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0)
|
||||
#define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_SHIFT 7
|
||||
#define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7)
|
||||
#define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0)
|
||||
|
||||
/* create_cq_cmd */
|
||||
#define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
|
||||
#define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
|
||||
#define EFA_ADMIN_CREATE_CQ_CMD_VIRT_SHIFT 6
|
||||
#define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6)
|
||||
#define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
|
||||
|
||||
/* get_set_feature_common_desc */
|
||||
#define EFA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
|
||||
|
||||
#endif /* _EFA_ADMIN_CMDS_H_ */
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _EFA_ADMIN_H_
|
||||
#define _EFA_ADMIN_H_
|
||||
|
||||
enum efa_admin_aq_completion_status {
|
||||
EFA_ADMIN_SUCCESS = 0,
|
||||
EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
|
||||
EFA_ADMIN_BAD_OPCODE = 2,
|
||||
EFA_ADMIN_UNSUPPORTED_OPCODE = 3,
|
||||
EFA_ADMIN_MALFORMED_REQUEST = 4,
|
||||
/* Additional status is provided in ACQ entry extended_status */
|
||||
EFA_ADMIN_ILLEGAL_PARAMETER = 5,
|
||||
EFA_ADMIN_UNKNOWN_ERROR = 6,
|
||||
EFA_ADMIN_RESOURCE_BUSY = 7,
|
||||
};
|
||||
|
||||
struct efa_admin_aq_common_desc {
|
||||
/*
|
||||
* 11:0 : command_id
|
||||
* 15:12 : reserved12
|
||||
*/
|
||||
u16 command_id;
|
||||
|
||||
/* as appears in efa_admin_aq_opcode */
|
||||
u8 opcode;
|
||||
|
||||
/*
|
||||
* 0 : phase
|
||||
* 1 : ctrl_data - control buffer address valid
|
||||
* 2 : ctrl_data_indirect - control buffer address
|
||||
* points to list of pages with addresses of control
|
||||
* buffers
|
||||
* 7:3 : reserved3
|
||||
*/
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
/*
|
||||
* used in efa_admin_aq_entry. Can point directly to control data, or to a
|
||||
* page list chunk. Used also at the end of indirect mode page list chunks,
|
||||
* for chaining.
|
||||
*/
|
||||
struct efa_admin_ctrl_buff_info {
|
||||
u32 length;
|
||||
|
||||
struct efa_common_mem_addr address;
|
||||
};
|
||||
|
||||
struct efa_admin_aq_entry {
|
||||
struct efa_admin_aq_common_desc aq_common_descriptor;
|
||||
|
||||
union {
|
||||
u32 inline_data_w1[3];
|
||||
|
||||
struct efa_admin_ctrl_buff_info control_buffer;
|
||||
} u;
|
||||
|
||||
u32 inline_data_w4[12];
|
||||
};
|
||||
|
||||
struct efa_admin_acq_common_desc {
|
||||
/*
|
||||
* command identifier to associate it with the aq descriptor
|
||||
* 11:0 : command_id
|
||||
* 15:12 : reserved12
|
||||
*/
|
||||
u16 command;
|
||||
|
||||
u8 status;
|
||||
|
||||
/*
|
||||
* 0 : phase
|
||||
* 7:1 : reserved1
|
||||
*/
|
||||
u8 flags;
|
||||
|
||||
u16 extended_status;
|
||||
|
||||
/*
|
||||
* indicates to the driver which AQ entry has been consumed by the
|
||||
* device and could be reused
|
||||
*/
|
||||
u16 sq_head_indx;
|
||||
};
|
||||
|
||||
struct efa_admin_acq_entry {
|
||||
struct efa_admin_acq_common_desc acq_common_descriptor;
|
||||
|
||||
u32 response_specific_data[14];
|
||||
};
|
||||
|
||||
struct efa_admin_aenq_common_desc {
|
||||
u16 group;
|
||||
|
||||
u16 syndrom;
|
||||
|
||||
/*
|
||||
* 0 : phase
|
||||
* 7:1 : reserved - MBZ
|
||||
*/
|
||||
u8 flags;
|
||||
|
||||
u8 reserved1[3];
|
||||
|
||||
u32 timestamp_low;
|
||||
|
||||
u32 timestamp_high;
|
||||
};
|
||||
|
||||
struct efa_admin_aenq_entry {
|
||||
struct efa_admin_aenq_common_desc aenq_common_desc;
|
||||
|
||||
/* command specific inline data */
|
||||
u32 inline_data_w4[12];
|
||||
};
|
||||
|
||||
/* aq_common_desc */
|
||||
#define EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
|
||||
#define EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
|
||||
#define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
|
||||
#define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
|
||||
#define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
|
||||
#define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
|
||||
|
||||
/* acq_common_desc */
|
||||
#define EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
|
||||
#define EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
|
||||
|
||||
/* aenq_common_desc */
|
||||
#define EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
|
||||
|
||||
#endif /* _EFA_ADMIN_H_ */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _EFA_COMMON_H_
|
||||
#define _EFA_COMMON_H_
|
||||
|
||||
#define EFA_COMMON_SPEC_VERSION_MAJOR 2
|
||||
#define EFA_COMMON_SPEC_VERSION_MINOR 0
|
||||
|
||||
struct efa_common_mem_addr {
|
||||
u32 mem_addr_low;
|
||||
|
||||
u32 mem_addr_high;
|
||||
};
|
||||
|
||||
#endif /* _EFA_COMMON_H_ */
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _EFA_REGS_H_
|
||||
#define _EFA_REGS_H_
|
||||
|
||||
enum efa_regs_reset_reason_types {
|
||||
EFA_REGS_RESET_NORMAL = 0,
|
||||
/* Keep alive timeout */
|
||||
EFA_REGS_RESET_KEEP_ALIVE_TO = 1,
|
||||
EFA_REGS_RESET_ADMIN_TO = 2,
|
||||
EFA_REGS_RESET_INIT_ERR = 3,
|
||||
EFA_REGS_RESET_DRIVER_INVALID_STATE = 4,
|
||||
EFA_REGS_RESET_OS_TRIGGER = 5,
|
||||
EFA_REGS_RESET_SHUTDOWN = 6,
|
||||
EFA_REGS_RESET_USER_TRIGGER = 7,
|
||||
EFA_REGS_RESET_GENERIC = 8,
|
||||
};
|
||||
|
||||
/* efa_registers offsets */
|
||||
|
||||
/* 0 base */
|
||||
#define EFA_REGS_VERSION_OFF 0x0
|
||||
#define EFA_REGS_CONTROLLER_VERSION_OFF 0x4
|
||||
#define EFA_REGS_CAPS_OFF 0x8
|
||||
#define EFA_REGS_AQ_BASE_LO_OFF 0x10
|
||||
#define EFA_REGS_AQ_BASE_HI_OFF 0x14
|
||||
#define EFA_REGS_AQ_CAPS_OFF 0x18
|
||||
#define EFA_REGS_ACQ_BASE_LO_OFF 0x20
|
||||
#define EFA_REGS_ACQ_BASE_HI_OFF 0x24
|
||||
#define EFA_REGS_ACQ_CAPS_OFF 0x28
|
||||
#define EFA_REGS_AQ_PROD_DB_OFF 0x2c
|
||||
#define EFA_REGS_AENQ_CAPS_OFF 0x34
|
||||
#define EFA_REGS_AENQ_BASE_LO_OFF 0x38
|
||||
#define EFA_REGS_AENQ_BASE_HI_OFF 0x3c
|
||||
#define EFA_REGS_AENQ_CONS_DB_OFF 0x40
|
||||
#define EFA_REGS_INTR_MASK_OFF 0x4c
|
||||
#define EFA_REGS_DEV_CTL_OFF 0x54
|
||||
#define EFA_REGS_DEV_STS_OFF 0x58
|
||||
#define EFA_REGS_MMIO_REG_READ_OFF 0x5c
|
||||
#define EFA_REGS_MMIO_RESP_LO_OFF 0x60
|
||||
#define EFA_REGS_MMIO_RESP_HI_OFF 0x64
|
||||
|
||||
/* version register */
|
||||
#define EFA_REGS_VERSION_MINOR_VERSION_MASK 0xff
|
||||
#define EFA_REGS_VERSION_MAJOR_VERSION_SHIFT 8
|
||||
#define EFA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00
|
||||
|
||||
/* controller_version register */
|
||||
#define EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff
|
||||
#define EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8
|
||||
#define EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00
|
||||
#define EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16
|
||||
#define EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000
|
||||
#define EFA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24
|
||||
#define EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000
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/* caps register */
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#define EFA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1
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#define EFA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1
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#define EFA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
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#define EFA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8
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#define EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
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#define EFA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16
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#define EFA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
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/* aq_caps register */
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#define EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
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#define EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16
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#define EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000
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/* acq_caps register */
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#define EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff
|
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#define EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16
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#define EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xff0000
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#define EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_SHIFT 24
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#define EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK 0xff000000
|
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|
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/* aenq_caps register */
|
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#define EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff
|
||||
#define EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16
|
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#define EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xff0000
|
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#define EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_SHIFT 24
|
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#define EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK 0xff000000
|
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|
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/* dev_ctl register */
|
||||
#define EFA_REGS_DEV_CTL_DEV_RESET_MASK 0x1
|
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#define EFA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1
|
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#define EFA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2
|
||||
#define EFA_REGS_DEV_CTL_RESET_REASON_SHIFT 28
|
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#define EFA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000
|
||||
|
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/* dev_sts register */
|
||||
#define EFA_REGS_DEV_STS_READY_MASK 0x1
|
||||
#define EFA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1
|
||||
#define EFA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2
|
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#define EFA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2
|
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#define EFA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4
|
||||
#define EFA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3
|
||||
#define EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8
|
||||
#define EFA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4
|
||||
#define EFA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10
|
||||
#define EFA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5
|
||||
#define EFA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20
|
||||
|
||||
/* mmio_reg_read register */
|
||||
#define EFA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff
|
||||
#define EFA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16
|
||||
#define EFA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000
|
||||
|
||||
#endif /* _EFA_REGS_H_ */
|
||||
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Reference in New Issue