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drm/i915: Use cached cdclk value 

Rather than reading out the current cdclk value use the cached value we
have tucked away in dev_priv.

v2: Rebased to the latest
v3: Rebased to the latest
v4: Fix for patch style problems

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2015-06-03 15:45:08 +03:00 committed by Jani Nikula
parent b6283055b4
commit 05024da3c2
3 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/intel_display.c
View File

@ -6610,8 +6610,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
/* FIXME should check pixel clock limits on all platforms */
if (INTEL_INFO(dev)->gen < 4) {
int clock_limit =
dev_priv->display.get_display_clock_speed(dev);
int clock_limit = dev_priv->cdclk_freq;
/*
* Enable pixel doubling when the dot clock

5
drivers/gpu/drm/i915/intel_dp.c
View File

@ -710,7 +710,8 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
return 0;
if (intel_dig_port->port == PORT_A) {
return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
} else {
return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
}
@ -725,7 +726,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
if (intel_dig_port->port == PORT_A) {
if (index)
return 0;
return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
/* Workaround for non-ULT HSW */
switch (index) {

2
drivers/gpu/drm/i915/intel_pm.c
View File

@ -1815,7 +1815,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
mode->crtc_clock);
ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
dev_priv->display.get_display_clock_speed(dev_priv->dev));
dev_priv->cdclk_freq);
return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
PIPE_WM_LINETIME_TIME(linetime);