arm64 fixes:
- SPsel register initialisation on reset as the architecture defines its state as unknown - Use READ_ONCE when dereferencing pmd_t pointers to avoid race conditions in page_vma_mapped_walk() (or fast GUP) with concurrent modifications of the page table - Avoid invoking the mm fault handling code for kernel addresses (check against TASK_SIZE) which would otherwise result in calling might_sleep() in atomic context -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAlnOfcoACgkQa9axLQDI XvElRQ//ciHbKkJpjJdbWPRaWPfqPrOlbnWNJ4ZC2ydgd8gz5aUqCidlZGStxu0s 27+z1dtN+Yb6/oEYs90wgGTXkXl1Tc46mv/9jdpW97ERcpWb+X4iJJ0J4olDR7l0 k+p1c//bda961mg+ZoSh6NJFO5X8BfXiistBOicS8mXrMEF5B6bk/Qc7Y0cKSSZ8 wrZSOfvbIWi2kD2UqUz1H6UxyafgrYjcbLyJcUoquRz28eBGEYY4dNcLmUEIzon+ LxVhoVc0KshX/O0wkUNA7z2SxxBxy8kqRDrmJyIgC/HsuehxTYLDgEvJnYc3+hdP Xy9exrl2UQFkjU0ZfGgWVpScvOB9xqg16uqPpSukIa1jW88VfkvLDHz5TIeIOl6s sjkzUFbtLZNfgC43qKieQhIRMnaJZiRXdZMFSV6SI3R9YsZWTWnP1HYIh9U1tgHH WqUZrswsg2EM1VJksQpnE+e04//7KvKjfBvtjzEU7dYwTbXheQb+3IzPjxe2jrl4 T/ZicpE7eViTM83rE33kZoxK2tbDoq7/iBq8qXq8mgVM0P7FQgtYFpBhTGai1Ash K7lzNOUpUBfg8Mx2MWcw6pmgkLO3Pd8C2iyljrSZCLZmgD5VTHjZfCqtVOfd3Ld9 v42wZj8ap+XIqZDzV+xSmil6700msNACMzYC8AcX97QixF7V6aA= =zqDu -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Catalin Marinas: - SPsel register initialisation on reset as the architecture defines its state as unknown - Use READ_ONCE when dereferencing pmd_t pointers to avoid race conditions in page_vma_mapped_walk() (or fast GUP) with concurrent modifications of the page table - Avoid invoking the mm fault handling code for kernel addresses (check against TASK_SIZE) which would otherwise result in calling might_sleep() in atomic context * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: fault: Route pte translation faults via do_translation_fault arm64: mm: Use READ_ONCE when dereferencing pointer to pte table arm64: Make sure SPsel is always set
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commit
0648260041
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@ -401,7 +401,7 @@ static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
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/* Find an entry in the third-level page table. */
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#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t))
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#define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
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#define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))
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#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
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@ -384,6 +384,7 @@ ENTRY(kimage_vaddr)
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* booted in EL1 or EL2 respectively.
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*/
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ENTRY(el2_setup)
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msr SPsel, #1 // We want to use SP_EL{1,2}
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mrs x0, CurrentEL
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cmp x0, #CurrentEL_EL2
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b.eq 1f
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@ -651,7 +651,7 @@ static const struct fault_info fault_info[] = {
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{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },
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{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
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{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
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{ do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
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{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
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{ do_bad, SIGBUS, 0, "unknown 8" },
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{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
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{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
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