ARM: hisi: enable hix5hd2 SoC
Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series support both single and dual Cortex-A9 cores. Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx. They are different in implementation such as SMP, IPs integarted and earlycon configure. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Jiancheng Xue <jchxue@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Haifeng Yan
Olof Johansson
parent
7685b125ca
commit
06cc5c1d4d
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@ -31,6 +31,17 @@ Example:
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reboot-offset = <0x4>;
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};
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-----------------------------------------------------------------------
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Hisilicon CPU controller
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Required properties:
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- compatible : "hisilicon,cpuctrl"
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- reg : Register address and size
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The clock registers and power registers of secondary cores are defined
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in CPU controller, especially in HIX5HD2 SoC.
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-----------------------------------------------------------------------
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PCTRL: Peripheral misc control register
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Required Properties:
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@ -10,15 +10,24 @@ if ARCH_HISI
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menu "Hisilicon platform type"
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config ARCH_HI3xxx
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bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
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bool "Hisilicon Hi36xx family" if ARCH_MULTI_V7
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select CACHE_L2X0
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select PINCTRL
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select PINCTRL_SINGLE
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help
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Support for Hisilicon Hi36xx/Hi37xx processor family
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Support for Hisilicon Hi36xx SoC family
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config ARCH_HIX5HD2
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bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7
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select CACHE_L2X0
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select PINCTRL
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select PINCTRL_SINGLE
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help
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Support for Hisilicon HIX5HD2 SoC family
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endmenu
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endif
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@ -3,4 +3,4 @@
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#
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obj-y += hisilicon.o
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obj-$(CONFIG_SMP) += platsmp.o hotplug.o
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obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o
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@ -12,4 +12,9 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
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extern int hi3xxx_cpu_kill(unsigned int cpu);
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extern void hi3xxx_set_cpu(int cpu, bool enable);
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extern void hix5hd2_secondary_startup(void);
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extern struct smp_operations hix5hd2_smp_ops;
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extern void hix5hd2_set_cpu(int cpu, bool enable);
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extern void hix5hd2_cpu_die(unsigned int cpu);
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#endif
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@ -0,0 +1,16 @@
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/*
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* Copyright (c) 2014 Hisilicon Limited.
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* Copyright (c) 2014 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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__CPUINIT
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ENTRY(hix5hd2_secondary_startup)
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bl v7_invalidate_l1
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b secondary_startup
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@ -88,3 +88,15 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
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.smp = smp_ops(hi3xxx_smp_ops),
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.restart = hi3xxx_restart,
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MACHINE_END
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static const char *hix5hd2_compat[] __initconst = {
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"hisilicon,hix5hd2",
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NULL,
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};
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DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
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.dt_compat = hix5hd2_compat,
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.init_late = hi3xxx_init_late,
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.smp = smp_ops(hix5hd2_smp_ops),
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.restart = hi3xxx_restart,
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MACHINE_END
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@ -57,6 +57,14 @@
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#define CPU0_NEON_SRST_REQ_EN (1 << 4)
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#define CPU0_SRST_REQ_EN (1 << 0)
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#define HIX5HD2_PERI_CRG20 0x50
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#define CRG20_CPU1_RESET (1 << 17)
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#define HIX5HD2_PERI_PMC0 0x1000
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#define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
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#define PMC0_CPU1_PMC_ENABLE (1 << 7)
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#define PMC0_CPU1_POWERDOWN (1 << 3)
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enum {
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HI3620_CTRL,
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ERROR_CTRL,
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@ -157,6 +165,50 @@ void hi3xxx_set_cpu(int cpu, bool enable)
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set_cpu_hi3620(cpu, enable);
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}
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static bool hix5hd2_hotplug_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
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if (np) {
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ctrl_base = of_iomap(np, 0);
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return true;
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}
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return false;
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}
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void hix5hd2_set_cpu(int cpu, bool enable)
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{
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u32 val = 0;
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if (!ctrl_base)
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if (!hix5hd2_hotplug_init())
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BUG();
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if (enable) {
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/* power on cpu1 */
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val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
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val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
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val |= PMC0_CPU1_PMC_ENABLE;
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writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
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/* unreset */
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val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
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val &= ~CRG20_CPU1_RESET;
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writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
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} else {
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/* power down cpu1 */
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val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
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val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
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val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
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writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
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/* reset */
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val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
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val |= CRG20_CPU1_RESET;
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writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
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}
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}
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static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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@ -199,4 +251,10 @@ int hi3xxx_cpu_kill(unsigned int cpu)
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hi3xxx_set_cpu(cpu, false);
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return 1;
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}
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void hix5hd2_cpu_die(unsigned int cpu)
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{
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flush_cache_all();
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hix5hd2_set_cpu(cpu, false);
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}
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#endif
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@ -17,6 +17,8 @@
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#include "core.h"
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#define HIX5HD2_BOOT_ADDRESS 0xffff0000
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static void __iomem *ctrl_base;
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void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
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@ -35,11 +37,9 @@ int hi3xxx_get_cpu_jump(int cpu)
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return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
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}
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static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
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static void __init hisi_enable_scu_a9(void)
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{
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struct device_node *np = NULL;
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unsigned long base = 0;
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u32 offset = 0;
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void __iomem *scu_base = NULL;
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if (scu_a9_has_base()) {
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@ -52,6 +52,14 @@ static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
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scu_enable(scu_base);
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iounmap(scu_base);
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}
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}
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static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np = NULL;
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u32 offset = 0;
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hisi_enable_scu_a9();
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if (!ctrl_base) {
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np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
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if (!np) {
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@ -87,3 +95,39 @@ struct smp_operations hi3xxx_smp_ops __initdata = {
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.cpu_kill = hi3xxx_cpu_kill,
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#endif
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};
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static void __init hix5hd2_smp_prepare_cpus(unsigned int max_cpus)
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{
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hisi_enable_scu_a9();
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}
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void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
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{
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void __iomem *virt;
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virt = ioremap(start_addr, PAGE_SIZE);
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writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
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writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
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iounmap(virt);
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}
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static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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phys_addr_t jumpaddr;
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jumpaddr = virt_to_phys(hix5hd2_secondary_startup);
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hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
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hix5hd2_set_cpu(cpu, true);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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struct smp_operations hix5hd2_smp_ops __initdata = {
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.smp_prepare_cpus = hix5hd2_smp_prepare_cpus,
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.smp_boot_secondary = hix5hd2_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = hix5hd2_cpu_die,
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#endif
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};
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