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ARM: mediatek: add UART dts for mt8127 and mt8135 

This add dts support for mt8127 and mt8135 SOC UART

Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Eddie Huang 2014-10-22 15:12:00 +02:00 committed by Matthias Brugger
parent e0bed07745
commit 0714947369
2 changed files with 78 additions and 0 deletions
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38
arch/arm/boot/dts/mt8127.dtsi
View File

@ -64,6 +64,12 @@ rtc_clk: dummy32k {
clock-frequency = <32000>;
#clock-cells = <0>;
};
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
};
soc {
@ -100,5 +106,37 @@ gic: interrupt-controller@10211000 {
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
uart0: serial@11006000 {
compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@11007000 {
compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@11008000 {
compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart3: serial@11009000 {
compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
};
};

40
arch/arm/boot/dts/mt8135.dtsi
View File

@ -86,6 +86,13 @@ rtc_clk: dummy32k {
clock-frequency = <32000>;
#clock-cells = <0>;
};
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
};
soc {
@ -122,5 +129,38 @@ gic: interrupt-controller@10211000 {
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
uart0: serial@11006000 {
compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
reg = <0 0x11006000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@11007000 {
compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
reg = <0 0x11007000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@11008000 {
compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
reg = <0 0x11008000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart3: serial@11009000 {
compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
reg = <0 0x11009000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
};
};