spi: Add YAML schemas for the generic SPI options
The SPI controllers have a bunch of generic options that are needed in a device tree. Add a YAML schemas for those. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Maxime Ripard
Mark Brown
parent
9783da2384
commit
0a1b929356
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SPI (Serial Peripheral Interface) busses
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This file has moved to spi-controller.yaml.
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SPI busses can be described with a node for the SPI controller device
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and a set of child nodes for each SPI slave on the bus. The system's SPI
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controller may be described for use in SPI master mode or in SPI slave mode,
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but not for both at the same time.
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The SPI controller node requires the following properties:
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- compatible - Name of SPI bus controller following generic names
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recommended practice.
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In master mode, the SPI controller node requires the following additional
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properties:
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- #address-cells - number of cells required to define a chip select
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address on the SPI bus.
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- #size-cells - should be zero.
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In slave mode, the SPI controller node requires one additional property:
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- spi-slave - Empty property.
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No other properties are required in the SPI bus node. It is assumed
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that a driver for an SPI bus device will understand that it is an SPI bus.
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However, the binding does not attempt to define the specific method for
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assigning chip select numbers. Since SPI chip select configuration is
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flexible and non-standardized, it is left out of this binding with the
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assumption that board specific platform code will be used to manage
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chip selects. Individual drivers can define additional properties to
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support describing the chip select layout.
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Optional properties (master mode only):
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- cs-gpios - gpios chip select.
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- num-cs - total number of chipselects.
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If cs-gpios is used the number of chip selects will be increased automatically
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with max(cs-gpios > hw cs).
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So if for example the controller has 2 CS lines, and the cs-gpios
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property looks like this:
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cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
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Then it should be configured so that num_chipselect = 4 with the
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following mapping:
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cs0 : &gpio1 0 0
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cs1 : native
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cs2 : &gpio1 1 0
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cs3 : &gpio1 2 0
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SPI slave nodes must be children of the SPI controller node.
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In master mode, one or more slave nodes (up to the number of chip selects) can
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be present. Required properties are:
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- compatible - Name of SPI device following generic names recommended
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practice.
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- reg - Chip select address of device.
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- spi-max-frequency - Maximum SPI clocking speed of device in Hz.
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In slave mode, the (single) slave node is optional.
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If present, it must be called "slave". Required properties are:
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- compatible - Name of SPI device following generic names recommended
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practice.
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All slave nodes can contain the following optional properties:
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- spi-cpol - Empty property indicating device requires inverse clock
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polarity (CPOL) mode.
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- spi-cpha - Empty property indicating device requires shifted clock
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phase (CPHA) mode.
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- spi-cs-high - Empty property indicating device requires chip select
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active high.
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- spi-3wire - Empty property indicating device requires 3-wire mode.
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- spi-lsb-first - Empty property indicating device requires LSB first mode.
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- spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI.
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Defaults to 1 if not present.
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- spi-rx-bus-width - The bus width (number of data wires) that is used for MISO.
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Defaults to 1 if not present.
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- spi-rx-delay-us - Microsecond delay after a read transfer.
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- spi-tx-delay-us - Microsecond delay after a write transfer.
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Some SPI controllers and devices support Dual and Quad SPI transfer mode.
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It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4
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wires (QUAD).
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Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
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only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).
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Dual/Quad mode is not allowed when 3-wire mode is used.
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If a gpio chipselect is used for the SPI slave the gpio number will be passed
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via the SPI master node cs-gpios property.
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SPI example for an MPC5200 SPI bus:
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spi@f00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
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reg = <0xf00 0x20>;
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interrupts = <2 13 0 2 14 0>;
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interrupt-parent = <&mpc5200_pic>;
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ethernet-switch@0 {
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compatible = "micrel,ks8995m";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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codec@1 {
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compatible = "ti,tlv320aic26";
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spi-max-frequency = <100000>;
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reg = <1>;
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};
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};
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@ -0,0 +1,161 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/spi-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SPI Controller Generic Binding
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maintainers:
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- Mark Brown <broonie@kernel.org>
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description: |
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SPI busses can be described with a node for the SPI controller device
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and a set of child nodes for each SPI slave on the bus. The system SPI
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controller may be described for use in SPI master mode or in SPI slave mode,
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but not for both at the same time.
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properties:
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$nodename:
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pattern: "^spi(@.*|-[0-9a-f])*$"
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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cs-gpios:
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description: |
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GPIOs used as chip selects.
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If that property is used, the number of chip selects will be
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increased automatically with max(cs-gpios, hardware chip selects).
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So if, for example, the controller has 2 CS lines, and the
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cs-gpios looks like this
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cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
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Then it should be configured so that num_chipselect = 4, with
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the following mapping
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cs0 : &gpio1 0 0
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cs1 : native
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cs2 : &gpio1 1 0
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cs3 : &gpio1 2 0
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num-cs:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Total number of chip selects.
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spi-slave:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The SPI controller acts as a slave, instead of a master.
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patternProperties:
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"^slave$":
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type: object
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properties:
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compatible:
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description:
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Compatible of the SPI device.
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required:
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- compatible
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"^.*@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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description:
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Compatible of the SPI device.
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reg:
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maxItems: 1
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minimum: 0
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maximum: 256
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description:
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Chip select used by the device.
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spi-3wire:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The device requires 3-wire mode.
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spi-cpha:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The device requires shifted clock phase (CPHA) mode.
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spi-cpol:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The device requires inverse clock polarity (CPOL) mode.
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spi-cs-high:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The device requires the chip select active high.
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spi-lsb-first:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The device requires the LSB first mode.
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spi-max-frequency:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Maximum SPI clocking speed of the device in Hz.
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spi-rx-bus-width:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 1, 2, 4 ]
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- default: 1
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description:
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Bus width to the SPI bus used for MISO.
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spi-rx-delay-us:
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description:
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Delay, in microseconds, after a read transfer.
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spi-tx-bus-width:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 1, 2, 4 ]
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- default: 1
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description:
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Bus width to the SPI bus used for MOSI.
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spi-tx-delay-us:
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description:
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Delay, in microseconds, after a write transfer.
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required:
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- compatible
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- reg
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examples:
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- |
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spi@f00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
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reg = <0xf00 0x20>;
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interrupts = <2 13 0 2 14 0>;
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interrupt-parent = <&mpc5200_pic>;
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ethernet-switch@0 {
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compatible = "micrel,ks8995m";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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codec@1 {
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compatible = "ti,tlv320aic26";
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spi-max-frequency = <100000>;
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reg = <1>;
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};
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};
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