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drm/amdgpu/sdma4:re-org SDMA initial steps for sriov 

Rework sdma init to support SR-IOV.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu 2016-12-15 13:56:53 +08:00 committed by Alex Deucher
parent cfee05bc90
commit 0e11de1ef5
1 changed files with 20 additions and 0 deletions
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20
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
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@ -522,6 +522,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
u32 wb_offset;
u32 doorbell;
u32 doorbell_offset;
u32 temp;
int i,r;
for (i = 0; i < adev->sdma.num_instances; i++) {
@ -576,6 +577,16 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
/* set utc l1 enable flag always to 1 */
temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp);
/* unhalt engine */
temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
/* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
@ -690,6 +701,15 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
{
int r;
if (amdgpu_sriov_vf(adev)) {
/* disable RB and halt engine */
sdma_v4_0_enable(adev, false);
/* set RB registers */
r = sdma_v4_0_gfx_resume(adev);
return r;
}
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
DRM_INFO("Loading via direct write\n");
r = sdma_v4_0_load_microcode(adev);