usb: renesas_usbhs: add support for R-Car D3
This patch adds support for R-Car D3. This SoC needs to release the PLL reset by the UGCTRL register. So, since this is not the same as other R-Car Gen3 SoCs, this patch adds a new type as "USBHS_TYPE_RCAR_GEN3_WITH_PLL". Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@ -10,6 +10,7 @@ Required properties:
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- "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device
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- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
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- "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device
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- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
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- "renesas,rcar-gen2-usbhs" for R-Car Gen2 compatible device
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- "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
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@ -485,6 +485,10 @@ static const struct of_device_id usbhs_of_match[] = {
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.compatible = "renesas,usbhs-r8a7796",
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.data = (void *)USBHS_TYPE_RCAR_GEN3,
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},
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{
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.compatible = "renesas,usbhs-r8a77995",
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.data = (void *)USBHS_TYPE_RCAR_GEN3_WITH_PLL,
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},
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{
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.compatible = "renesas,rcar-gen2-usbhs",
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.data = (void *)USBHS_TYPE_RCAR_GEN2,
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@ -519,7 +523,8 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev)
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dparam->enable_gpio = gpio;
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if (dparam->type == USBHS_TYPE_RCAR_GEN2 ||
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dparam->type == USBHS_TYPE_RCAR_GEN3) {
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dparam->type == USBHS_TYPE_RCAR_GEN3 ||
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dparam->type == USBHS_TYPE_RCAR_GEN3_WITH_PLL) {
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dparam->has_usb_dmac = 1;
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dparam->pipe_configs = usbhsc_new_pipe;
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dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
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@ -584,6 +589,9 @@ static int usbhs_probe(struct platform_device *pdev)
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case USBHS_TYPE_RCAR_GEN3:
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priv->pfunc = usbhs_rcar3_ops;
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break;
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case USBHS_TYPE_RCAR_GEN3_WITH_PLL:
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priv->pfunc = usbhs_rcar3_with_pll_ops;
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break;
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default:
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if (!info->platform_callback.get_id) {
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dev_err(&pdev->dev, "no platform callbacks");
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@ -15,24 +15,39 @@
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#include "rcar3.h"
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#define LPSTS 0x102
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#define UGCTRL 0x180 /* 32-bit register */
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#define UGCTRL2 0x184 /* 32-bit register */
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#define UGSTS 0x188 /* 32-bit register */
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/* Low Power Status register (LPSTS) */
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#define LPSTS_SUSPM 0x4000
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/* R-Car D3 only: USB General control register (UGCTRL) */
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#define UGCTRL_PLLRESET 0x00000001
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#define UGCTRL_CONNECT 0x00000004
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/*
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* USB General control register 2 (UGCTRL2)
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* Remarks: bit[31:11] and bit[9:6] should be 0
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*/
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#define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
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#define UGCTRL2_USB0SEL_HSUSB 0x00000020
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#define UGCTRL2_USB0SEL_OTG 0x00000030
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#define UGCTRL2_VBUSSEL 0x00000400
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/* R-Car D3 only: USB General status register (UGSTS) */
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#define UGSTS_LOCK 0x00000100
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static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
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{
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iowrite32(data, priv->base + reg);
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}
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static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg)
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{
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return ioread32(priv->base + reg);
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}
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static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
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void __iomem *base, int enable)
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{
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@ -52,6 +67,34 @@ static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
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return 0;
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}
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/* R-Car D3 needs to release UGCTRL.PLLRESET */
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static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
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void __iomem *base, int enable)
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{
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struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
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u32 val;
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int timeout = 1000;
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if (enable) {
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usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */
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usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 |
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UGCTRL2_USB0SEL_HSUSB);
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
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do {
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val = usbhs_read32(priv, UGSTS);
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udelay(1);
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} while (!(val & UGSTS_LOCK) && timeout--);
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usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT);
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} else {
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usbhs_write32(priv, UGCTRL, 0);
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
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usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET);
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}
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return 0;
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}
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static int usbhs_rcar3_get_id(struct platform_device *pdev)
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{
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return USBHS_GADGET;
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@ -61,3 +104,8 @@ const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = {
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.power_ctrl = usbhs_rcar3_power_ctrl,
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.get_id = usbhs_rcar3_get_id,
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};
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const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops = {
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.power_ctrl = usbhs_rcar3_power_and_pll_ctrl,
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.get_id = usbhs_rcar3_get_id,
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};
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@ -1,3 +1,4 @@
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#include "common.h"
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extern const struct renesas_usbhs_platform_callback usbhs_rcar3_ops;
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extern const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops;
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@ -183,8 +183,9 @@ struct renesas_usbhs_driver_param {
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#define USBHS_USB_DMAC_XFER_SIZE 32 /* hardcode the xfer size */
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};
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#define USBHS_TYPE_RCAR_GEN2 1
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#define USBHS_TYPE_RCAR_GEN3 2
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#define USBHS_TYPE_RCAR_GEN2 1
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#define USBHS_TYPE_RCAR_GEN3 2
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#define USBHS_TYPE_RCAR_GEN3_WITH_PLL 3
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/*
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* option:
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