STM32 DT for v5.19, round 1
Highlights:
----------
-MCU:
-Fix pinctrl node names to match with pinctrl yaml.
- MPU:
-General:
- Fix pinctrl node names to match with pinctrl yaml.
- Add Protonics boards support based on STM32MP151A SoC:
- PRTT1C - 10BaseT1L switch: mainly embeds a sja1105q switch with
TI and Micrel 10BaseT Phys and wifi support.
- PRTT1S - 10BaseT1L CO2 sensor board: mainly embeds I2C humidity
and CO2 sensors.
- PRTT1A - 10BaseT1L multi functional controller.
- ST boards:
- Add RTC support on stm32mp13.
- Add button and heartbit support on stm32mp13 DK board.
- Add a secure version of STM32MP15 ED1/EV1/DK1/DK2 boards based
on OP-TEE OS and SCMI protocol.
- DH boards:
- Use MCO2 to generate PHY clock and ETHRX clock in order to release
internal PLL for a better SD card usage.
- Add 1ms PHY post-reset on Avenger96 board to match with PHY
requirements.
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Merge tag 'stm32-dt-for-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT for v5.19, round 1
Highlights:
----------
-MCU:
-Fix pinctrl node names to match with pinctrl yaml.
- MPU:
-General:
- Fix pinctrl node names to match with pinctrl yaml.
- Add Protonics boards support based on STM32MP151A SoC:
- PRTT1C - 10BaseT1L switch: mainly embeds a sja1105q switch with
TI and Micrel 10BaseT Phys and wifi support.
- PRTT1S - 10BaseT1L CO2 sensor board: mainly embeds I2C humidity
and CO2 sensors.
- PRTT1A - 10BaseT1L multi functional controller.
- ST boards:
- Add RTC support on stm32mp13.
- Add button and heartbit support on stm32mp13 DK board.
- Add a secure version of STM32MP15 ED1/EV1/DK1/DK2 boards based
on OP-TEE OS and SCMI protocol.
- DH boards:
- Use MCO2 to generate PHY clock and ETHRX clock in order to release
internal PLL for a better SD card usage.
- Add 1ms PHY post-reset on Avenger96 board to match with PHY
requirements.
* tag 'stm32-dt-for-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (24 commits)
ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)
dt-bindings: arm: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)
ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15
dt-bindings: reset: stm32mp15: rename RST_SCMI define
dt-bindings: clock: stm32mp15: rename CK_SCMI define
dt-bindings: clock: stm32mp1: describes clocks if "st,stm32mp1-rcc-secure"
dt-bindings: rcc: Add optional external ethernet RX clock properties
ARM: dts: stm32: add UserPA13 button on stm32mp135f-dk
ARM: dts: stm32: add blue led (Linux heartbeat) on stm32mp135f-dk
ARM: dts: stm32: add EXTI interrupt-parent to pinctrl node on stm32mp131
ARM: dts: stm32: add support for Protonic PRTT1x boards
ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group
dt-bindings: net: silabs,wfx: add prt,prtt1c-wfm200 antenna variant
dt-bindings: arm: stm32: Add compatible strings for Protonic T1L boards
dt-bindings: arm: stm32: correct blank lines
dt-bindings: arm: stm32: narrow DH STM32MP1 SoM boards
ARM: dts: stm32: enable RTC support on stm32mp135f-dk
ARM: dts: stm32: add RTC node on stm32mp131
ARM: dts: stm32: Fix PHY post-reset delay on Avenger96
ARM: dts: stm32: fix pinctrl node name warnings (MPU soc)
...
Link: https://lore.kernel.org/r/5818c943-882d-7e50-430d-ae3299a108ee@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
0fd8954b9e
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@ -14,21 +14,6 @@ properties:
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||||||
const: "/"
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const: "/"
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compatible:
|
compatible:
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oneOf:
|
oneOf:
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||||||
- description: DH STM32MP1 SoM based Boards
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items:
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- enum:
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||||||
- arrow,stm32mp157a-avenger96 # Avenger96
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- dh,stm32mp153c-dhcom-drc02
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- dh,stm32mp157c-dhcom-pdk2
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- dh,stm32mp157c-dhcom-picoitx
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- enum:
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- dh,stm32mp153c-dhcom-som
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- dh,stm32mp157a-dhcor-som
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- dh,stm32mp157c-dhcom-som
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- enum:
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- st,stm32mp153
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- st,stm32mp157
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- description: emtrion STM32MP1 Argon based Boards
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- description: emtrion STM32MP1 Argon based Boards
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items:
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items:
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- const: emtrion,stm32mp157c-emsbc-argon
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- const: emtrion,stm32mp157c-emsbc-argon
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@ -65,6 +50,21 @@ properties:
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- enum:
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- enum:
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- st,stm32mp135f-dk
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- st,stm32mp135f-dk
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- const: st,stm32mp135
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- const: st,stm32mp135
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- description: ST STM32MP151 based Boards
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items:
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- enum:
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- prt,prtt1a # Protonic PRTT1A
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- prt,prtt1c # Protonic PRTT1C
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- prt,prtt1s # Protonic PRTT1S
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- const: st,stm32mp151
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- description: DH STM32MP153 SoM based Boards
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items:
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- const: dh,stm32mp153c-dhcom-drc02
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- const: dh,stm32mp153c-dhcom-som
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- const: st,stm32mp153
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- items:
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- items:
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- enum:
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- enum:
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- shiratech,stm32mp157a-iot-box # IoT Box
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- shiratech,stm32mp157a-iot-box # IoT Box
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@ -72,12 +72,44 @@ properties:
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- st,stm32mp157c-ed1
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- st,stm32mp157c-ed1
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- st,stm32mp157a-dk1
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- st,stm32mp157a-dk1
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- st,stm32mp157c-dk2
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- st,stm32mp157c-dk2
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- const: st,stm32mp157
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- items:
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- const: st,stm32mp157a-dk1-scmi
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- const: st,stm32mp157a-dk1
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- const: st,stm32mp157
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- items:
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- const: st,stm32mp157c-dk2-scmi
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- const: st,stm32mp157c-dk2
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- const: st,stm32mp157
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- items:
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- const: st,stm32mp157c-ed1-scmi
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- const: st,stm32mp157c-ed1
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- const: st,stm32mp157
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- const: st,stm32mp157
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- items:
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- items:
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- const: st,stm32mp157c-ev1
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- const: st,stm32mp157c-ev1
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- const: st,stm32mp157c-ed1
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- const: st,stm32mp157c-ed1
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- const: st,stm32mp157
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- const: st,stm32mp157
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- items:
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- const: st,stm32mp157c-ev1-scmi
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- const: st,stm32mp157c-ev1
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- const: st,stm32mp157c-ed1
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- const: st,stm32mp157
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- description: DH STM32MP1 SoM based Boards
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items:
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- enum:
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- arrow,stm32mp157a-avenger96 # Avenger96
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- const: dh,stm32mp157a-dhcor-som
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- const: st,stm32mp157
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- description: DH STM32MP1 SoM based Boards
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items:
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- enum:
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- dh,stm32mp157c-dhcom-pdk2
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- dh,stm32mp157c-dhcom-picoitx
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- const: dh,stm32mp157c-dhcom-som
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- const: st,stm32mp157
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- description: Engicam i.Core STM32MP1 SoM based Boards
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- description: Engicam i.Core STM32MP1 SoM based Boards
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items:
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items:
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@ -103,6 +135,7 @@ properties:
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||||||
- const: oct,stm32mp15xx-osd32
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- const: oct,stm32mp15xx-osd32
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- enum:
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- enum:
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- st,stm32mp157
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- st,stm32mp157
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- description: Odyssey STM32MP1 SoM based Boards
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- description: Odyssey STM32MP1 SoM based Boards
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items:
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items:
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- enum:
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- enum:
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@ -58,6 +58,8 @@ properties:
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- st,stm32mp1-rcc-secure
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- st,stm32mp1-rcc-secure
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- st,stm32mp1-rcc
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- st,stm32mp1-rcc
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- const: syscon
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- const: syscon
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clocks: true
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clock-names: true
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reg:
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reg:
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maxItems: 1
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maxItems: 1
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@ -68,6 +70,38 @@ required:
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- compatible
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- compatible
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- reg
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- reg
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if:
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properties:
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compatible:
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contains:
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enum:
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- st,stm32mp1-rcc-secure
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then:
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properties:
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clocks:
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description: Specifies oscillators.
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maxItems: 5
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clock-names:
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items:
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- const: hse
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- const: hsi
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- const: csi
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- const: lse
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- const: lsi
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required:
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- clocks
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- clock-names
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else:
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properties:
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clocks:
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description:
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|
Specifies the external RX clock for ethernet MAC.
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maxItems: 1
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clock-names:
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const: ETH_RX_CLK/ETH_REF_CLK
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additionalProperties: false
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additionalProperties: false
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examples:
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examples:
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|
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@ -39,6 +39,7 @@ properties:
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||||||
compatible:
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compatible:
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||||||
items:
|
items:
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- enum:
|
- enum:
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||||||
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- prt,prtt1c-wfm200 # Protonic PRTT1C Board
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- silabs,brd4001a # WGM160P Evaluation Board
|
- silabs,brd4001a # WGM160P Evaluation Board
|
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- silabs,brd8022a # WF200 Evaluation Board
|
- silabs,brd8022a # WF200 Evaluation Board
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- silabs,brd8023a # WFM200 Evaluation Board
|
- silabs,brd8023a # WFM200 Evaluation Board
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@ -1156,10 +1156,14 @@ dtb-$(CONFIG_ARCH_STM32) += \
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stm32h743i-disco.dtb \
|
stm32h743i-disco.dtb \
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stm32h750i-art-pi.dtb \
|
stm32h750i-art-pi.dtb \
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stm32mp135f-dk.dtb \
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stm32mp135f-dk.dtb \
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stm32mp151a-prtt1a.dtb \
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stm32mp151a-prtt1c.dtb \
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stm32mp151a-prtt1s.dtb \
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stm32mp153c-dhcom-drc02.dtb \
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stm32mp153c-dhcom-drc02.dtb \
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stm32mp157a-avenger96.dtb \
|
stm32mp157a-avenger96.dtb \
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stm32mp157a-dhcor-avenger96.dtb \
|
stm32mp157a-dhcor-avenger96.dtb \
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stm32mp157a-dk1.dtb \
|
stm32mp157a-dk1.dtb \
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stm32mp157a-dk1-scmi.dtb \
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stm32mp157a-iot-box.dtb \
|
stm32mp157a-iot-box.dtb \
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stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
|
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
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||||||
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
|
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
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|
|
@ -1170,9 +1174,12 @@ dtb-$(CONFIG_ARCH_STM32) += \
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stm32mp157c-dhcom-pdk2.dtb \
|
stm32mp157c-dhcom-pdk2.dtb \
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stm32mp157c-dhcom-picoitx.dtb \
|
stm32mp157c-dhcom-picoitx.dtb \
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stm32mp157c-dk2.dtb \
|
stm32mp157c-dk2.dtb \
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stm32mp157c-dk2-scmi.dtb \
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stm32mp157c-ed1.dtb \
|
stm32mp157c-ed1.dtb \
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stm32mp157c-ed1-scmi.dtb \
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stm32mp157c-emsbc-argon.dtb \
|
stm32mp157c-emsbc-argon.dtb \
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stm32mp157c-ev1.dtb \
|
stm32mp157c-ev1.dtb \
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stm32mp157c-ev1-scmi.dtb \
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stm32mp157c-lxa-mc1.dtb \
|
stm32mp157c-lxa-mc1.dtb \
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stm32mp157c-odyssey.dtb
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stm32mp157c-odyssey.dtb
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dtb-$(CONFIG_MACH_SUN4I) += \
|
dtb-$(CONFIG_MACH_SUN4I) += \
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|
|
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@ -45,7 +45,7 @@
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|
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/ {
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/ {
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soc {
|
soc {
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pinctrl: pin-controller@40020000 {
|
pinctrl: pinctrl@40020000 {
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#address-cells = <1>;
|
#address-cells = <1>;
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#size-cells = <1>;
|
#size-cells = <1>;
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ranges = <0 0x40020000 0x3000>;
|
ranges = <0 0x40020000 0x3000>;
|
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|
|
|
||||||
|
|
@ -9,7 +9,7 @@
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
soc {
|
soc {
|
||||||
pinctrl: pin-controller@40020000 {
|
pinctrl: pinctrl@40020000 {
|
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#address-cells = <1>;
|
#address-cells = <1>;
|
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#size-cells = <1>;
|
#size-cells = <1>;
|
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ranges = <0 0x40020000 0x3000>;
|
ranges = <0 0x40020000 0x3000>;
|
||||||
|
|
|
||||||
|
|
@ -583,7 +583,7 @@ mac: ethernet@40028000 {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
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|
|
||||||
pinctrl: pin-controller@58020000 {
|
pinctrl: pinctrl@58020000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "st,stm32h743-pinctrl";
|
compatible = "st,stm32h743-pinctrl";
|
||||||
|
|
|
||||||
|
|
@ -75,6 +75,12 @@ clk_pll4_r: clk-pll4_r {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
clock-frequency = <99000000>;
|
clock-frequency = <99000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
clk_rtc_k: clk-rtc-k {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <32768>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
intc: interrupt-controller@a0021000 {
|
intc: interrupt-controller@a0021000 {
|
||||||
|
|
@ -218,6 +224,15 @@ iwdg2: watchdog@5a002000 {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
rtc: rtc@5c004000 {
|
||||||
|
compatible = "st,stm32mp1-rtc";
|
||||||
|
reg = <0x5c004000 0x400>;
|
||||||
|
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clk_pclk4>, <&clk_rtc_k>;
|
||||||
|
clock-names = "pclk", "rtc_ck";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
bsec: efuse@5c005000 {
|
bsec: efuse@5c005000 {
|
||||||
compatible = "st,stm32mp15-bsec";
|
compatible = "st,stm32mp15-bsec";
|
||||||
reg = <0x5c005000 0x400>;
|
reg = <0x5c005000 0x400>;
|
||||||
|
|
@ -239,11 +254,13 @@ ts_cal2: calib@5e {
|
||||||
* Break node order to solve dependency probe issue between
|
* Break node order to solve dependency probe issue between
|
||||||
* pinctrl and exti.
|
* pinctrl and exti.
|
||||||
*/
|
*/
|
||||||
pinctrl: pin-controller@50002000 {
|
pinctrl: pinctrl@50002000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "st,stm32mp135-pinctrl";
|
compatible = "st,stm32mp135-pinctrl";
|
||||||
ranges = <0 0x50002000 0x8400>;
|
ranges = <0 0x50002000 0x8400>;
|
||||||
|
interrupt-parent = <&exti>;
|
||||||
|
st,syscfg = <&exti 0x60 0xff>;
|
||||||
pins-are-numbered;
|
pins-are-numbered;
|
||||||
|
|
||||||
gpioa: gpio@50002000 {
|
gpioa: gpio@50002000 {
|
||||||
|
|
|
||||||
|
|
@ -6,6 +6,9 @@
|
||||||
|
|
||||||
/dts-v1/;
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
#include <dt-bindings/input/input.h>
|
||||||
|
#include <dt-bindings/leds/common.h>
|
||||||
#include "stm32mp135.dtsi"
|
#include "stm32mp135.dtsi"
|
||||||
#include "stm32mp13xf.dtsi"
|
#include "stm32mp13xf.dtsi"
|
||||||
#include "stm32mp13-pinctrl.dtsi"
|
#include "stm32mp13-pinctrl.dtsi"
|
||||||
|
|
@ -23,6 +26,28 @@ memory@c0000000 {
|
||||||
reg = <0xc0000000 0x20000000>;
|
reg = <0xc0000000 0x20000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
gpio-keys {
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
|
||||||
|
user-pa13 {
|
||||||
|
label = "User-PA13";
|
||||||
|
linux,code = <BTN_1>;
|
||||||
|
gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
|
||||||
|
led-blue {
|
||||||
|
function = LED_FUNCTION_HEARTBEAT;
|
||||||
|
color = <LED_COLOR_ID_BLUE>;
|
||||||
|
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
||||||
|
linux,default-trigger = "heartbeat";
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
vdd_sd: vdd-sd {
|
vdd_sd: vdd-sd {
|
||||||
compatible = "regulator-fixed";
|
compatible = "regulator-fixed";
|
||||||
regulator-name = "vdd_sd";
|
regulator-name = "vdd_sd";
|
||||||
|
|
@ -37,6 +62,10 @@ &iwdg2 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&rtc {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
&sdmmc1 {
|
&sdmmc1 {
|
||||||
pinctrl-names = "default", "opendrain", "sleep";
|
pinctrl-names = "default", "opendrain", "sleep";
|
||||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
|
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
|
||||||
|
|
|
||||||
|
|
@ -379,6 +379,40 @@ pins1 {
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
ethernet0_rmii_pins_c: rmii-2 {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
|
||||||
|
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
|
||||||
|
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
|
||||||
|
<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
|
||||||
|
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
|
||||||
|
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
|
||||||
|
bias-disable;
|
||||||
|
drive-push-pull;
|
||||||
|
slew-rate = <2>;
|
||||||
|
};
|
||||||
|
pins2 {
|
||||||
|
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
|
||||||
|
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
|
||||||
|
<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
|
||||||
|
bias-disable;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
|
||||||
|
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
|
||||||
|
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
|
||||||
|
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
|
||||||
|
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
|
||||||
|
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
|
||||||
|
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
|
||||||
|
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
|
||||||
|
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
fmc_pins_a: fmc-0 {
|
fmc_pins_a: fmc-0 {
|
||||||
pins1 {
|
pins1 {
|
||||||
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
||||||
|
|
@ -889,6 +923,21 @@ pins {
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
mco2_pins_a: mco2-0 {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
|
||||||
|
bias-disable;
|
||||||
|
drive-push-pull;
|
||||||
|
slew-rate = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mco2_sleep_pins_a: mco2-sleep-0 {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
m_can1_pins_a: m-can1-0 {
|
m_can1_pins_a: m-can1-0 {
|
||||||
pins1 {
|
pins1 {
|
||||||
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
||||||
|
|
@ -2212,4 +2261,19 @@ pins2 {
|
||||||
bias-disable;
|
bias-disable;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
spi1_pins_b: spi1-1 {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
|
||||||
|
<STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
|
||||||
|
bias-disable;
|
||||||
|
drive-push-pull;
|
||||||
|
slew-rate = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins2 {
|
||||||
|
pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
|
||||||
|
bias-disable;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -115,6 +115,33 @@ booster: regulator-booster {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
firmware {
|
||||||
|
optee: optee {
|
||||||
|
compatible = "linaro,optee-tz";
|
||||||
|
method = "smc";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scmi: scmi {
|
||||||
|
compatible = "linaro,scmi-optee";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
linaro,optee-channel-id = <0>;
|
||||||
|
shmem = <&scmi_shm>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
scmi_clk: protocol@14 {
|
||||||
|
reg = <0x14>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
scmi_reset: protocol@16 {
|
||||||
|
reg = <0x16>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
soc {
|
soc {
|
||||||
compatible = "simple-bus";
|
compatible = "simple-bus";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -122,6 +149,20 @@ soc {
|
||||||
interrupt-parent = <&intc>;
|
interrupt-parent = <&intc>;
|
||||||
ranges;
|
ranges;
|
||||||
|
|
||||||
|
scmi_sram: sram@2ffff000 {
|
||||||
|
compatible = "mmio-sram";
|
||||||
|
reg = <0x2ffff000 0x1000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 0x2ffff000 0x1000>;
|
||||||
|
|
||||||
|
scmi_shm: scmi-sram@0 {
|
||||||
|
compatible = "arm,scmi-shmem";
|
||||||
|
reg = <0 0x80>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
timers2: timer@40000000 {
|
timers2: timer@40000000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
@ -1623,7 +1664,7 @@ tamp: tamp@5c00a000 {
|
||||||
* Break node order to solve dependency probe issue between
|
* Break node order to solve dependency probe issue between
|
||||||
* pinctrl and exti.
|
* pinctrl and exti.
|
||||||
*/
|
*/
|
||||||
pinctrl: pin-controller@50002000 {
|
pinctrl: pinctrl@50002000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "st,stm32mp157-pinctrl";
|
compatible = "st,stm32mp157-pinctrl";
|
||||||
|
|
@ -1754,7 +1795,7 @@ gpiok: gpio@5000c000 {
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
pinctrl_z: pin-controller-z@54004000 {
|
pinctrl_z: pinctrl@54004000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "st,stm32mp157-z-pinctrl";
|
compatible = "st,stm32mp157-z-pinctrl";
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,52 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) Protonic Holland
|
||||||
|
* Author: David Jander <david@protonic.nl>
|
||||||
|
*/
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp151a-prtt1l.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Protonic PRTT1A";
|
||||||
|
compatible = "prt,prtt1a", "st,stm32mp151";
|
||||||
|
};
|
||||||
|
|
||||||
|
ðernet0 {
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdio0 {
|
||||||
|
/* TI DP83TD510E */
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
compatible = "ethernet-phy-id2000.0181";
|
||||||
|
reg = <0>;
|
||||||
|
interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-assert-us = <10>;
|
||||||
|
reset-deassert-us = <35>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&pwm5_pins_a {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&pwm5_sleep_pins_a {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* TIM5_CH1 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&timers5 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
pinctrl-0 = <&pwm5_pins_a>;
|
||||||
|
pinctrl-1 = <&pwm5_sleep_pins_a>;
|
||||||
|
pinctrl-names = "default", "sleep";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,304 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) Protonic Holland
|
||||||
|
* Author: David Jander <david@protonic.nl>
|
||||||
|
*/
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp151a-prtt1l.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Protonic PRTT1C";
|
||||||
|
compatible = "prt,prtt1c", "st,stm32mp151";
|
||||||
|
|
||||||
|
clock_ksz9031: clock-ksz9031 {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <25000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clock_sja1105: clock-sja1105 {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <25000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio0: mdio {
|
||||||
|
compatible = "virtual,mdio-gpio";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
|
||||||
|
&gpioa 2 GPIO_ACTIVE_HIGH>;
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
wifi_pwrseq: wifi-pwrseq {
|
||||||
|
compatible = "mmc-pwrseq-simple";
|
||||||
|
reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ðernet0 {
|
||||||
|
fixed-link {
|
||||||
|
speed = <100>;
|
||||||
|
full-duplex;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioa {
|
||||||
|
gpio-line-names =
|
||||||
|
"", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "",
|
||||||
|
"", "", "", "", "", "", "", "SPI1_nSS";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpiod {
|
||||||
|
gpio-line-names =
|
||||||
|
"", "", "", "", "", "", "", "",
|
||||||
|
"WFM_RESET", "", "", "", "", "", "", "";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioe {
|
||||||
|
gpio-line-names =
|
||||||
|
"SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "",
|
||||||
|
"", "", "", "", "WFM_nIRQ", "", "", "";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpiog {
|
||||||
|
gpio-line-names =
|
||||||
|
"", "", "", "", "", "", "", "PHY3_nINT",
|
||||||
|
"PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET",
|
||||||
|
"PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", "";
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdio0 {
|
||||||
|
/* All this DP83TD510E PHYs can't be probed before switch@0 is
|
||||||
|
* probed so we need to use compatible with PHYid
|
||||||
|
*/
|
||||||
|
/* TI DP83TD510E */
|
||||||
|
t1l0_phy: ethernet-phy@6 {
|
||||||
|
compatible = "ethernet-phy-id2000.0181";
|
||||||
|
reg = <6>;
|
||||||
|
interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-assert-us = <10>;
|
||||||
|
reset-deassert-us = <35>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* TI DP83TD510E */
|
||||||
|
t1l1_phy: ethernet-phy@7 {
|
||||||
|
compatible = "ethernet-phy-id2000.0181";
|
||||||
|
reg = <7>;
|
||||||
|
interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-assert-us = <10>;
|
||||||
|
reset-deassert-us = <35>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* TI DP83TD510E */
|
||||||
|
t1l2_phy: ethernet-phy@10 {
|
||||||
|
compatible = "ethernet-phy-id2000.0181";
|
||||||
|
reg = <10>;
|
||||||
|
interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-assert-us = <10>;
|
||||||
|
reset-deassert-us = <35>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Micrel KSZ9031 */
|
||||||
|
rj45_phy: ethernet-phy@2 {
|
||||||
|
reg = <2>;
|
||||||
|
interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-assert-us = <10000>;
|
||||||
|
reset-deassert-us = <1000>;
|
||||||
|
|
||||||
|
clocks = <&clock_ksz9031>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&qspi {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc2 {
|
||||||
|
pinctrl-names = "default", "opendrain", "sleep";
|
||||||
|
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
||||||
|
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
|
||||||
|
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
|
||||||
|
non-removable;
|
||||||
|
no-sd;
|
||||||
|
no-sdio;
|
||||||
|
no-1-8-v;
|
||||||
|
st,neg-edge;
|
||||||
|
bus-width = <8>;
|
||||||
|
vmmc-supply = <®_3v3>;
|
||||||
|
vqmmc-supply = <®_3v3>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc2_b4_od_pins_a {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
||||||
|
<STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
|
||||||
|
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
||||||
|
<STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc2_b4_pins_a {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
||||||
|
<STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
|
||||||
|
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
||||||
|
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
||||||
|
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc2_b4_sleep_pins_a {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
|
||||||
|
<STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
|
||||||
|
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
|
||||||
|
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
|
||||||
|
<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
|
||||||
|
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc2_d47_pins_a {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
|
||||||
|
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
|
||||||
|
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
|
||||||
|
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc2_d47_sleep_pins_a {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
|
||||||
|
<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
|
||||||
|
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
|
||||||
|
<STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc3 {
|
||||||
|
pinctrl-names = "default", "opendrain", "sleep";
|
||||||
|
pinctrl-0 = <&sdmmc3_b4_pins_b>;
|
||||||
|
pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
|
||||||
|
pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
|
||||||
|
non-removable;
|
||||||
|
no-1-8-v;
|
||||||
|
st,neg-edge;
|
||||||
|
bus-width = <4>;
|
||||||
|
vmmc-supply = <®_3v3>;
|
||||||
|
vqmmc-supply = <®_3v3>;
|
||||||
|
mmc-pwrseq = <&wifi_pwrseq>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
mmc@1 {
|
||||||
|
compatible = "prt,prtt1c-wfm200", "silabs,wf200";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc3_b4_od_pins_b {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
|
||||||
|
<STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
|
||||||
|
<STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
|
||||||
|
<STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc3_b4_pins_b {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
|
||||||
|
<STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
|
||||||
|
<STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
|
||||||
|
<STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
|
||||||
|
<STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc3_b4_sleep_pins_b {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
|
||||||
|
<STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
|
||||||
|
<STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
|
||||||
|
<STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
|
||||||
|
<STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
|
||||||
|
<STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi1 {
|
||||||
|
pinctrl-0 = <&spi1_pins_b>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
|
||||||
|
/delete-property/dmas;
|
||||||
|
/delete-property/dma-names;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
switch@0 {
|
||||||
|
compatible = "nxp,sja1105q";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <4000000>;
|
||||||
|
spi-rx-delay-us = <1>;
|
||||||
|
spi-tx-delay-us = <1>;
|
||||||
|
spi-cpha;
|
||||||
|
|
||||||
|
reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
|
||||||
|
|
||||||
|
clocks = <&clock_sja1105>;
|
||||||
|
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
label = "t1l0";
|
||||||
|
phy-mode = "rmii";
|
||||||
|
phy-handle = <&t1l0_phy>;
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
label = "t1l1";
|
||||||
|
phy-mode = "rmii";
|
||||||
|
phy-handle = <&t1l1_phy>;
|
||||||
|
};
|
||||||
|
|
||||||
|
port@2 {
|
||||||
|
reg = <2>;
|
||||||
|
label = "t1l2";
|
||||||
|
phy-mode = "rmii";
|
||||||
|
phy-handle = <&t1l2_phy>;
|
||||||
|
};
|
||||||
|
|
||||||
|
port@3 {
|
||||||
|
reg = <3>;
|
||||||
|
label = "rj45";
|
||||||
|
phy-handle = <&rj45_phy>;
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@4 {
|
||||||
|
reg = <4>;
|
||||||
|
label = "cpu";
|
||||||
|
ethernet = <ðernet0>;
|
||||||
|
phy-mode = "rmii";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
speed = <100>;
|
||||||
|
full-duplex;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,229 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) Protonic Holland
|
||||||
|
* Author: David Jander <david@protonic.nl>
|
||||||
|
*/
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp151.dtsi"
|
||||||
|
#include "stm32mp15-pinctrl.dtsi"
|
||||||
|
#include "stm32mp15xxad-pinctrl.dtsi"
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
#include <dt-bindings/input/input.h>
|
||||||
|
#include <dt-bindings/leds/common.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
aliases {
|
||||||
|
ethernet0 = ðernet0;
|
||||||
|
mdio-gpio0 = &mdio0;
|
||||||
|
serial0 = &uart4;
|
||||||
|
};
|
||||||
|
|
||||||
|
led-controller-0 {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
|
||||||
|
led-0 {
|
||||||
|
color = <LED_COLOR_ID_RED>;
|
||||||
|
function = LED_FUNCTION_INDICATOR;
|
||||||
|
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
|
||||||
|
led-1 {
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
function = LED_FUNCTION_INDICATOR;
|
||||||
|
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
||||||
|
linux,default-trigger = "heartbeat";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce
|
||||||
|
* stmmac MDC clock without reducing system bus rate, we need to use
|
||||||
|
* gpio based MDIO bus.
|
||||||
|
*/
|
||||||
|
mdio0: mdio {
|
||||||
|
compatible = "virtual,mdio-gpio";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
|
||||||
|
&gpioa 2 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
reg_3v3: regulator-3v3 {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "3v3";
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&dts {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
ðernet0 {
|
||||||
|
pinctrl-0 = <ðernet0_rmii_pins_a>;
|
||||||
|
pinctrl-1 = <ðernet0_rmii_sleep_pins_a>;
|
||||||
|
pinctrl-names = "default", "sleep";
|
||||||
|
phy-mode = "rmii";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
ðernet0_rmii_pins_a {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
|
||||||
|
<STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
|
||||||
|
<STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
|
||||||
|
};
|
||||||
|
pins2 {
|
||||||
|
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
|
||||||
|
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
|
||||||
|
<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK input */
|
||||||
|
<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ðernet0_rmii_sleep_pins_a {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */
|
||||||
|
<STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */
|
||||||
|
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
|
||||||
|
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
|
||||||
|
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
|
||||||
|
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
|
||||||
|
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&iwdg2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&qspi {
|
||||||
|
pinctrl-names = "default", "sleep";
|
||||||
|
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
|
||||||
|
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
|
||||||
|
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
flash@0 {
|
||||||
|
compatible = "spi-nand";
|
||||||
|
reg = <0>;
|
||||||
|
spi-rx-bus-width = <4>;
|
||||||
|
spi-max-frequency = <104000000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&qspi_bk1_pins_a {
|
||||||
|
pins1 {
|
||||||
|
bias-pull-up;
|
||||||
|
drive-push-pull;
|
||||||
|
slew-rate = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&rng1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc1 {
|
||||||
|
pinctrl-names = "default", "opendrain", "sleep";
|
||||||
|
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||||
|
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||||
|
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||||
|
broken-cd;
|
||||||
|
st,neg-edge;
|
||||||
|
bus-width = <4>;
|
||||||
|
vmmc-supply = <®_3v3>;
|
||||||
|
vqmmc-supply = <®_3v3>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc1_b4_od_pins_a {
|
||||||
|
pins1 {
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
pins2 {
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc1_b4_pins_a {
|
||||||
|
pins1 {
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
pins2 {
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart4 {
|
||||||
|
pinctrl-names = "default", "sleep", "idle";
|
||||||
|
pinctrl-0 = <&uart4_pins_a>;
|
||||||
|
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||||
|
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||||
|
/delete-property/dmas;
|
||||||
|
/delete-property/dma-names;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart4_idle_pins_a {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* UART4_TX */
|
||||||
|
};
|
||||||
|
pins2 {
|
||||||
|
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart4_pins_a {
|
||||||
|
pins1 {
|
||||||
|
pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
|
||||||
|
bias-disable;
|
||||||
|
drive-push-pull;
|
||||||
|
slew-rate = <0>;
|
||||||
|
};
|
||||||
|
pins2 {
|
||||||
|
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart4_sleep_pins_a {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* UART4_TX */
|
||||||
|
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbh_ehci {
|
||||||
|
phys = <&usbphyc_port0>;
|
||||||
|
phy-names = "usb";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbotg_hs {
|
||||||
|
dr_mode = "host";
|
||||||
|
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
phys = <&usbphyc_port1 0>;
|
||||||
|
phy-names = "usb2-phy";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbphyc {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbphyc_port0 {
|
||||||
|
phy-supply = <®_3v3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbphyc_port1 {
|
||||||
|
phy-supply = <®_3v3>;
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,63 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) Protonic Holland
|
||||||
|
* Author: David Jander <david@protonic.nl>
|
||||||
|
*/
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp151a-prtt1l.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Protonic PRTT1S";
|
||||||
|
compatible = "prt,prtt1s", "st,stm32mp151";
|
||||||
|
};
|
||||||
|
|
||||||
|
ðernet0 {
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c1 {
|
||||||
|
pinctrl-names = "default", "sleep";
|
||||||
|
pinctrl-0 = <&i2c1_pins_a>;
|
||||||
|
pinctrl-1 = <&i2c1_sleep_pins_a>;
|
||||||
|
clock-frequency = <100000>;
|
||||||
|
/delete-property/dmas;
|
||||||
|
/delete-property/dma-names;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
humidity-sensor@40 {
|
||||||
|
compatible = "ti,hdc1080";
|
||||||
|
reg = <0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
co2-sensor@62 {
|
||||||
|
compatible = "sensirion,scd41";
|
||||||
|
reg = <0x62>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c1_pins_a {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
||||||
|
<STM32_PINMUX('D', 13, AF5)>; /* I2C1_SDA */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c1_sleep_pins_a {
|
||||||
|
pins {
|
||||||
|
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
||||||
|
<STM32_PINMUX('D', 13, ANALOG)>; /* I2C1_SDA */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdio0 {
|
||||||
|
/* TI DP83TD510E */
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
compatible = "ethernet-phy-id2000.0181";
|
||||||
|
reg = <0>;
|
||||||
|
interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-assert-us = <10>;
|
||||||
|
reset-deassert-us = <35>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,86 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp157a-dk1.dts"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
|
||||||
|
compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
optee@de000000 {
|
||||||
|
reg = <0xde000000 0x2000000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu0 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioz {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&hash1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c4 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&iwdg2 {
|
||||||
|
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdma1 {
|
||||||
|
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mlahb {
|
||||||
|
resets = <&scmi_reset RST_SCMI_MCU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&optee {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&rcc {
|
||||||
|
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||||
|
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||||
|
<&scmi_clk CK_SCMI_HSI>,
|
||||||
|
<&scmi_clk CK_SCMI_CSI>,
|
||||||
|
<&scmi_clk CK_SCMI_LSE>,
|
||||||
|
<&scmi_clk CK_SCMI_LSI>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&rng1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&rtc {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&scmi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&scmi_shm {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,95 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp157c-dk2.dts"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
|
||||||
|
compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
optee@de000000 {
|
||||||
|
reg = <0xde000000 0x2000000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu0 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cryp1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_CRYP1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_CRYP1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&dsi {
|
||||||
|
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioz {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&hash1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c4 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&iwdg2 {
|
||||||
|
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdma1 {
|
||||||
|
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mlahb {
|
||||||
|
resets = <&scmi_reset RST_SCMI_MCU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&optee {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&rcc {
|
||||||
|
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||||
|
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||||
|
<&scmi_clk CK_SCMI_HSI>,
|
||||||
|
<&scmi_clk CK_SCMI_CSI>,
|
||||||
|
<&scmi_clk CK_SCMI_LSE>,
|
||||||
|
<&scmi_clk CK_SCMI_LSI>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&rng1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&rtc {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&scmi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&scmi_shm {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,91 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp157c-ed1.dts"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
|
||||||
|
compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
optee@fe000000 {
|
||||||
|
reg = <0xfe000000 0x2000000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu0 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cryp1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_CRYP1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_CRYP1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioz {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&hash1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c4 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&iwdg2 {
|
||||||
|
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdma1 {
|
||||||
|
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mlahb {
|
||||||
|
resets = <&scmi_reset RST_SCMI_MCU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&optee {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&rcc {
|
||||||
|
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||||
|
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||||
|
<&scmi_clk CK_SCMI_HSI>,
|
||||||
|
<&scmi_clk CK_SCMI_CSI>,
|
||||||
|
<&scmi_clk CK_SCMI_LSE>,
|
||||||
|
<&scmi_clk CK_SCMI_LSI>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&rng1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&rtc {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&scmi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&scmi_shm {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,100 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp157c-ev1.dts"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
|
||||||
|
compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
|
||||||
|
"st,stm32mp157";
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
optee@fe000000 {
|
||||||
|
reg = <0xfe000000 0x2000000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu0 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cryp1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_CRYP1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_CRYP1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&dsi {
|
||||||
|
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioz {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&hash1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c4 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&iwdg2 {
|
||||||
|
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&m_can1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdma1 {
|
||||||
|
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mlahb {
|
||||||
|
resets = <&scmi_reset RST_SCMI_MCU>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&optee {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&rcc {
|
||||||
|
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||||
|
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||||
|
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||||
|
<&scmi_clk CK_SCMI_HSI>,
|
||||||
|
<&scmi_clk CK_SCMI_CSI>,
|
||||||
|
<&scmi_clk CK_SCMI_LSE>,
|
||||||
|
<&scmi_clk CK_SCMI_LSI>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&rng1 {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||||
|
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&rtc {
|
||||||
|
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&scmi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&scmi_shm {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
@ -118,13 +118,12 @@ &dts {
|
||||||
|
|
||||||
ðernet0 {
|
ðernet0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
pinctrl-0 = <ðernet0_rmii_pins_a>;
|
pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>;
|
||||||
pinctrl-1 = <ðernet0_rmii_sleep_pins_a>;
|
pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
|
||||||
pinctrl-names = "default", "sleep";
|
pinctrl-names = "default", "sleep";
|
||||||
phy-mode = "rmii";
|
phy-mode = "rmii";
|
||||||
max-speed = <100>;
|
max-speed = <100>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
st,eth-ref-clk-sel;
|
|
||||||
|
|
||||||
mdio0 {
|
mdio0 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -136,7 +135,7 @@ phy0: ethernet-phy@1 {
|
||||||
/* LAN8710Ai */
|
/* LAN8710Ai */
|
||||||
compatible = "ethernet-phy-id0007.c0f0",
|
compatible = "ethernet-phy-id0007.c0f0",
|
||||||
"ethernet-phy-ieee802.3-c22";
|
"ethernet-phy-ieee802.3-c22";
|
||||||
clocks = <&rcc ETHCK_K>;
|
clocks = <&rcc CK_MCO2>;
|
||||||
reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
|
reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
|
||||||
reset-assert-us = <500>;
|
reset-assert-us = <500>;
|
||||||
reset-deassert-us = <500>;
|
reset-deassert-us = <500>;
|
||||||
|
|
@ -446,6 +445,21 @@ flash0: flash@0 {
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&rcc {
|
||||||
|
/* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
|
||||||
|
clocks = <&rcc CK_MCO2>;
|
||||||
|
clock-names = "ETH_RX_CLK/ETH_REF_CLK";
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
|
||||||
|
* set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
|
||||||
|
* so that MCO2 behaves as a divider for the ETHRX clock here.
|
||||||
|
*/
|
||||||
|
assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
|
||||||
|
assigned-clock-parents = <&rcc PLL4_P>;
|
||||||
|
assigned-clock-rates = <50000000>, <100000000>;
|
||||||
|
};
|
||||||
|
|
||||||
&rng1 {
|
&rng1 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -141,6 +141,7 @@ mdio0 {
|
||||||
compatible = "snps,dwmac-mdio";
|
compatible = "snps,dwmac-mdio";
|
||||||
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
|
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
|
||||||
reset-delay-us = <1000>;
|
reset-delay-us = <1000>;
|
||||||
|
reset-post-delay-us = <1000>;
|
||||||
|
|
||||||
phy0: ethernet-phy@7 {
|
phy0: ethernet-phy@7 {
|
||||||
reg = <7>;
|
reg = <7>;
|
||||||
|
|
|
||||||
|
|
@ -249,30 +249,26 @@
|
||||||
#define STM32MP1_LAST_CLK 232
|
#define STM32MP1_LAST_CLK 232
|
||||||
|
|
||||||
/* SCMI clock identifiers */
|
/* SCMI clock identifiers */
|
||||||
#define CK_SCMI0_HSE 0
|
#define CK_SCMI_HSE 0
|
||||||
#define CK_SCMI0_HSI 1
|
#define CK_SCMI_HSI 1
|
||||||
#define CK_SCMI0_CSI 2
|
#define CK_SCMI_CSI 2
|
||||||
#define CK_SCMI0_LSE 3
|
#define CK_SCMI_LSE 3
|
||||||
#define CK_SCMI0_LSI 4
|
#define CK_SCMI_LSI 4
|
||||||
#define CK_SCMI0_PLL2_Q 5
|
#define CK_SCMI_PLL2_Q 5
|
||||||
#define CK_SCMI0_PLL2_R 6
|
#define CK_SCMI_PLL2_R 6
|
||||||
#define CK_SCMI0_MPU 7
|
#define CK_SCMI_MPU 7
|
||||||
#define CK_SCMI0_AXI 8
|
#define CK_SCMI_AXI 8
|
||||||
#define CK_SCMI0_BSEC 9
|
#define CK_SCMI_BSEC 9
|
||||||
#define CK_SCMI0_CRYP1 10
|
#define CK_SCMI_CRYP1 10
|
||||||
#define CK_SCMI0_GPIOZ 11
|
#define CK_SCMI_GPIOZ 11
|
||||||
#define CK_SCMI0_HASH1 12
|
#define CK_SCMI_HASH1 12
|
||||||
#define CK_SCMI0_I2C4 13
|
#define CK_SCMI_I2C4 13
|
||||||
#define CK_SCMI0_I2C6 14
|
#define CK_SCMI_I2C6 14
|
||||||
#define CK_SCMI0_IWDG1 15
|
#define CK_SCMI_IWDG1 15
|
||||||
#define CK_SCMI0_RNG1 16
|
#define CK_SCMI_RNG1 16
|
||||||
#define CK_SCMI0_RTC 17
|
#define CK_SCMI_RTC 17
|
||||||
#define CK_SCMI0_RTCAPB 18
|
#define CK_SCMI_RTCAPB 18
|
||||||
#define CK_SCMI0_SPI6 19
|
#define CK_SCMI_SPI6 19
|
||||||
#define CK_SCMI0_USART1 20
|
#define CK_SCMI_USART1 20
|
||||||
|
|
||||||
#define CK_SCMI1_PLL3_Q 0
|
|
||||||
#define CK_SCMI1_PLL3_R 1
|
|
||||||
#define CK_SCMI1_MCU 2
|
|
||||||
|
|
||||||
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
|
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
|
||||||
|
|
|
||||||
|
|
@ -107,17 +107,17 @@
|
||||||
#define GPIOK_R 19786
|
#define GPIOK_R 19786
|
||||||
|
|
||||||
/* SCMI reset domain identifiers */
|
/* SCMI reset domain identifiers */
|
||||||
#define RST_SCMI0_SPI6 0
|
#define RST_SCMI_SPI6 0
|
||||||
#define RST_SCMI0_I2C4 1
|
#define RST_SCMI_I2C4 1
|
||||||
#define RST_SCMI0_I2C6 2
|
#define RST_SCMI_I2C6 2
|
||||||
#define RST_SCMI0_USART1 3
|
#define RST_SCMI_USART1 3
|
||||||
#define RST_SCMI0_STGEN 4
|
#define RST_SCMI_STGEN 4
|
||||||
#define RST_SCMI0_GPIOZ 5
|
#define RST_SCMI_GPIOZ 5
|
||||||
#define RST_SCMI0_CRYP1 6
|
#define RST_SCMI_CRYP1 6
|
||||||
#define RST_SCMI0_HASH1 7
|
#define RST_SCMI_HASH1 7
|
||||||
#define RST_SCMI0_RNG1 8
|
#define RST_SCMI_RNG1 8
|
||||||
#define RST_SCMI0_MDMA 9
|
#define RST_SCMI_MDMA 9
|
||||||
#define RST_SCMI0_MCU 10
|
#define RST_SCMI_MCU 10
|
||||||
#define RST_SCMI0_MCU_HOLD_BOOT 11
|
#define RST_SCMI_MCU_HOLD_BOOT 11
|
||||||
|
|
||||||
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
|
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue