ASoC: tlv320aic32x4: Use BIT and GENMASK for bit field definitions
Inter-register definitions should use BIT and GENMASK definitions and also be grouped by what register they belong to. This makes it easy to cross-check with the datasheet and is consistent with other drivers. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Andrew F. Davis
Mark Brown
parent
77bdb58795
commit
0fe7aa39ba
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@ -686,7 +686,7 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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}
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/* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
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snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
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snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_PLL);
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snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
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/* We will fix R value to 1 and will make P & J=K.D as varialble */
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@ -97,61 +97,103 @@ int aic32x4_remove(struct device *dev);
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#define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59)
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#define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60)
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#define AIC32X4_WORD_LEN_16BITS 0x00
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#define AIC32X4_WORD_LEN_20BITS 0x01
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#define AIC32X4_WORD_LEN_24BITS 0x02
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#define AIC32X4_WORD_LEN_32BITS 0x03
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/* Bits, masks, and shifts */
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#define AIC32X4_LADC_EN (1 << 7)
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#define AIC32X4_RADC_EN (1 << 6)
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/* AIC32X4_CLKMUX */
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#define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2)
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#define AIC32X4_PLL_CLKIN_SHIFT (2)
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#define AIC32X4_PLL_CLKIN_MCLK (0x00)
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#define AIC32X4_PLL_CLKIN_BCKL (0x01)
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#define AIC32X4_PLL_CLKIN_GPIO1 (0x02)
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#define AIC32X4_PLL_CLKIN_DIN (0x03)
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#define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0)
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#define AIC32X4_CODEC_CLKIN_SHIFT (0)
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#define AIC32X4_CODEC_CLKIN_MCLK (0x00)
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#define AIC32X4_CODEC_CLKIN_BCLK (0x01)
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#define AIC32X4_CODEC_CLKIN_GPIO1 (0x02)
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#define AIC32X4_CODEC_CLKIN_PLL (0x03)
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#define AIC32X4_I2S_MODE 0x00
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#define AIC32X4_DSP_MODE 0x01
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#define AIC32X4_RIGHT_JUSTIFIED_MODE 0x02
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#define AIC32X4_LEFT_JUSTIFIED_MODE 0x03
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/* AIC32X4_PLLPR */
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#define AIC32X4_PLLEN BIT(7)
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#define AIC32X4_AVDDWEAKDISABLE 0x08
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#define AIC32X4_LDOCTLEN 0x01
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/* AIC32X4_NDAC */
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#define AIC32X4_NDACEN BIT(7)
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#define AIC32X4_LDOIN_18_36 0x01
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#define AIC32X4_LDOIN2HP 0x02
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/* AIC32X4_MDAC */
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#define AIC32X4_MDACEN BIT(7)
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#define AIC32X4_DACSPBLOCK_MASK 0x1f
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#define AIC32X4_ADCSPBLOCK_MASK 0x1f
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/* AIC32X4_NADC */
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#define AIC32X4_NADCEN BIT(7)
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#define AIC32X4_PLLJ_SHIFT 6
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#define AIC32X4_DOSRMSB_SHIFT 4
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/* AIC32X4_MADC */
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#define AIC32X4_MADCEN BIT(7)
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#define AIC32X4_PLLCLKIN 0x03
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/* AIC32X4_BCLKN */
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#define AIC32X4_BCLKEN BIT(7)
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#define AIC32X4_MICBIAS_LDOIN 0x08
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/* AIC32X4_IFACE1 */
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#define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6)
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#define AIC32X4_IFACE1_DATATYPE_SHIFT (6)
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#define AIC32X4_I2S_MODE (0x00)
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#define AIC32X4_DSP_MODE (0x01)
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#define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02)
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#define AIC32X4_LEFT_JUSTIFIED_MODE (0x03)
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#define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4)
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#define AIC32X4_IFACE1_DATALEN_SHIFT (4)
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#define AIC32X4_WORD_LEN_16BITS (0x00)
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#define AIC32X4_WORD_LEN_20BITS (0x01)
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#define AIC32X4_WORD_LEN_24BITS (0x02)
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#define AIC32X4_WORD_LEN_32BITS (0x03)
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#define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2)
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#define AIC32X4_BCLKMASTER BIT(2)
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#define AIC32X4_WCLKMASTER BIT(3)
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/* AIC32X4_IFACE2 */
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#define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0)
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/* AIC32X4_IFACE3 */
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#define AIC32X4_BCLKINV_MASK BIT(3)
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#define AIC32X4_BDIVCLK_MASK GENMASK(1, 0)
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#define AIC32X4_BDIVCLK_SHIFT (0)
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#define AIC32X4_DAC2BCLK (0x00)
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#define AIC32X4_DACMOD2BCLK (0x01)
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#define AIC32X4_ADC2BCLK (0x02)
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#define AIC32X4_ADCMOD2BCLK (0x03)
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/* AIC32X4_DACSETUP */
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#define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2)
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#define AIC32X4_LDAC2RCHN BIT(5)
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#define AIC32X4_LDAC2LCHN BIT(4)
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#define AIC32X4_RDAC2LCHN BIT(3)
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#define AIC32X4_RDAC2RCHN BIT(2)
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/* AIC32X4_DACMUTE */
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#define AIC32X4_MUTEON 0x0C
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/* AIC32X4_ADCSETUP */
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#define AIC32X4_LADC_EN BIT(7)
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#define AIC32X4_RADC_EN BIT(6)
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/* AIC32X4_PWRCFG */
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#define AIC32X4_AVDDWEAKDISABLE BIT(3)
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/* AIC32X4_LDOCTL */
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#define AIC32X4_LDOCTLEN BIT(0)
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/* AIC32X4_CMMODE */
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#define AIC32X4_LDOIN_18_36 BIT(0)
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#define AIC32X4_LDOIN2HP BIT(1)
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/* AIC32X4_MICBIAS */
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#define AIC32X4_MICBIAS_LDOIN BIT(3)
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#define AIC32X4_MICBIAS_2075V 0x60
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/* AIC32X4_LMICPGANIN */
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#define AIC32X4_LMICPGANIN_IN2R_10K 0x10
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#define AIC32X4_LMICPGANIN_CM1L_10K 0x40
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/* AIC32X4_RMICPGANIN */
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#define AIC32X4_RMICPGANIN_IN1L_10K 0x10
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#define AIC32X4_RMICPGANIN_CM1R_10K 0x40
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#define AIC32X4_LMICPGAVOL_NOGAIN 0x80
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#define AIC32X4_RMICPGAVOL_NOGAIN 0x80
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#define AIC32X4_BCLKMASTER 0x08
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#define AIC32X4_WCLKMASTER 0x04
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#define AIC32X4_PLLEN (0x01 << 7)
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#define AIC32X4_NDACEN (0x01 << 7)
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#define AIC32X4_MDACEN (0x01 << 7)
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#define AIC32X4_NADCEN (0x01 << 7)
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#define AIC32X4_MADCEN (0x01 << 7)
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#define AIC32X4_BCLKEN (0x01 << 7)
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#define AIC32X4_DACEN (0x03 << 6)
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#define AIC32X4_RDAC2LCHN (0x02 << 2)
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#define AIC32X4_LDAC2RCHN (0x02 << 4)
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#define AIC32X4_LDAC2LCHN (0x01 << 4)
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#define AIC32X4_RDAC2RCHN (0x01 << 2)
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#define AIC32X4_DAC_CHAN_MASK 0x3c
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#define AIC32X4_SSTEP2WCLK 0x01
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#define AIC32X4_MUTEON 0x0C
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#define AIC32X4_DACMOD2BCLK 0x01
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#endif /* _TLV320AIC32X4_H */
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