thermal: exynos: Remove exynos_tmu_data.c file
Data already present in the exynos_tmu_data.c file has been moved to the appropriate device tree files. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Lukasz Majewski
Eduardo Valentin
parent
1e9a1aea7a
commit
1024cf8b0f
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/*
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* exynos_tmu_data.c - Samsung EXYNOS tmu data file
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*
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* Copyright (C) 2013 Samsung Electronics
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include "exynos_thermal_common.h"
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#include "exynos_tmu.h"
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struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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.tmu_data = {
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{
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.threshold = 80,
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.trigger_levels[0] = 5,
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.trigger_levels[1] = 20,
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.trigger_levels[2] = 30,
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.trigger_enable[0] = true,
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.trigger_enable[1] = true,
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.trigger_enable[2] = true,
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.trigger_enable[3] = false,
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.trigger_type[0] = THROTTLE_ACTIVE,
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.trigger_type[1] = THROTTLE_ACTIVE,
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.trigger_type[2] = SW_TRIP,
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.max_trigger_level = 4,
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.non_hw_trigger_levels = 3,
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.gain = 15,
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.reference_voltage = 7,
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.cal_type = TYPE_ONE_POINT_TRIMMING,
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.min_efuse_value = 40,
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.max_efuse_value = 100,
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.first_point_trim = 25,
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.second_point_trim = 85,
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.default_temp_offset = 50,
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.type = SOC_ARCH_EXYNOS4210,
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},
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},
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.tmu_count = 1,
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};
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#define EXYNOS3250_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 70, \
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.trigger_levels[1] = 95, \
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.trigger_levels[2] = 110, \
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.trigger_levels[3] = 120, \
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.trigger_enable[0] = true, \
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.trigger_enable[1] = true, \
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.trigger_enable[2] = true, \
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.trigger_enable[3] = false, \
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.trigger_type[0] = THROTTLE_ACTIVE, \
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.trigger_type[1] = THROTTLE_ACTIVE, \
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.trigger_type[2] = SW_TRIP, \
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.trigger_type[3] = HW_TRIP, \
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.max_trigger_level = 4, \
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.non_hw_trigger_levels = 3, \
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.gain = 8, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_TWO_POINT_TRIMMING, \
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.efuse_value = 55, \
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.min_efuse_value = 40, \
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.max_efuse_value = 100, \
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.first_point_trim = 25, \
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.second_point_trim = 85, \
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.default_temp_offset = 50
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struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
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.tmu_data = {
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{
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EXYNOS3250_TMU_DATA,
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.type = SOC_ARCH_EXYNOS3250,
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},
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},
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.tmu_count = 1,
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};
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#define EXYNOS4412_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 70, \
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.trigger_levels[1] = 95, \
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.trigger_levels[2] = 110, \
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.trigger_levels[3] = 120, \
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.trigger_enable[0] = true, \
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.trigger_enable[1] = true, \
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.trigger_enable[2] = true, \
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.trigger_enable[3] = false, \
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.trigger_type[0] = THROTTLE_ACTIVE, \
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.trigger_type[1] = THROTTLE_ACTIVE, \
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.trigger_type[2] = SW_TRIP, \
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.trigger_type[3] = HW_TRIP, \
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.max_trigger_level = 4, \
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.non_hw_trigger_levels = 3, \
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.gain = 8, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_ONE_POINT_TRIMMING, \
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.efuse_value = 55, \
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.min_efuse_value = 40, \
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.max_efuse_value = 100, \
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.first_point_trim = 25, \
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.second_point_trim = 85, \
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.default_temp_offset = 50
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struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
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.tmu_data = {
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{
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EXYNOS4412_TMU_DATA,
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.type = SOC_ARCH_EXYNOS4412,
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},
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},
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.tmu_count = 1,
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};
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struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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.tmu_data = {
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{
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EXYNOS4412_TMU_DATA,
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.type = SOC_ARCH_EXYNOS5250,
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},
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},
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.tmu_count = 1,
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};
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#define __EXYNOS5260_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 85, \
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.trigger_levels[1] = 103, \
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.trigger_levels[2] = 110, \
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.trigger_levels[3] = 120, \
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.trigger_enable[0] = true, \
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.trigger_enable[1] = true, \
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.trigger_enable[2] = true, \
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.trigger_enable[3] = false, \
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.trigger_type[0] = THROTTLE_ACTIVE, \
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.trigger_type[1] = THROTTLE_ACTIVE, \
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.trigger_type[2] = SW_TRIP, \
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.trigger_type[3] = HW_TRIP, \
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.max_trigger_level = 4, \
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.non_hw_trigger_levels = 3, \
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.gain = 8, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_ONE_POINT_TRIMMING, \
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.efuse_value = 55, \
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.min_efuse_value = 40, \
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.max_efuse_value = 100, \
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.first_point_trim = 25, \
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.second_point_trim = 85, \
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.default_temp_offset = 50,
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#define EXYNOS5260_TMU_DATA \
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__EXYNOS5260_TMU_DATA \
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.type = SOC_ARCH_EXYNOS5260
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struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
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.tmu_data = {
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{ EXYNOS5260_TMU_DATA },
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{ EXYNOS5260_TMU_DATA },
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{ EXYNOS5260_TMU_DATA },
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{ EXYNOS5260_TMU_DATA },
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{ EXYNOS5260_TMU_DATA },
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},
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.tmu_count = 5,
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};
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#define EXYNOS5420_TMU_DATA \
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__EXYNOS5260_TMU_DATA \
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.type = SOC_ARCH_EXYNOS5420
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#define EXYNOS5420_TMU_DATA_SHARED \
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__EXYNOS5260_TMU_DATA \
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.type = SOC_ARCH_EXYNOS5420_TRIMINFO
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struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
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.tmu_data = {
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{ EXYNOS5420_TMU_DATA },
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{ EXYNOS5420_TMU_DATA },
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{ EXYNOS5420_TMU_DATA_SHARED },
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{ EXYNOS5420_TMU_DATA_SHARED },
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{ EXYNOS5420_TMU_DATA_SHARED },
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},
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.tmu_count = 5,
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};
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#define EXYNOS5440_TMU_DATA \
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.trigger_levels[0] = 100, \
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.trigger_levels[4] = 105, \
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.trigger_enable[0] = 1, \
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.trigger_type[0] = SW_TRIP, \
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.trigger_type[4] = HW_TRIP, \
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.max_trigger_level = 5, \
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.non_hw_trigger_levels = 1, \
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.gain = 5, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_ONE_POINT_TRIMMING, \
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.efuse_value = 0x5b2d, \
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.min_efuse_value = 16, \
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.max_efuse_value = 76, \
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.first_point_trim = 25, \
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.second_point_trim = 70, \
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.default_temp_offset = 25, \
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.type = SOC_ARCH_EXYNOS5440
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struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
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.tmu_data = {
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{ EXYNOS5440_TMU_DATA } ,
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{ EXYNOS5440_TMU_DATA } ,
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{ EXYNOS5440_TMU_DATA } ,
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},
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.tmu_count = 3,
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};
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