net: stmmac: dwmac-meson8b: simplify clock registration
To goal of this patch is to simplify the registration of the RGMII TX clock (and it's parent clocks). This is achieved by: - introducing the meson8b_dwmac_register_clk helper-function to remove code duplication when registering a single clock (this saves a few lines since we have 4 clocks internally) - using devm_add_action_or_reset to disable the RGMII TX clock automatically when needed. This also allows us to re-use the standard stmmac_pltfr_remove function. - devm_kasprintf() and devm_kstrdup() are not used anymore to generate the clock name (these are replaced by a variable on the stack) because the common clock framework already uses kstrdup() internally. No functional changes intended. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -55,17 +55,11 @@ struct meson8b_dwmac {
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phy_interface_t phy_mode;
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struct clk_mux m250_mux;
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struct clk *m250_mux_clk;
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struct clk *m250_mux_parent[MUX_CLK_NUM_PARENTS];
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struct clk_divider m250_div;
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struct clk *m250_div_clk;
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struct clk_fixed_factor fixed_div2;
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struct clk *fixed_div2_clk;
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struct clk_gate rgmii_tx_en;
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struct clk *rgmii_tx_en_clk;
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struct clk *rgmii_tx_clk;
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u32 tx_delay_ns;
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};
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@ -82,106 +76,95 @@ static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
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writel(data, dwmac->regs + reg);
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}
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static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
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const char *name_suffix,
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const char **parent_names,
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int num_parents,
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const struct clk_ops *ops,
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struct clk_hw *hw)
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{
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struct device *dev = &dwmac->pdev->dev;
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struct clk_init_data init;
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char clk_name[32];
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snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dev),
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name_suffix);
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init.name = clk_name;
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init.ops = ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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hw->init = &init;
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return devm_clk_register(dev, hw);
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}
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static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
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{
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struct clk_init_data init;
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int i, ret;
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struct clk *clk;
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struct device *dev = &dwmac->pdev->dev;
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char clk_name[32];
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const char *clk_div_parents[1];
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const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
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const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS];
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/* get the mux parents from DT */
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for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
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char name[16];
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snprintf(name, sizeof(name), "clkin%d", i);
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dwmac->m250_mux_parent[i] = devm_clk_get(dev, name);
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if (IS_ERR(dwmac->m250_mux_parent[i])) {
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ret = PTR_ERR(dwmac->m250_mux_parent[i]);
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clk = devm_clk_get(dev, name);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Missing clock %s\n", name);
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return ret;
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}
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mux_parent_names[i] =
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__clk_get_name(dwmac->m250_mux_parent[i]);
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mux_parent_names[i] = __clk_get_name(clk);
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}
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/* create the m250_mux */
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snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev));
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init.name = clk_name;
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init.ops = &clk_mux_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = mux_parent_names;
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init.num_parents = MUX_CLK_NUM_PARENTS;
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dwmac->m250_mux.reg = dwmac->regs + PRG_ETH0;
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dwmac->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
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dwmac->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
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dwmac->m250_mux.flags = 0;
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dwmac->m250_mux.table = NULL;
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dwmac->m250_mux.hw.init = &init;
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dwmac->m250_mux_clk = devm_clk_register(dev, &dwmac->m250_mux.hw);
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if (WARN_ON(IS_ERR(dwmac->m250_mux_clk)))
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return PTR_ERR(dwmac->m250_mux_clk);
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/* create the m250_div */
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snprintf(clk_name, sizeof(clk_name), "%s#m250_div", dev_name(dev));
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init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL);
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init.ops = &clk_divider_ops;
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init.flags = CLK_SET_RATE_PARENT;
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clk_div_parents[0] = __clk_get_name(dwmac->m250_mux_clk);
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init.parent_names = clk_div_parents;
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init.num_parents = ARRAY_SIZE(clk_div_parents);
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clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names,
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MUX_CLK_NUM_PARENTS, &clk_mux_ops,
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&dwmac->m250_mux.hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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parent_name = __clk_get_name(clk);
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dwmac->m250_div.reg = dwmac->regs + PRG_ETH0;
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dwmac->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
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dwmac->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
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dwmac->m250_div.hw.init = &init;
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dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO |
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CLK_DIVIDER_ROUND_CLOSEST;
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clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1,
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&clk_divider_ops,
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&dwmac->m250_div.hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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dwmac->m250_div_clk = devm_clk_register(dev, &dwmac->m250_div.hw);
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if (WARN_ON(IS_ERR(dwmac->m250_div_clk)))
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return PTR_ERR(dwmac->m250_div_clk);
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/* create the fixed_div2 */
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snprintf(clk_name, sizeof(clk_name), "%s#fixed_div2", dev_name(dev));
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init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL);
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init.ops = &clk_fixed_factor_ops;
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init.flags = CLK_SET_RATE_PARENT;
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clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk);
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init.parent_names = clk_div_parents;
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init.num_parents = ARRAY_SIZE(clk_div_parents);
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parent_name = __clk_get_name(clk);
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dwmac->fixed_div2.mult = 1;
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dwmac->fixed_div2.div = 2;
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dwmac->fixed_div2.hw.init = &init;
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dwmac->fixed_div2_clk = devm_clk_register(dev, &dwmac->fixed_div2.hw);
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if (WARN_ON(IS_ERR(dwmac->fixed_div2_clk)))
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return PTR_ERR(dwmac->fixed_div2_clk);
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/* create the rgmii_tx_en */
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init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#rgmii_tx_en",
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dev_name(dev));
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init.ops = &clk_gate_ops;
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init.flags = CLK_SET_RATE_PARENT;
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clk_div_parents[0] = __clk_get_name(dwmac->fixed_div2_clk);
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init.parent_names = clk_div_parents;
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init.num_parents = ARRAY_SIZE(clk_div_parents);
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clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_name, 1,
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&clk_fixed_factor_ops,
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&dwmac->fixed_div2.hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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parent_name = __clk_get_name(clk);
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dwmac->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
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dwmac->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;
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dwmac->rgmii_tx_en.hw.init = &init;
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clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_name, 1,
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&clk_gate_ops,
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&dwmac->rgmii_tx_en.hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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dwmac->rgmii_tx_en_clk = devm_clk_register(dev,
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&dwmac->rgmii_tx_en.hw);
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if (WARN_ON(IS_ERR(dwmac->rgmii_tx_en_clk)))
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return PTR_ERR(dwmac->rgmii_tx_en_clk);
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dwmac->rgmii_tx_clk = clk;
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return 0;
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}
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@ -219,19 +202,23 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
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* a register) based on the line-speed (125MHz for Gbit speeds,
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* 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s).
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*/
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ret = clk_set_rate(dwmac->rgmii_tx_en_clk, 125 * 1000 * 1000);
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ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);
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if (ret) {
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dev_err(&dwmac->pdev->dev,
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"failed to set RGMII TX clock\n");
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return ret;
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}
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ret = clk_prepare_enable(dwmac->rgmii_tx_en_clk);
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ret = clk_prepare_enable(dwmac->rgmii_tx_clk);
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if (ret) {
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dev_err(&dwmac->pdev->dev,
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"failed to enable the RGMII TX clock\n");
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return ret;
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}
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devm_add_action_or_reset(&dwmac->pdev->dev,
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(void(*)(void *))clk_disable_unprepare,
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dwmac->rgmii_tx_clk);
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break;
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case PHY_INTERFACE_MODE_RMII:
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@ -317,29 +304,16 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
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ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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if (ret)
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goto err_clk_disable;
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goto err_remove_config_dt;
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return 0;
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err_clk_disable:
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if (phy_interface_mode_is_rgmii(dwmac->phy_mode))
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clk_disable_unprepare(dwmac->rgmii_tx_en_clk);
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err_remove_config_dt:
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stmmac_remove_config_dt(pdev, plat_dat);
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return ret;
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}
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static int meson8b_dwmac_remove(struct platform_device *pdev)
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{
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struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
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if (phy_interface_mode_is_rgmii(dwmac->phy_mode))
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clk_disable_unprepare(dwmac->rgmii_tx_en_clk);
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return stmmac_pltfr_remove(pdev);
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}
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static const struct of_device_id meson8b_dwmac_match[] = {
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{ .compatible = "amlogic,meson8b-dwmac" },
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{ .compatible = "amlogic,meson-gxbb-dwmac" },
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@ -349,7 +323,7 @@ MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
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static struct platform_driver meson8b_dwmac_driver = {
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.probe = meson8b_dwmac_probe,
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.remove = meson8b_dwmac_remove,
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.remove = stmmac_pltfr_remove,
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.driver = {
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.name = "meson8b-dwmac",
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.pm = &stmmac_pltfr_pm_ops,
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