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Merge branches 'ib-mfd-arm-iio-pwm-4.11', 'ib-mfd-input-4.11-1', 'ib-mfd-mtd-4.11' and 'ib-mfd-power-supply-4.11' into ibs-for-mfd-merged

This commit is contained in:
Lee Jones 2017-02-13 09:29:15 +00:00
parent 93fbe91b55 6ccc3a3381 87eb832ae9 888f97435a
commit 128818f126
14 changed files with 1712 additions and 521 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

88
Documentation/mtd/intel-spi.txt Normal file
View File

@ -0,0 +1,88 @@
Upgrading BIOS using intel-spi
------------------------------
Many Intel CPUs like Baytrail and Braswell include SPI serial flash host
controller which is used to hold BIOS and other platform specific data.
Since contents of the SPI serial flash is crucial for machine to function,
it is typically protected by different hardware protection mechanisms to
avoid accidental (or on purpose) overwrite of the content.
Not all manufacturers protect the SPI serial flash, mainly because it
allows upgrading the BIOS image directly from an OS.
The intel-spi driver makes it possible to read and write the SPI serial
flash, if certain protection bits are not set and locked. If it finds
any of them set, the whole MTD device is made read-only to prevent
partial overwrites. By default the driver exposes SPI serial flash
contents as read-only but it can be changed from kernel command line,
passing "intel-spi.writeable=1".
Please keep in mind that overwriting the BIOS image on SPI serial flash
might render the machine unbootable and requires special equipment like
Dediprog to revive. You have been warned!
Below are the steps how to upgrade MinnowBoard MAX BIOS directly from
Linux.
1) Download and extract the latest Minnowboard MAX BIOS SPI image
[1]. At the time writing this the latest image is v92.
2) Install mtd-utils package [2]. We need this in order to erase the SPI
serial flash. Distros like Debian and Fedora have this prepackaged with
name "mtd-utils".
3) Add "intel-spi.writeable=1" to the kernel command line and reboot
the board (you can also reload the driver passing "writeable=1" as
module parameter to modprobe).
4) Once the board is up and running again, find the right MTD partition
(it is named as "BIOS"):
# cat /proc/mtd
dev: size erasesize name
mtd0: 00800000 00001000 "BIOS"
So here it will be /dev/mtd0 but it may vary.
5) Make backup of the existing image first:
# dd if=/dev/mtd0ro of=bios.bak
16384+0 records in
16384+0 records out
8388608 bytes (8.4 MB) copied, 10.0269 s, 837 kB/s
6) Verify the backup
# sha1sum /dev/mtd0ro bios.bak
fdbb011920572ca6c991377c4b418a0502668b73 /dev/mtd0ro
fdbb011920572ca6c991377c4b418a0502668b73 bios.bak
The SHA1 sums must match. Otherwise do not continue any further!
7) Erase the SPI serial flash. After this step, do not reboot the
board! Otherwise it will not start anymore.
# flash_erase /dev/mtd0 0 0
Erasing 4 Kibyte @ 7ff000 -- 100 % complete
8) Once completed without errors you can write the new BIOS image:
# dd if=MNW2MAX1.X64.0092.R01.1605221712.bin of=/dev/mtd0
9) Verify that the new content of the SPI serial flash matches the new
BIOS image:
# sha1sum /dev/mtd0ro MNW2MAX1.X64.0092.R01.1605221712.bin
9b4df9e4be2057fceec3a5529ec3d950836c87a2 /dev/mtd0ro
9b4df9e4be2057fceec3a5529ec3d950836c87a2 MNW2MAX1.X64.0092.R01.1605221712.bin
The SHA1 sums should match.
10) Now you can reboot your board and observe the new BIOS starting up
properly.
References
----------
[1] https://firmware.intel.com/sites/default/files/MinnowBoard.MAX_.X64.92.R01.zip
[2] http://www.linux-mtd.infradead.org/

454
drivers/input/keyboard/cros_ec_keyb.c
View File

@ -34,6 +34,8 @@
#include <linux/mfd/cros_ec.h>
#include <linux/mfd/cros_ec_commands.h>
#include <asm/unaligned.h>
/*
* @rows: Number of rows in the keypad
* @cols: Number of columns in the keypad
@ -43,8 +45,9 @@
* @valid_keys: bitmap of existing keys for each matrix column
* @old_kb_state: bitmap of keys pressed last scan
* @dev: Device pointer
* @idev: Input device
* @ec: Top level ChromeOS device to use to talk to EC
* @idev: The input device for the matrix keys.
* @bs_idev: The input device for non-matrix buttons and switches (or NULL).
* @notifier: interrupt event notifier for transport devices
*/
struct cros_ec_keyb {
@ -57,12 +60,64 @@ struct cros_ec_keyb {
uint8_t *old_kb_state;
struct device *dev;
struct input_dev *idev;
struct cros_ec_device *ec;
struct input_dev *idev;
struct input_dev *bs_idev;
struct notifier_block notifier;
};
/**
* cros_ec_bs_map - Struct mapping Linux keycodes to EC button/switch bitmap
* #defines
*
* @ev_type: The type of the input event to generate (e.g., EV_KEY).
* @code: A linux keycode
* @bit: A #define like EC_MKBP_POWER_BUTTON or EC_MKBP_LID_OPEN
* @inverted: If the #define and EV_SW have opposite meanings, this is true.
* Only applicable to switches.
*/
struct cros_ec_bs_map {
unsigned int ev_type;
unsigned int code;
u8 bit;
bool inverted;
};
/* cros_ec_keyb_bs - Map EC button/switch #defines into kernel ones */
static const struct cros_ec_bs_map cros_ec_keyb_bs[] = {
/* Buttons */
{
.ev_type = EV_KEY,
.code = KEY_POWER,
.bit = EC_MKBP_POWER_BUTTON,
},
{
.ev_type = EV_KEY,
.code = KEY_VOLUMEUP,
.bit = EC_MKBP_VOL_UP,
},
{
.ev_type = EV_KEY,
.code = KEY_VOLUMEDOWN,
.bit = EC_MKBP_VOL_DOWN,
},
/* Switches */
{
.ev_type = EV_SW,
.code = SW_LID,
.bit = EC_MKBP_LID_OPEN,
.inverted = true,
},
{
.ev_type = EV_SW,
.code = SW_TABLET_MODE,
.bit = EC_MKBP_TABLET_MODE,
},
};
/*
* Returns true when there is at least one combination of pressed keys that
* results in ghosting.
@ -149,20 +204,33 @@ static void cros_ec_keyb_process(struct cros_ec_keyb *ckdev,
input_sync(ckdev->idev);
}
static int cros_ec_keyb_open(struct input_dev *dev)
/**
* cros_ec_keyb_report_bs - Report non-matrixed buttons or switches
*
* This takes a bitmap of buttons or switches from the EC and reports events,
* syncing at the end.
*
* @ckdev: The keyboard device.
* @ev_type: The input event type (e.g., EV_KEY).
* @mask: A bitmap of buttons from the EC.
*/
static void cros_ec_keyb_report_bs(struct cros_ec_keyb *ckdev,
unsigned int ev_type, u32 mask)
{
struct cros_ec_keyb *ckdev = input_get_drvdata(dev);
struct input_dev *idev = ckdev->bs_idev;
int i;
return blocking_notifier_chain_register(&ckdev->ec->event_notifier,
&ckdev->notifier);
}
for (i = 0; i < ARRAY_SIZE(cros_ec_keyb_bs); i++) {
const struct cros_ec_bs_map *map = &cros_ec_keyb_bs[i];
static void cros_ec_keyb_close(struct input_dev *dev)
{
struct cros_ec_keyb *ckdev = input_get_drvdata(dev);
if (map->ev_type != ev_type)
continue;
blocking_notifier_chain_unregister(&ckdev->ec->event_notifier,
&ckdev->notifier);
input_event(idev, ev_type, map->code,
!!(mask & BIT(map->bit)) ^ map->inverted);
}
input_sync(idev);
}
static int cros_ec_keyb_work(struct notifier_block *nb,
@ -170,22 +238,54 @@ static int cros_ec_keyb_work(struct notifier_block *nb,
{
struct cros_ec_keyb *ckdev = container_of(nb, struct cros_ec_keyb,
notifier);
u32 val;
unsigned int ev_type;
if (ckdev->ec->event_data.event_type != EC_MKBP_EVENT_KEY_MATRIX)
switch (ckdev->ec->event_data.event_type) {
case EC_MKBP_EVENT_KEY_MATRIX:
/*
* If EC is not the wake source, discard key state changes
* during suspend.
*/
if (queued_during_suspend)
return NOTIFY_OK;
if (ckdev->ec->event_size != ckdev->cols) {
dev_err(ckdev->dev,
"Discarded incomplete key matrix event.\n");
return NOTIFY_OK;
}
cros_ec_keyb_process(ckdev,
ckdev->ec->event_data.data.key_matrix,
ckdev->ec->event_size);
break;
case EC_MKBP_EVENT_BUTTON:
case EC_MKBP_EVENT_SWITCH:
/*
* If EC is not the wake source, discard key state
* changes during suspend. Switches will be re-checked in
* cros_ec_keyb_resume() to be sure nothing is lost.
*/
if (queued_during_suspend)
return NOTIFY_OK;
if (ckdev->ec->event_data.event_type == EC_MKBP_EVENT_BUTTON) {
val = get_unaligned_le32(
&ckdev->ec->event_data.data.buttons);
ev_type = EV_KEY;
} else {
val = get_unaligned_le32(
&ckdev->ec->event_data.data.switches);
ev_type = EV_SW;
}
cros_ec_keyb_report_bs(ckdev, ev_type, val);
break;
default:
return NOTIFY_DONE;
/*
* If EC is not the wake source, discard key state changes during
* suspend.
*/
if (queued_during_suspend)
return NOTIFY_OK;
if (ckdev->ec->event_size != ckdev->cols) {
dev_err(ckdev->dev,
"Discarded incomplete key matrix event.\n");
return NOTIFY_OK;
}
cros_ec_keyb_process(ckdev, ckdev->ec->event_data.data.key_matrix,
ckdev->ec->event_size);
return NOTIFY_OK;
}
@ -213,22 +313,228 @@ static void cros_ec_keyb_compute_valid_keys(struct cros_ec_keyb *ckdev)
}
}
static int cros_ec_keyb_probe(struct platform_device *pdev)
/**
* cros_ec_keyb_info - Wrap the EC command EC_CMD_MKBP_INFO
*
* This wraps the EC_CMD_MKBP_INFO, abstracting out all of the marshalling and
* unmarshalling and different version nonsense into something simple.
*
* @ec_dev: The EC device
* @info_type: Either EC_MKBP_INFO_SUPPORTED or EC_MKBP_INFO_CURRENT.
* @event_type: Either EC_MKBP_EVENT_BUTTON or EC_MKBP_EVENT_SWITCH. Actually
* in some cases this could be EC_MKBP_EVENT_KEY_MATRIX or
* EC_MKBP_EVENT_HOST_EVENT too but we don't use in this driver.
* @result: Where we'll store the result; a union
* @result_size: The size of the result. Expected to be the size of one of
* the elements in the union.
*
* Returns 0 if no error or -error upon error.
*/
static int cros_ec_keyb_info(struct cros_ec_device *ec_dev,
enum ec_mkbp_info_type info_type,
enum ec_mkbp_event event_type,
union ec_response_get_next_data *result,
size_t result_size)
{
struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct cros_ec_keyb *ckdev;
struct ec_params_mkbp_info *params;
struct cros_ec_command *msg;
int ret;
msg = kzalloc(sizeof(*msg) + max_t(size_t, result_size,
sizeof(*params)), GFP_KERNEL);
if (!msg)
return -ENOMEM;
msg->command = EC_CMD_MKBP_INFO;
msg->version = 1;
msg->outsize = sizeof(*params);
msg->insize = result_size;
params = (struct ec_params_mkbp_info *)msg->data;
params->info_type = info_type;
params->event_type = event_type;
ret = cros_ec_cmd_xfer(ec_dev, msg);
if (ret < 0) {
dev_warn(ec_dev->dev, "Transfer error %d/%d: %d\n",
(int)info_type, (int)event_type, ret);
} else if (msg->result == EC_RES_INVALID_VERSION) {
/* With older ECs we just return 0 for everything */
memset(result, 0, result_size);
ret = 0;
} else if (msg->result != EC_RES_SUCCESS) {
dev_warn(ec_dev->dev, "Error getting info %d/%d: %d\n",
(int)info_type, (int)event_type, msg->result);
ret = -EPROTO;
} else if (ret != result_size) {
dev_warn(ec_dev->dev, "Wrong size %d/%d: %d != %zu\n",
(int)info_type, (int)event_type,
ret, result_size);
ret = -EPROTO;
} else {
memcpy(result, msg->data, result_size);
ret = 0;
}
kfree(msg);
return ret;
}
/**
* cros_ec_keyb_query_switches - Query the state of switches and report
*
* This will ask the EC about the current state of switches and report to the
* kernel. Note that we don't query for buttons because they are more
* transitory and we'll get an update on the next release / press.
*
* @ckdev: The keyboard device
*
* Returns 0 if no error or -error upon error.
*/
static int cros_ec_keyb_query_switches(struct cros_ec_keyb *ckdev)
{
struct cros_ec_device *ec_dev = ckdev->ec;
union ec_response_get_next_data event_data = {};
int ret;
ret = cros_ec_keyb_info(ec_dev, EC_MKBP_INFO_CURRENT,
EC_MKBP_EVENT_SWITCH, &event_data,
sizeof(event_data.switches));
if (ret)
return ret;
cros_ec_keyb_report_bs(ckdev, EV_SW,
get_unaligned_le32(&event_data.switches));
return 0;
}
/**
* cros_ec_keyb_resume - Resume the keyboard
*
* We use the resume notification as a chance to query the EC for switches.
*
* @dev: The keyboard device
*
* Returns 0 if no error or -error upon error.
*/
static __maybe_unused int cros_ec_keyb_resume(struct device *dev)
{
struct cros_ec_keyb *ckdev = dev_get_drvdata(dev);
if (ckdev->bs_idev)
return cros_ec_keyb_query_switches(ckdev);
return 0;
}
/**
* cros_ec_keyb_register_bs - Register non-matrix buttons/switches
*
* Handles all the bits of the keyboard driver related to non-matrix buttons
* and switches, including asking the EC about which are present and telling
* the kernel to expect them.
*
* If this device has no support for buttons and switches we'll return no error
* but the ckdev->bs_idev will remain NULL when this function exits.
*
* @ckdev: The keyboard device
*
* Returns 0 if no error or -error upon error.
*/
static int cros_ec_keyb_register_bs(struct cros_ec_keyb *ckdev)
{
struct cros_ec_device *ec_dev = ckdev->ec;
struct device *dev = ckdev->dev;
struct input_dev *idev;
struct device_node *np;
union ec_response_get_next_data event_data = {};
const char *phys;
u32 buttons;
u32 switches;
int ret;
int i;
ret = cros_ec_keyb_info(ec_dev, EC_MKBP_INFO_SUPPORTED,
EC_MKBP_EVENT_BUTTON, &event_data,
sizeof(event_data.buttons));
if (ret)
return ret;
buttons = get_unaligned_le32(&event_data.buttons);
ret = cros_ec_keyb_info(ec_dev, EC_MKBP_INFO_SUPPORTED,
EC_MKBP_EVENT_SWITCH, &event_data,
sizeof(event_data.switches));
if (ret)
return ret;
switches = get_unaligned_le32(&event_data.switches);
if (!buttons && !switches)
return 0;
/*
* We call the non-matrix buttons/switches 'input1', if present.
* Allocate phys before input dev, to ensure correct tear-down
* ordering.
*/
phys = devm_kasprintf(dev, GFP_KERNEL, "%s/input1", ec_dev->phys_name);
if (!phys)
return -ENOMEM;
idev = devm_input_allocate_device(dev);
if (!idev)
return -ENOMEM;
idev->name = "cros_ec_buttons";
idev->phys = phys;
__set_bit(EV_REP, idev->evbit);
idev->id.bustype = BUS_VIRTUAL;
idev->id.version = 1;
idev->id.product = 0;
idev->dev.parent = dev;
input_set_drvdata(idev, ckdev);
ckdev->bs_idev = idev;
for (i = 0; i < ARRAY_SIZE(cros_ec_keyb_bs); i++) {
const struct cros_ec_bs_map *map = &cros_ec_keyb_bs[i];
if (buttons & BIT(map->bit))
input_set_capability(idev, map->ev_type, map->code);
}
ret = cros_ec_keyb_query_switches(ckdev);
if (ret) {
dev_err(dev, "cannot query switches\n");
return ret;
}
ret = input_register_device(ckdev->bs_idev);
if (ret) {
dev_err(dev, "cannot register input device\n");
return ret;
}
return 0;
}
/**
* cros_ec_keyb_register_bs - Register matrix keys
*
* Handles all the bits of the keyboard driver related to matrix keys.
*
* @ckdev: The keyboard device
*
* Returns 0 if no error or -error upon error.
*/
static int cros_ec_keyb_register_matrix(struct cros_ec_keyb *ckdev)
{
struct cros_ec_device *ec_dev = ckdev->ec;
struct device *dev = ckdev->dev;
struct input_dev *idev;
const char *phys;
int err;
np = pdev->dev.of_node;
if (!np)
return -ENODEV;
ckdev = devm_kzalloc(dev, sizeof(*ckdev), GFP_KERNEL);
if (!ckdev)
return -ENOMEM;
err = matrix_keypad_parse_of_params(dev, &ckdev->rows, &ckdev->cols);
if (err)
return err;
@ -241,27 +547,28 @@ static int cros_ec_keyb_probe(struct platform_device *pdev)
if (!ckdev->old_kb_state)
return -ENOMEM;
/*
* We call the keyboard matrix 'input0'. Allocate phys before input
* dev, to ensure correct tear-down ordering.
*/
phys = devm_kasprintf(dev, GFP_KERNEL, "%s/input0", ec_dev->phys_name);
if (!phys)
return -ENOMEM;
idev = devm_input_allocate_device(dev);
if (!idev)
return -ENOMEM;
ckdev->ec = ec;
ckdev->notifier.notifier_call = cros_ec_keyb_work;
ckdev->dev = dev;
dev_set_drvdata(dev, ckdev);
idev->name = CROS_EC_DEV_NAME;
idev->phys = ec->phys_name;
idev->phys = phys;
__set_bit(EV_REP, idev->evbit);
idev->id.bustype = BUS_VIRTUAL;
idev->id.version = 1;
idev->id.product = 0;
idev->dev.parent = dev;
idev->open = cros_ec_keyb_open;
idev->close = cros_ec_keyb_close;
ckdev->ghost_filter = of_property_read_bool(np,
ckdev->ghost_filter = of_property_read_bool(dev->of_node,
"google,needs-ghost-filter");
err = matrix_keypad_build_keymap(NULL, NULL, ckdev->rows, ckdev->cols,
@ -287,6 +594,57 @@ static int cros_ec_keyb_probe(struct platform_device *pdev)
return 0;
}
static int cros_ec_keyb_probe(struct platform_device *pdev)
{
struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct cros_ec_keyb *ckdev;
int err;
if (!dev->of_node)
return -ENODEV;
ckdev = devm_kzalloc(dev, sizeof(*ckdev), GFP_KERNEL);
if (!ckdev)
return -ENOMEM;
ckdev->ec = ec;
ckdev->dev = dev;
dev_set_drvdata(dev, ckdev);
err = cros_ec_keyb_register_matrix(ckdev);
if (err) {
dev_err(dev, "cannot register matrix inputs: %d\n", err);
return err;
}
err = cros_ec_keyb_register_bs(ckdev);
if (err) {
dev_err(dev, "cannot register non-matrix inputs: %d\n", err);
return err;
}
ckdev->notifier.notifier_call = cros_ec_keyb_work;
err = blocking_notifier_chain_register(&ckdev->ec->event_notifier,
&ckdev->notifier);
if (err) {
dev_err(dev, "cannot register notifier: %d\n", err);
return err;
}
return 0;
}
static int cros_ec_keyb_remove(struct platform_device *pdev)
{
struct cros_ec_keyb *ckdev = dev_get_drvdata(&pdev->dev);
blocking_notifier_chain_unregister(&ckdev->ec->event_notifier,
&ckdev->notifier);
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id cros_ec_keyb_of_match[] = {
{ .compatible = "google,cros-ec-keyb" },
@ -295,11 +653,15 @@ static const struct of_device_id cros_ec_keyb_of_match[] = {
MODULE_DEVICE_TABLE(of, cros_ec_keyb_of_match);
#endif
static const SIMPLE_DEV_PM_OPS(cros_ec_keyb_pm_ops, NULL, cros_ec_keyb_resume);
static struct platform_driver cros_ec_keyb_driver = {
.probe = cros_ec_keyb_probe,
.remove = cros_ec_keyb_remove,
.driver = {
.name = "cros-ec-keyb",
.of_match_table = of_match_ptr(cros_ec_keyb_of_match),
.pm = &cros_ec_keyb_pm_ops,
},
};

131
drivers/mfd/lpc_ich.c
View File

@ -56,6 +56,7 @@
* document number TBD : Wildcat Point-LP
* document number TBD : 9 Series
* document number TBD : Lewisburg
* document number TBD : Apollo Lake SoC
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@ -83,6 +84,17 @@
#define ACPIBASE_GCS_OFF 0x3410
#define ACPIBASE_GCS_END 0x3414
#define SPIBASE_BYT 0x54
#define SPIBASE_BYT_SZ 512
#define SPIBASE_BYT_EN BIT(1)
#define SPIBASE_LPT 0x3800
#define SPIBASE_LPT_SZ 512
#define BCR 0xdc
#define BCR_WPD BIT(0)
#define SPIBASE_APL_SZ 4096
#define GPIOBASE_ICH0 0x58
#define GPIOCTRL_ICH0 0x5C
#define GPIOBASE_ICH6 0x48
@ -133,6 +145,12 @@ static struct resource gpio_ich_res[] = {
},
};
static struct resource intel_spi_res[] = {
{
.flags = IORESOURCE_MEM,
}
};
static struct mfd_cell lpc_ich_wdt_cell = {
.name = "iTCO_wdt",
.num_resources = ARRAY_SIZE(wdt_ich_res),
@ -147,6 +165,14 @@ static struct mfd_cell lpc_ich_gpio_cell = {
.ignore_resource_conflicts = true,
};
static struct mfd_cell lpc_ich_spi_cell = {
.name = "intel-spi",
.num_resources = ARRAY_SIZE(intel_spi_res),
.resources = intel_spi_res,
.ignore_resource_conflicts = true,
};
/* chipset related info */
enum lpc_chipsets {
LPC_ICH = 0, /* ICH */
@ -216,6 +242,7 @@ enum lpc_chipsets {
LPC_BRASWELL, /* Braswell SoC */
LPC_LEWISBURG, /* Lewisburg */
LPC_9S, /* 9 Series */
LPC_APL, /* Apollo Lake SoC */
};
static struct lpc_ich_info lpc_chipset_info[] = {
@ -494,10 +521,12 @@ static struct lpc_ich_info lpc_chipset_info[] = {
.name = "Lynx Point",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
.spi_type = INTEL_SPI_LPT,
},
[LPC_LPT_LP] = {
.name = "Lynx Point_LP",
.iTCO_version = 2,
.spi_type = INTEL_SPI_LPT,
},
[LPC_WBG] = {
.name = "Wellsburg",
@ -511,6 +540,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_BAYTRAIL] = {
.name = "Bay Trail SoC",
.iTCO_version = 3,
.spi_type = INTEL_SPI_BYT,
},
[LPC_COLETO] = {
.name = "Coleto Creek",
@ -519,10 +549,12 @@ static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_WPT_LP] = {
.name = "Wildcat Point_LP",
.iTCO_version = 2,
.spi_type = INTEL_SPI_LPT,
},
[LPC_BRASWELL] = {
.name = "Braswell SoC",
.iTCO_version = 3,
.spi_type = INTEL_SPI_BYT,
},
[LPC_LEWISBURG] = {
.name = "Lewisburg",
@ -533,6 +565,10 @@ static struct lpc_ich_info lpc_chipset_info[] = {
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_APL] = {
.name = "Apollo Lake SoC",
.spi_type = INTEL_SPI_BXT,
},
};
/*
@ -681,6 +717,7 @@ static const struct pci_device_id lpc_ich_ids[] = {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
{ PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
@ -1056,6 +1093,94 @@ static int lpc_ich_init_wdt(struct pci_dev *dev)
return ret;
}
static int lpc_ich_init_spi(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
struct resource *res = &intel_spi_res[0];
struct intel_spi_boardinfo *info;
u32 spi_base, rcba, bcr;
info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->type = lpc_chipset_info[priv->chipset].spi_type;
switch (info->type) {
case INTEL_SPI_BYT:
pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
if (spi_base & SPIBASE_BYT_EN) {
res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
res->end = res->start + SPIBASE_BYT_SZ - 1;
}
break;
case INTEL_SPI_LPT:
pci_read_config_dword(dev, RCBABASE, &rcba);
if (rcba & 1) {
spi_base = round_down(rcba, SPIBASE_LPT_SZ);
res->start = spi_base + SPIBASE_LPT;
res->end = res->start + SPIBASE_LPT_SZ - 1;
/*
* Try to make the flash chip writeable now by
* setting BCR_WPD. It it fails we tell the driver
* that it can only read the chip.
*/
pci_read_config_dword(dev, BCR, &bcr);
if (!(bcr & BCR_WPD)) {
bcr |= BCR_WPD;
pci_write_config_dword(dev, BCR, bcr);
pci_read_config_dword(dev, BCR, &bcr);
}
info->writeable = !!(bcr & BCR_WPD);
}
break;
case INTEL_SPI_BXT: {
unsigned int p2sb = PCI_DEVFN(13, 0);
unsigned int spi = PCI_DEVFN(13, 2);
struct pci_bus *bus = dev->bus;
/*
* The P2SB is hidden by BIOS and we need to unhide it in
* order to read BAR of the SPI flash device. Once that is
* done we hide it again.
*/
pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
&spi_base);
if (spi_base != ~0) {
res->start = spi_base & 0xfffffff0;
res->end = res->start + SPIBASE_APL_SZ - 1;
pci_bus_read_config_dword(bus, spi, BCR, &bcr);
if (!(bcr & BCR_WPD)) {
bcr |= BCR_WPD;
pci_bus_write_config_dword(bus, spi, BCR, bcr);
pci_bus_read_config_dword(bus, spi, BCR, &bcr);
}
info->writeable = !!(bcr & BCR_WPD);
}
pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
break;
}
default:
return -EINVAL;
}
if (!res->start)
return -ENODEV;
lpc_ich_spi_cell.platform_data = info;
lpc_ich_spi_cell.pdata_size = sizeof(*info);
return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
&lpc_ich_spi_cell, 1, NULL, 0, NULL);
}
static int lpc_ich_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
@ -1099,6 +1224,12 @@ static int lpc_ich_probe(struct pci_dev *dev,
cell_added = true;
}
if (lpc_chipset_info[priv->chipset].spi_type) {
ret = lpc_ich_init_spi(dev);
if (!ret)
cell_added = true;
}
/*
* We only care if at least one or none of the cells registered
* successfully.

20
drivers/mtd/spi-nor/Kconfig
View File

@ -76,4 +76,24 @@ config SPI_NXP_SPIFI
Flash. Enable this option if you have a device with a SPIFI
controller and want to access the Flash as a mtd device.
config SPI_INTEL_SPI
tristate
config SPI_INTEL_SPI_PLATFORM
tristate "Intel PCH/PCU SPI flash platform driver" if EXPERT
depends on X86
select SPI_INTEL_SPI
help
This enables platform support for the Intel PCH/PCU SPI
controller in master mode. This controller is present in modern
Intel hardware and is used to hold BIOS and other persistent
settings. Using this driver it is possible to upgrade BIOS
directly from Linux.
Say N here unless you know what you are doing. Overwriting the
SPI flash may render the system unbootable.
To compile this driver as a module, choose M here: the module
will be called intel-spi-platform.
endif # MTD_SPI_NOR

2
drivers/mtd/spi-nor/Makefile
View File

@ -5,3 +5,5 @@ obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o

57
drivers/mtd/spi-nor/intel-spi-platform.c Normal file
View File

@ -0,0 +1,57 @@
/*
* Intel PCH/PCU SPI flash platform driver.
*
* Copyright (C) 2016, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "intel-spi.h"
static int intel_spi_platform_probe(struct platform_device *pdev)
{
struct intel_spi_boardinfo *info;
struct intel_spi *ispi;
struct resource *mem;
info = dev_get_platdata(&pdev->dev);
if (!info)
return -EINVAL;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ispi = intel_spi_probe(&pdev->dev, mem, info);
if (IS_ERR(ispi))
return PTR_ERR(ispi);
platform_set_drvdata(pdev, ispi);
return 0;
}
static int intel_spi_platform_remove(struct platform_device *pdev)
{
struct intel_spi *ispi = platform_get_drvdata(pdev);
return intel_spi_remove(ispi);
}
static struct platform_driver intel_spi_platform_driver = {
.probe = intel_spi_platform_probe,
.remove = intel_spi_platform_remove,
.driver = {
.name = "intel-spi",
},
};
module_platform_driver(intel_spi_platform_driver);
MODULE_DESCRIPTION("Intel PCH/PCU SPI flash platform driver");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:intel-spi");

777
drivers/mtd/spi-nor/intel-spi.c Normal file
View File

@ -0,0 +1,777 @@
/*
* Intel PCH/PCU SPI flash driver.
*
* Copyright (C) 2016, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/sizes.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/spi-nor.h>
#include <linux/platform_data/intel-spi.h>
#include "intel-spi.h"
/* Offsets are from @ispi->base */
#define BFPREG 0x00
#define HSFSTS_CTL 0x04
#define HSFSTS_CTL_FSMIE BIT(31)
#define HSFSTS_CTL_FDBC_SHIFT 24
#define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
#define HSFSTS_CTL_FCYCLE_SHIFT 17
#define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
/* HW sequencer opcodes */
#define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FGO BIT(16)
#define HSFSTS_CTL_FLOCKDN BIT(15)
#define HSFSTS_CTL_FDV BIT(14)
#define HSFSTS_CTL_SCIP BIT(5)
#define HSFSTS_CTL_AEL BIT(2)
#define HSFSTS_CTL_FCERR BIT(1)
#define HSFSTS_CTL_FDONE BIT(0)
#define FADDR 0x08
#define DLOCK 0x0c
#define FDATA(n) (0x10 + ((n) * 4))
#define FRACC 0x50
#define FREG(n) (0x54 + ((n) * 4))
#define FREG_BASE_MASK 0x3fff
#define FREG_LIMIT_SHIFT 16
#define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
/* Offset is from @ispi->pregs */
#define PR(n) ((n) * 4)
#define PR_WPE BIT(31)
#define PR_LIMIT_SHIFT 16
#define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
#define PR_RPE BIT(15)
#define PR_BASE_MASK 0x3fff
/* Last PR is GPR0 */
#define PR_NUM (5 + 1)
/* Offsets are from @ispi->sregs */
#define SSFSTS_CTL 0x00
#define SSFSTS_CTL_FSMIE BIT(23)
#define SSFSTS_CTL_DS BIT(22)
#define SSFSTS_CTL_DBC_SHIFT 16
#define SSFSTS_CTL_SPOP BIT(11)
#define SSFSTS_CTL_ACS BIT(10)
#define SSFSTS_CTL_SCGO BIT(9)
#define SSFSTS_CTL_COP_SHIFT 12
#define SSFSTS_CTL_FRS BIT(7)
#define SSFSTS_CTL_DOFRS BIT(6)
#define SSFSTS_CTL_AEL BIT(4)
#define SSFSTS_CTL_FCERR BIT(3)
#define SSFSTS_CTL_FDONE BIT(2)
#define SSFSTS_CTL_SCIP BIT(0)
#define PREOP_OPTYPE 0x04
#define OPMENU0 0x08
#define OPMENU1 0x0c
/* CPU specifics */
#define BYT_PR 0x74
#define BYT_SSFSTS_CTL 0x90
#define BYT_BCR 0xfc
#define BYT_BCR_WPD BIT(0)
#define BYT_FREG_NUM 5
#define LPT_PR 0x74
#define LPT_SSFSTS_CTL 0x90
#define LPT_FREG_NUM 5
#define BXT_PR 0x84
#define BXT_SSFSTS_CTL 0xa0
#define BXT_FREG_NUM 12
#define INTEL_SPI_TIMEOUT 5000 /* ms */
#define INTEL_SPI_FIFO_SZ 64
/**
* struct intel_spi - Driver private data
* @dev: Device pointer
* @info: Pointer to board specific info
* @nor: SPI NOR layer structure
* @base: Beginning of MMIO space
* @pregs: Start of protection registers
* @sregs: Start of software sequencer registers
* @nregions: Maximum number of regions
* @writeable: Is the chip writeable
* @swseq: Use SW sequencer in register reads/writes
* @erase_64k: 64k erase supported
* @opcodes: Opcodes which are supported. This are programmed by BIOS
* before it locks down the controller.
* @preopcodes: Preopcodes which are supported.
*/
struct intel_spi {
struct device *dev;
const struct intel_spi_boardinfo *info;
struct spi_nor nor;
void __iomem *base;
void __iomem *pregs;
void __iomem *sregs;
size_t nregions;
bool writeable;
bool swseq;
bool erase_64k;
u8 opcodes[8];
u8 preopcodes[2];
};
static bool writeable;
module_param(writeable, bool, 0);
MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
static void intel_spi_dump_regs(struct intel_spi *ispi)
{
u32 value;
int i;
dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
value = readl(ispi->base + HSFSTS_CTL);
dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
if (value & HSFSTS_CTL_FLOCKDN)
dev_dbg(ispi->dev, "-> Locked\n");
dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
for (i = 0; i < 16; i++)
dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
i, readl(ispi->base + FDATA(i)));
dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
for (i = 0; i < ispi->nregions; i++)
dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
readl(ispi->base + FREG(i)));
for (i = 0; i < PR_NUM; i++)
dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
readl(ispi->pregs + PR(i)));
value = readl(ispi->sregs + SSFSTS_CTL);
dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
readl(ispi->sregs + PREOP_OPTYPE));
dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0));
dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1));
if (ispi->info->type == INTEL_SPI_BYT)
dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
dev_dbg(ispi->dev, "Protected regions:\n");
for (i = 0; i < PR_NUM; i++) {
u32 base, limit;
value = readl(ispi->pregs + PR(i));
if (!(value & (PR_WPE | PR_RPE)))
continue;
limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
base = value & PR_BASE_MASK;
dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
i, base << 12, (limit << 12) | 0xfff,
value & PR_WPE ? 'W' : '.',
value & PR_RPE ? 'R' : '.');
}
dev_dbg(ispi->dev, "Flash regions:\n");
for (i = 0; i < ispi->nregions; i++) {
u32 region, base, limit;
region = readl(ispi->base + FREG(i));
base = region & FREG_BASE_MASK;
limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
if (base >= limit || (i > 0 && limit == 0))
dev_dbg(ispi->dev, " %02d disabled\n", i);
else
dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
i, base << 12, (limit << 12) | 0xfff);
}
dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
ispi->swseq ? 'S' : 'H');
}
/* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
{
size_t bytes;
int i = 0;
if (size > INTEL_SPI_FIFO_SZ)
return -EINVAL;
while (size > 0) {
bytes = min_t(size_t, size, 4);
memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
size -= bytes;
buf += bytes;
i++;
}
return 0;
}
/* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
size_t size)
{
size_t bytes;
int i = 0;
if (size > INTEL_SPI_FIFO_SZ)
return -EINVAL;
while (size > 0) {
bytes = min_t(size_t, size, 4);
memcpy_toio(ispi->base + FDATA(i), buf, bytes);
size -= bytes;
buf += bytes;
i++;
}
return 0;
}
static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
{
u32 val;
return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
!(val & HSFSTS_CTL_SCIP), 0,
INTEL_SPI_TIMEOUT * 1000);
}
static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
{
u32 val;
return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
!(val & SSFSTS_CTL_SCIP), 0,
INTEL_SPI_TIMEOUT * 1000);
}
static int intel_spi_init(struct intel_spi *ispi)
{
u32 opmenu0, opmenu1, val;
int i;
switch (ispi->info->type) {
case INTEL_SPI_BYT:
ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
ispi->pregs = ispi->base + BYT_PR;
ispi->nregions = BYT_FREG_NUM;
if (writeable) {
/* Disable write protection */
val = readl(ispi->base + BYT_BCR);
if (!(val & BYT_BCR_WPD)) {
val |= BYT_BCR_WPD;
writel(val, ispi->base + BYT_BCR);
val = readl(ispi->base + BYT_BCR);
}
ispi->writeable = !!(val & BYT_BCR_WPD);
}
break;
case INTEL_SPI_LPT:
ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
ispi->pregs = ispi->base + LPT_PR;
ispi->nregions = LPT_FREG_NUM;
break;
case INTEL_SPI_BXT:
ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
ispi->pregs = ispi->base + BXT_PR;
ispi->nregions = BXT_FREG_NUM;
ispi->erase_64k = true;
break;
default:
return -EINVAL;
}
/* Disable #SMI generation */
val = readl(ispi->base + HSFSTS_CTL);
val &= ~HSFSTS_CTL_FSMIE;
writel(val, ispi->base + HSFSTS_CTL);
/*
* BIOS programs allowed opcodes and then locks down the register.
* So read back what opcodes it decided to support. That's the set
* we are going to support as well.
*/
opmenu0 = readl(ispi->sregs + OPMENU0);
opmenu1 = readl(ispi->sregs + OPMENU1);
/*
* Some controllers can only do basic operations using hardware
* sequencer. All other operations are supposed to be carried out
* using software sequencer. If we find that BIOS has programmed
* opcodes for the software sequencer we use that over the hardware
* sequencer.
*/
if (opmenu0 && opmenu1) {
for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
ispi->opcodes[i] = opmenu0 >> i * 8;
ispi->opcodes[i + 4] = opmenu1 >> i * 8;
}
val = readl(ispi->sregs + PREOP_OPTYPE);
ispi->preopcodes[0] = val;
ispi->preopcodes[1] = val >> 8;
/* Disable #SMI generation from SW sequencer */
val = readl(ispi->sregs + SSFSTS_CTL);
val &= ~SSFSTS_CTL_FSMIE;
writel(val, ispi->sregs + SSFSTS_CTL);
ispi->swseq = true;
}
intel_spi_dump_regs(ispi);
return 0;
}
static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode)
{
int i;
for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
if (ispi->opcodes[i] == opcode)
return i;
return -EINVAL;
}
static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, u8 *buf,
int len)
{
u32 val, status;
int ret;
val = readl(ispi->base + HSFSTS_CTL);
val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
switch (opcode) {
case SPINOR_OP_RDID:
val |= HSFSTS_CTL_FCYCLE_RDID;
break;
case SPINOR_OP_WRSR:
val |= HSFSTS_CTL_FCYCLE_WRSR;
break;
case SPINOR_OP_RDSR:
val |= HSFSTS_CTL_FCYCLE_RDSR;
break;
default:
return -EINVAL;
}
val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
val |= HSFSTS_CTL_FGO;
writel(val, ispi->base + HSFSTS_CTL);
ret = intel_spi_wait_hw_busy(ispi);
if (ret)
return ret;
status = readl(ispi->base + HSFSTS_CTL);
if (status & HSFSTS_CTL_FCERR)
return -EIO;
else if (status & HSFSTS_CTL_AEL)
return -EACCES;
return 0;
}
static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, u8 *buf,
int len)
{
u32 val, status;
int ret;
ret = intel_spi_opcode_index(ispi, opcode);
if (ret < 0)
return ret;
val = (len << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
val |= ret << SSFSTS_CTL_COP_SHIFT;
val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
val |= SSFSTS_CTL_SCGO;
writel(val, ispi->sregs + SSFSTS_CTL);
ret = intel_spi_wait_sw_busy(ispi);
if (ret)
return ret;
status = readl(ispi->base + SSFSTS_CTL);
if (status & SSFSTS_CTL_FCERR)
return -EIO;
else if (status & SSFSTS_CTL_AEL)
return -EACCES;
return 0;
}
static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
struct intel_spi *ispi = nor->priv;
int ret;
/* Address of the first chip */
writel(0, ispi->base + FADDR);
if (ispi->swseq)
ret = intel_spi_sw_cycle(ispi, opcode, buf, len);
else
ret = intel_spi_hw_cycle(ispi, opcode, buf, len);
if (ret)
return ret;
return intel_spi_read_block(ispi, buf, len);
}
static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
struct intel_spi *ispi = nor->priv;
int ret;
/*
* This is handled with atomic operation and preop code in Intel
* controller so skip it here now.
*/
if (opcode == SPINOR_OP_WREN)
return 0;
writel(0, ispi->base + FADDR);
/* Write the value beforehand */
ret = intel_spi_write_block(ispi, buf, len);
if (ret)
return ret;
if (ispi->swseq)
return intel_spi_sw_cycle(ispi, opcode, buf, len);
return intel_spi_hw_cycle(ispi, opcode, buf, len);
}
static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
u_char *read_buf)
{
struct intel_spi *ispi = nor->priv;
size_t block_size, retlen = 0;
u32 val, status;
ssize_t ret;
switch (nor->read_opcode) {
case SPINOR_OP_READ:
case SPINOR_OP_READ_FAST:
break;
default:
return -EINVAL;
}
while (len > 0) {
block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
writel(from, ispi->base + FADDR);
val = readl(ispi->base + HSFSTS_CTL);
val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
val |= HSFSTS_CTL_FCYCLE_READ;
val |= HSFSTS_CTL_FGO;
writel(val, ispi->base + HSFSTS_CTL);
ret = intel_spi_wait_hw_busy(ispi);
if (ret)
return ret;
status = readl(ispi->base + HSFSTS_CTL);
if (status & HSFSTS_CTL_FCERR)
ret = -EIO;
else if (status & HSFSTS_CTL_AEL)
ret = -EACCES;
if (ret < 0) {
dev_err(ispi->dev, "read error: %llx: %#x\n", from,
status);
return ret;
}
ret = intel_spi_read_block(ispi, read_buf, block_size);
if (ret)
return ret;
len -= block_size;
from += block_size;
retlen += block_size;
read_buf += block_size;
}
return retlen;
}
static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
const u_char *write_buf)
{
struct intel_spi *ispi = nor->priv;
size_t block_size, retlen = 0;
u32 val, status;
ssize_t ret;
while (len > 0) {
block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
writel(to, ispi->base + FADDR);
val = readl(ispi->base + HSFSTS_CTL);
val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
val |= HSFSTS_CTL_FCYCLE_WRITE;
/* Write enable */
if (ispi->preopcodes[1] == SPINOR_OP_WREN)
val |= SSFSTS_CTL_SPOP;
val |= SSFSTS_CTL_ACS;
writel(val, ispi->base + HSFSTS_CTL);
ret = intel_spi_write_block(ispi, write_buf, block_size);
if (ret) {
dev_err(ispi->dev, "failed to write block\n");
return ret;
}
/* Start the write now */
val = readl(ispi->base + HSFSTS_CTL);
writel(val | HSFSTS_CTL_FGO, ispi->base + HSFSTS_CTL);
ret = intel_spi_wait_hw_busy(ispi);
if (ret) {
dev_err(ispi->dev, "timeout\n");
return ret;
}
status = readl(ispi->base + HSFSTS_CTL);
if (status & HSFSTS_CTL_FCERR)
ret = -EIO;
else if (status & HSFSTS_CTL_AEL)
ret = -EACCES;
if (ret < 0) {
dev_err(ispi->dev, "write error: %llx: %#x\n", to,
status);
return ret;
}
len -= block_size;
to += block_size;
retlen += block_size;
write_buf += block_size;
}
return retlen;
}
static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
{
size_t erase_size, len = nor->mtd.erasesize;
struct intel_spi *ispi = nor->priv;
u32 val, status, cmd;
int ret;
/* If the hardware can do 64k erase use that when possible */
if (len >= SZ_64K && ispi->erase_64k) {
cmd = HSFSTS_CTL_FCYCLE_ERASE_64K;
erase_size = SZ_64K;
} else {
cmd = HSFSTS_CTL_FCYCLE_ERASE;
erase_size = SZ_4K;
}
while (len > 0) {
writel(offs, ispi->base + FADDR);
val = readl(ispi->base + HSFSTS_CTL);
val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
val |= cmd;
val |= HSFSTS_CTL_FGO;
writel(val, ispi->base + HSFSTS_CTL);
ret = intel_spi_wait_hw_busy(ispi);
if (ret)
return ret;
status = readl(ispi->base + HSFSTS_CTL);
if (status & HSFSTS_CTL_FCERR)
return -EIO;
else if (status & HSFSTS_CTL_AEL)
return -EACCES;
offs += erase_size;
len -= erase_size;
}
return 0;
}
static bool intel_spi_is_protected(const struct intel_spi *ispi,
unsigned int base, unsigned int limit)
{
int i;
for (i = 0; i < PR_NUM; i++) {
u32 pr_base, pr_limit, pr_value;
pr_value = readl(ispi->pregs + PR(i));
if (!(pr_value & (PR_WPE | PR_RPE)))
continue;
pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
pr_base = pr_value & PR_BASE_MASK;
if (pr_base >= base && pr_limit <= limit)
return true;
}
return false;
}
/*
* There will be a single partition holding all enabled flash regions. We
* call this "BIOS".
*/
static void intel_spi_fill_partition(struct intel_spi *ispi,
struct mtd_partition *part)
{
u64 end;
int i;
memset(part, 0, sizeof(*part));
/* Start from the mandatory descriptor region */
part->size = 4096;
part->name = "BIOS";
/*
* Now try to find where this partition ends based on the flash
* region registers.
*/
for (i = 1; i < ispi->nregions; i++) {
u32 region, base, limit;
region = readl(ispi->base + FREG(i));
base = region & FREG_BASE_MASK;
limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
if (base >= limit || limit == 0)
continue;
/*
* If any of the regions have protection bits set, make the
* whole partition read-only to be on the safe side.
*/
if (intel_spi_is_protected(ispi, base, limit))
ispi->writeable = 0;
end = (limit << 12) + 4096;
if (end > part->size)
part->size = end;
}
}
struct intel_spi *intel_spi_probe(struct device *dev,
struct resource *mem, const struct intel_spi_boardinfo *info)
{
struct mtd_partition part;
struct intel_spi *ispi;
int ret;
if (!info || !mem)
return ERR_PTR(-EINVAL);
ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
if (!ispi)
return ERR_PTR(-ENOMEM);
ispi->base = devm_ioremap_resource(dev, mem);
if (IS_ERR(ispi->base))
return ispi->base;
ispi->dev = dev;
ispi->info = info;
ispi->writeable = info->writeable;
ret = intel_spi_init(ispi);
if (ret)
return ERR_PTR(ret);
ispi->nor.dev = ispi->dev;
ispi->nor.priv = ispi;
ispi->nor.read_reg = intel_spi_read_reg;
ispi->nor.write_reg = intel_spi_write_reg;
ispi->nor.read = intel_spi_read;
ispi->nor.write = intel_spi_write;
ispi->nor.erase = intel_spi_erase;
ret = spi_nor_scan(&ispi->nor, NULL, SPI_NOR_NORMAL);
if (ret) {
dev_info(dev, "failed to locate the chip\n");
return ERR_PTR(ret);
}
intel_spi_fill_partition(ispi, &part);
/* Prevent writes if not explicitly enabled */
if (!ispi->writeable || !writeable)
ispi->nor.mtd.flags &= ~MTD_WRITEABLE;
ret = mtd_device_parse_register(&ispi->nor.mtd, NULL, NULL, &part, 1);
if (ret)
return ERR_PTR(ret);
return ispi;
}
EXPORT_SYMBOL_GPL(intel_spi_probe);
int intel_spi_remove(struct intel_spi *ispi)
{
return mtd_device_unregister(&ispi->nor.mtd);
}
EXPORT_SYMBOL_GPL(intel_spi_remove);
MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_LICENSE("GPL v2");

24
drivers/mtd/spi-nor/intel-spi.h Normal file
View File

@ -0,0 +1,24 @@
/*
* Intel PCH/PCU SPI flash driver.
*
* Copyright (C) 2016, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef INTEL_SPI_H
#define INTEL_SPI_H
#include <linux/platform_data/intel-spi.h>
struct intel_spi;
struct resource;
struct intel_spi *intel_spi_probe(struct device *dev,
struct resource *mem, const struct intel_spi_boardinfo *info);
int intel_spi_remove(struct intel_spi *ispi);
#endif /* INTEL_SPI_H */

138
drivers/power/supply/axp288_charger.c
View File

@ -143,7 +143,6 @@ enum {
struct axp288_chrg_info {
struct platform_device *pdev;
struct axp20x_chrg_pdata *pdata;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irqc;
int irq[CHRG_INTR_END];
@ -701,110 +700,112 @@ static int axp288_charger_handle_otg_evt(struct notifier_block *nb,
return NOTIFY_OK;
}
static void charger_init_hw_regs(struct axp288_chrg_info *info)
static int charger_init_hw_regs(struct axp288_chrg_info *info)
{
int ret, cc, cv;
unsigned int val;
/* Program temperature thresholds */
ret = regmap_write(info->regmap, AXP20X_V_LTF_CHRG, CHRG_VLTFC_0C);
if (ret < 0)
dev_warn(&info->pdev->dev, "register(%x) write error(%d)\n",
if (ret < 0) {
dev_err(&info->pdev->dev, "register(%x) write error(%d)\n",
AXP20X_V_LTF_CHRG, ret);
return ret;
}
ret = regmap_write(info->regmap, AXP20X_V_HTF_CHRG, CHRG_VHTFC_45C);
if (ret < 0)
dev_warn(&info->pdev->dev, "register(%x) write error(%d)\n",
if (ret < 0) {
dev_err(&info->pdev->dev, "register(%x) write error(%d)\n",
AXP20X_V_HTF_CHRG, ret);
return ret;
}
/* Do not turn-off charger o/p after charge cycle ends */
ret = regmap_update_bits(info->regmap,
AXP20X_CHRG_CTRL2,
CNTL2_CHG_OUT_TURNON, 1);
if (ret < 0)
dev_warn(&info->pdev->dev, "register(%x) write error(%d)\n",
if (ret < 0) {
dev_err(&info->pdev->dev, "register(%x) write error(%d)\n",
AXP20X_CHRG_CTRL2, ret);
return ret;
}
/* Enable interrupts */
ret = regmap_update_bits(info->regmap,
AXP20X_IRQ2_EN,
BAT_IRQ_CFG_BAT_MASK, 1);
if (ret < 0)
dev_warn(&info->pdev->dev, "register(%x) write error(%d)\n",
if (ret < 0) {
dev_err(&info->pdev->dev, "register(%x) write error(%d)\n",
AXP20X_IRQ2_EN, ret);
return ret;
}
ret = regmap_update_bits(info->regmap, AXP20X_IRQ3_EN,
TEMP_IRQ_CFG_MASK, 1);
if (ret < 0)
dev_warn(&info->pdev->dev, "register(%x) write error(%d)\n",
if (ret < 0) {
dev_err(&info->pdev->dev, "register(%x) write error(%d)\n",
AXP20X_IRQ3_EN, ret);
return ret;
}
/* Setup ending condition for charging to be 10% of I(chrg) */
ret = regmap_update_bits(info->regmap,
AXP20X_CHRG_CTRL1,
CHRG_CCCV_ITERM_20P, 0);
if (ret < 0)
dev_warn(&info->pdev->dev, "register(%x) write error(%d)\n",
if (ret < 0) {
dev_err(&info->pdev->dev, "register(%x) write error(%d)\n",
AXP20X_CHRG_CTRL1, ret);
return ret;
}
/* Disable OCV-SOC curve calibration */
ret = regmap_update_bits(info->regmap,
AXP20X_CC_CTRL,
FG_CNTL_OCV_ADJ_EN, 0);
if (ret < 0)
dev_warn(&info->pdev->dev, "register(%x) write error(%d)\n",
if (ret < 0) {
dev_err(&info->pdev->dev, "register(%x) write error(%d)\n",
AXP20X_CC_CTRL, ret);
/* Init charging current and voltage */
info->max_cc = info->pdata->max_cc;
info->max_cv = info->pdata->max_cv;
return ret;
}
/* Read current charge voltage and current limit */
ret = regmap_read(info->regmap, AXP20X_CHRG_CTRL1, &val);
if (ret < 0) {
/* Assume default if cannot read */
info->cc = info->pdata->def_cc;
info->cv = info->pdata->def_cv;
} else {
/* Determine charge voltage */
cv = (val & CHRG_CCCV_CV_MASK) >> CHRG_CCCV_CV_BIT_POS;
switch (cv) {
case CHRG_CCCV_CV_4100MV:
info->cv = CV_4100MV;
break;
case CHRG_CCCV_CV_4150MV:
info->cv = CV_4150MV;
break;
case CHRG_CCCV_CV_4200MV:
info->cv = CV_4200MV;
break;
case CHRG_CCCV_CV_4350MV:
info->cv = CV_4350MV;
break;
default:
info->cv = INT_MAX;
break;
}
/* Determine charge current limit */
cc = (ret & CHRG_CCCV_CC_MASK) >> CHRG_CCCV_CC_BIT_POS;
cc = (cc * CHRG_CCCV_CC_LSB_RES) + CHRG_CCCV_CC_OFFSET;
info->cc = cc;
/* Program default charging voltage and current */
cc = min(info->pdata->def_cc, info->max_cc);
cv = min(info->pdata->def_cv, info->max_cv);
ret = axp288_charger_set_cc(info, cc);
if (ret < 0)
dev_warn(&info->pdev->dev,
"error(%d) in setting CC\n", ret);
ret = axp288_charger_set_cv(info, cv);
if (ret < 0)
dev_warn(&info->pdev->dev,
"error(%d) in setting CV\n", ret);
dev_err(&info->pdev->dev, "register(%x) read error(%d)\n",
AXP20X_CHRG_CTRL1, ret);
return ret;
}
/* Determine charge voltage */
cv = (val & CHRG_CCCV_CV_MASK) >> CHRG_CCCV_CV_BIT_POS;
switch (cv) {
case CHRG_CCCV_CV_4100MV:
info->cv = CV_4100MV;
break;
case CHRG_CCCV_CV_4150MV:
info->cv = CV_4150MV;
break;
case CHRG_CCCV_CV_4200MV:
info->cv = CV_4200MV;
break;
case CHRG_CCCV_CV_4350MV:
info->cv = CV_4350MV;
break;
}
/* Determine charge current limit */
cc = (ret & CHRG_CCCV_CC_MASK) >> CHRG_CCCV_CC_BIT_POS;
cc = (cc * CHRG_CCCV_CC_LSB_RES) + CHRG_CCCV_CC_OFFSET;
info->cc = cc;
/*
* Do not allow the user to configure higher settings then those
* set by the firmware
*/
info->max_cv = info->cv;
info->max_cc = info->cc;
return 0;
}
static int axp288_charger_probe(struct platform_device *pdev)
@ -821,15 +822,6 @@ static int axp288_charger_probe(struct platform_device *pdev)
info->pdev = pdev;
info->regmap = axp20x->regmap;
info->regmap_irqc = axp20x->regmap_irqc;
info->pdata = pdev->dev.platform_data;
if (!info->pdata) {
/* Try ACPI provided pdata via device properties */
if (!device_property_present(&pdev->dev,
"axp288_charger_data\n"))
dev_err(&pdev->dev, "failed to get platform data\n");
return -ENODEV;
}
info->cable.edev = extcon_get_extcon_dev(AXP288_EXTCON_DEV_NAME);
if (info->cable.edev == NULL) {
@ -916,7 +908,9 @@ static int axp288_charger_probe(struct platform_device *pdev)
}
}
charger_init_hw_regs(info);
ret = charger_init_hw_regs(info);
if (ret)
goto intr_reg_failed;
return 0;

405
drivers/power/supply/axp288_fuel_gauge.c
View File

@ -49,11 +49,6 @@
#define CHRG_CCCV_CV_4350MV 0x3 /* 4.35V */
#define CHRG_CCCV_CHG_EN (1 << 7)
#define CV_4100 4100 /* 4100mV */
#define CV_4150 4150 /* 4150mV */
#define CV_4200 4200 /* 4200mV */
#define CV_4350 4350 /* 4350mV */
#define TEMP_IRQ_CFG_QWBTU (1 << 0)
#define TEMP_IRQ_CFG_WBTU (1 << 1)
#define TEMP_IRQ_CFG_QWBTO (1 << 2)
@ -104,9 +99,7 @@
/* 1.1mV per LSB expressed in uV */
#define VOLTAGE_FROM_ADC(a) ((a * 11) / 10)
/* properties converted to tenths of degrees, uV, uA, uW */
#define PROP_TEMP(a) ((a) * 10)
#define UNPROP_TEMP(a) ((a) / 10)
/* properties converted to uV, uA */
#define PROP_VOLT(a) ((a) * 1000)
#define PROP_CURR(a) ((a) * 1000)
@ -122,13 +115,13 @@ enum {
struct axp288_fg_info {
struct platform_device *pdev;
struct axp20x_fg_pdata *pdata;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irqc;
int irq[AXP288_FG_INTR_NUM];
struct power_supply *bat;
struct mutex lock;
int status;
int max_volt;
struct delayed_work status_monitor;
struct dentry *debug_file;
};
@ -138,22 +131,14 @@ static enum power_supply_property fuel_gauge_props[] = {
POWER_SUPPLY_PROP_PRESENT,
POWER_SUPPLY_PROP_HEALTH,
POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
POWER_SUPPLY_PROP_VOLTAGE_NOW,
POWER_SUPPLY_PROP_VOLTAGE_OCV,
POWER_SUPPLY_PROP_CURRENT_NOW,
POWER_SUPPLY_PROP_CAPACITY,
POWER_SUPPLY_PROP_CAPACITY_ALERT_MIN,
POWER_SUPPLY_PROP_TEMP,
POWER_SUPPLY_PROP_TEMP_MAX,
POWER_SUPPLY_PROP_TEMP_MIN,
POWER_SUPPLY_PROP_TEMP_ALERT_MIN,
POWER_SUPPLY_PROP_TEMP_ALERT_MAX,
POWER_SUPPLY_PROP_TECHNOLOGY,
POWER_SUPPLY_PROP_CHARGE_FULL,
POWER_SUPPLY_PROP_CHARGE_NOW,
POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
POWER_SUPPLY_PROP_MODEL_NAME,
};
static int fuel_gauge_reg_readb(struct axp288_fg_info *info, int reg)
@ -417,102 +402,6 @@ static int fuel_gauge_get_current(struct axp288_fg_info *info, int *cur)
return ret;
}
static int temp_to_adc(struct axp288_fg_info *info, int tval)
{
int rntc = 0, i, ret, adc_val;
int rmin, rmax, tmin, tmax;
int tcsz = info->pdata->tcsz;
/* get the Rntc resitance value for this temp */
if (tval > info->pdata->thermistor_curve[0][1]) {
rntc = info->pdata->thermistor_curve[0][0];
} else if (tval <= info->pdata->thermistor_curve[tcsz-1][1]) {
rntc = info->pdata->thermistor_curve[tcsz-1][0];
} else {
for (i = 1; i < tcsz; i++) {
if (tval > info->pdata->thermistor_curve[i][1]) {
rmin = info->pdata->thermistor_curve[i-1][0];
rmax = info->pdata->thermistor_curve[i][0];
tmin = info->pdata->thermistor_curve[i-1][1];
tmax = info->pdata->thermistor_curve[i][1];
rntc = rmin + ((rmax - rmin) *
(tval - tmin) / (tmax - tmin));
break;
}
}
}
/* we need the current to calculate the proper adc voltage */
ret = fuel_gauge_reg_readb(info, AXP20X_ADC_RATE);
if (ret < 0) {
dev_err(&info->pdev->dev, "%s:read err:%d\n", __func__, ret);
ret = 0x30;
}
/*
* temperature is proportional to NTS thermistor resistance
* ADC_RATE[5-4] determines current, 00=20uA,01=40uA,10=60uA,11=80uA
* [12-bit ADC VAL] = R_NTC(Ω) * current / 800
*/
adc_val = rntc * (20 + (20 * ((ret >> 4) & 0x3))) / 800;
return adc_val;
}
static int adc_to_temp(struct axp288_fg_info *info, int adc_val)
{
int ret, r, i, tval = 0;
int rmin, rmax, tmin, tmax;
int tcsz = info->pdata->tcsz;
ret = fuel_gauge_reg_readb(info, AXP20X_ADC_RATE);
if (ret < 0) {
dev_err(&info->pdev->dev, "%s:read err:%d\n", __func__, ret);
ret = 0x30;
}
/*
* temperature is proportional to NTS thermistor resistance
* ADC_RATE[5-4] determines current, 00=20uA,01=40uA,10=60uA,11=80uA
* R_NTC(Ω) = [12-bit ADC VAL] * 800 / current
*/
r = adc_val * 800 / (20 + (20 * ((ret >> 4) & 0x3)));
if (r < info->pdata->thermistor_curve[0][0]) {
tval = info->pdata->thermistor_curve[0][1];
} else if (r >= info->pdata->thermistor_curve[tcsz-1][0]) {
tval = info->pdata->thermistor_curve[tcsz-1][1];
} else {
for (i = 1; i < tcsz; i++) {
if (r < info->pdata->thermistor_curve[i][0]) {
rmin = info->pdata->thermistor_curve[i-1][0];
rmax = info->pdata->thermistor_curve[i][0];
tmin = info->pdata->thermistor_curve[i-1][1];
tmax = info->pdata->thermistor_curve[i][1];
tval = tmin + ((tmax - tmin) *
(r - rmin) / (rmax - rmin));
break;
}
}
}
return tval;
}
static int fuel_gauge_get_btemp(struct axp288_fg_info *info, int *btemp)
{
int ret, raw_val = 0;
ret = pmic_read_adc_val("axp288-batt-temp", &raw_val, info);
if (ret < 0)
goto temp_read_fail;
*btemp = adc_to_temp(info, raw_val);
temp_read_fail:
return ret;
}
static int fuel_gauge_get_vocv(struct axp288_fg_info *info, int *vocv)
{
int ret, value;
@ -535,25 +424,14 @@ static int fuel_gauge_get_vocv(struct axp288_fg_info *info, int *vocv)
static int fuel_gauge_battery_health(struct axp288_fg_info *info)
{
int temp, vocv;
int ret, health = POWER_SUPPLY_HEALTH_UNKNOWN;
ret = fuel_gauge_get_btemp(info, &temp);
if (ret < 0)
goto health_read_fail;
int ret, vocv, health = POWER_SUPPLY_HEALTH_UNKNOWN;
ret = fuel_gauge_get_vocv(info, &vocv);
if (ret < 0)
goto health_read_fail;
if (vocv > info->pdata->max_volt)
if (vocv > info->max_volt)
health = POWER_SUPPLY_HEALTH_OVERVOLTAGE;
else if (temp > info->pdata->max_temp)
health = POWER_SUPPLY_HEALTH_OVERHEAT;
else if (temp < info->pdata->min_temp)
health = POWER_SUPPLY_HEALTH_COLD;
else if (vocv < info->pdata->min_volt)
health = POWER_SUPPLY_HEALTH_DEAD;
else
health = POWER_SUPPLY_HEALTH_GOOD;
@ -561,28 +439,6 @@ static int fuel_gauge_battery_health(struct axp288_fg_info *info)
return health;
}
static int fuel_gauge_set_high_btemp_alert(struct axp288_fg_info *info)
{
int ret, adc_val;
/* program temperature threshold as 1/16 ADC value */
adc_val = temp_to_adc(info, info->pdata->max_temp);
ret = fuel_gauge_reg_writeb(info, AXP20X_V_HTF_DISCHRG, adc_val >> 4);
return ret;
}
static int fuel_gauge_set_low_btemp_alert(struct axp288_fg_info *info)
{
int ret, adc_val;
/* program temperature threshold as 1/16 ADC value */
adc_val = temp_to_adc(info, info->pdata->min_temp);
ret = fuel_gauge_reg_writeb(info, AXP20X_V_LTF_DISCHRG, adc_val >> 4);
return ret;
}
static int fuel_gauge_get_property(struct power_supply *ps,
enum power_supply_property prop,
union power_supply_propval *val)
@ -643,20 +499,6 @@ static int fuel_gauge_get_property(struct power_supply *ps,
goto fuel_gauge_read_err;
val->intval = (ret & 0x0f);
break;
case POWER_SUPPLY_PROP_TEMP:
ret = fuel_gauge_get_btemp(info, &value);
if (ret < 0)
goto fuel_gauge_read_err;
val->intval = PROP_TEMP(value);
break;
case POWER_SUPPLY_PROP_TEMP_MAX:
case POWER_SUPPLY_PROP_TEMP_ALERT_MAX:
val->intval = PROP_TEMP(info->pdata->max_temp);
break;
case POWER_SUPPLY_PROP_TEMP_MIN:
case POWER_SUPPLY_PROP_TEMP_ALERT_MIN:
val->intval = PROP_TEMP(info->pdata->min_temp);
break;
case POWER_SUPPLY_PROP_TECHNOLOGY:
val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
break;
@ -684,17 +526,8 @@ static int fuel_gauge_get_property(struct power_supply *ps,
value |= (ret & FG_DES_CAP0_VAL_MASK);
val->intval = value * FG_DES_CAP_RES_LSB;
break;
case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
val->intval = PROP_CURR(info->pdata->design_cap);
break;
case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
val->intval = PROP_VOLT(info->pdata->max_volt);
break;
case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
val->intval = PROP_VOLT(info->pdata->min_volt);
break;
case POWER_SUPPLY_PROP_MODEL_NAME:
val->strval = info->pdata->battid;
val->intval = PROP_VOLT(info->max_volt);
break;
default:
mutex_unlock(&info->lock);
@ -718,35 +551,6 @@ static int fuel_gauge_set_property(struct power_supply *ps,
mutex_lock(&info->lock);
switch (prop) {
case POWER_SUPPLY_PROP_STATUS:
info->status = val->intval;
break;
case POWER_SUPPLY_PROP_TEMP_MIN:
case POWER_SUPPLY_PROP_TEMP_ALERT_MIN:
if ((val->intval < PD_DEF_MIN_TEMP) ||
(val->intval > PD_DEF_MAX_TEMP)) {
ret = -EINVAL;
break;
}
info->pdata->min_temp = UNPROP_TEMP(val->intval);
ret = fuel_gauge_set_low_btemp_alert(info);
if (ret < 0)
dev_err(&info->pdev->dev,
"temp alert min set fail:%d\n", ret);
break;
case POWER_SUPPLY_PROP_TEMP_MAX:
case POWER_SUPPLY_PROP_TEMP_ALERT_MAX:
if ((val->intval < PD_DEF_MIN_TEMP) ||
(val->intval > PD_DEF_MAX_TEMP)) {
ret = -EINVAL;
break;
}
info->pdata->max_temp = UNPROP_TEMP(val->intval);
ret = fuel_gauge_set_high_btemp_alert(info);
if (ret < 0)
dev_err(&info->pdev->dev,
"temp alert max set fail:%d\n", ret);
break;
case POWER_SUPPLY_PROP_CAPACITY_ALERT_MIN:
if ((val->intval < 0) || (val->intval > 15)) {
ret = -EINVAL;
@ -774,11 +578,6 @@ static int fuel_gauge_property_is_writeable(struct power_supply *psy,
int ret;
switch (psp) {
case POWER_SUPPLY_PROP_STATUS:
case POWER_SUPPLY_PROP_TEMP_MIN:
case POWER_SUPPLY_PROP_TEMP_ALERT_MIN:
case POWER_SUPPLY_PROP_TEMP_MAX:
case POWER_SUPPLY_PROP_TEMP_ALERT_MAX:
case POWER_SUPPLY_PROP_CAPACITY_ALERT_MIN:
ret = 1;
break;
@ -863,158 +662,6 @@ static const struct power_supply_desc fuel_gauge_desc = {
.external_power_changed = fuel_gauge_external_power_changed,
};
static int fuel_gauge_set_lowbatt_thresholds(struct axp288_fg_info *info)
{
int ret;
u8 reg_val;
ret = fuel_gauge_reg_readb(info, AXP20X_FG_RES);
if (ret < 0) {
dev_err(&info->pdev->dev, "%s:read err:%d\n", __func__, ret);
return ret;
}
ret = (ret & FG_REP_CAP_VAL_MASK);
if (ret > FG_LOW_CAP_WARN_THR)
reg_val = FG_LOW_CAP_WARN_THR;
else if (ret > FG_LOW_CAP_CRIT_THR)
reg_val = FG_LOW_CAP_CRIT_THR;
else
reg_val = FG_LOW_CAP_SHDN_THR;
reg_val |= FG_LOW_CAP_THR1_VAL;
ret = fuel_gauge_reg_writeb(info, AXP288_FG_LOW_CAP_REG, reg_val);
if (ret < 0)
dev_err(&info->pdev->dev, "%s:write err:%d\n", __func__, ret);
return ret;
}
static int fuel_gauge_program_vbatt_full(struct axp288_fg_info *info)
{
int ret;
u8 val;
ret = fuel_gauge_reg_readb(info, AXP20X_CHRG_CTRL1);
if (ret < 0)
goto fg_prog_ocv_fail;
else
val = (ret & ~CHRG_CCCV_CV_MASK);
switch (info->pdata->max_volt) {
case CV_4100:
val |= (CHRG_CCCV_CV_4100MV << CHRG_CCCV_CV_BIT_POS);
break;
case CV_4150:
val |= (CHRG_CCCV_CV_4150MV << CHRG_CCCV_CV_BIT_POS);
break;
case CV_4200:
val |= (CHRG_CCCV_CV_4200MV << CHRG_CCCV_CV_BIT_POS);
break;
case CV_4350:
val |= (CHRG_CCCV_CV_4350MV << CHRG_CCCV_CV_BIT_POS);
break;
default:
val |= (CHRG_CCCV_CV_4200MV << CHRG_CCCV_CV_BIT_POS);
break;
}
ret = fuel_gauge_reg_writeb(info, AXP20X_CHRG_CTRL1, val);
fg_prog_ocv_fail:
return ret;
}
static int fuel_gauge_program_design_cap(struct axp288_fg_info *info)
{
int ret;
ret = fuel_gauge_reg_writeb(info,
AXP288_FG_DES_CAP1_REG, info->pdata->cap1);
if (ret < 0)
goto fg_prog_descap_fail;
ret = fuel_gauge_reg_writeb(info,
AXP288_FG_DES_CAP0_REG, info->pdata->cap0);
fg_prog_descap_fail:
return ret;
}
static int fuel_gauge_program_ocv_curve(struct axp288_fg_info *info)
{
int ret = 0, i;
for (i = 0; i < OCV_CURVE_SIZE; i++) {
ret = fuel_gauge_reg_writeb(info,
AXP288_FG_OCV_CURVE_REG + i, info->pdata->ocv_curve[i]);
if (ret < 0)
goto fg_prog_ocv_fail;
}
fg_prog_ocv_fail:
return ret;
}
static int fuel_gauge_program_rdc_vals(struct axp288_fg_info *info)
{
int ret;
ret = fuel_gauge_reg_writeb(info,
AXP288_FG_RDC1_REG, info->pdata->rdc1);
if (ret < 0)
goto fg_prog_ocv_fail;
ret = fuel_gauge_reg_writeb(info,
AXP288_FG_RDC0_REG, info->pdata->rdc0);
fg_prog_ocv_fail:
return ret;
}
static void fuel_gauge_init_config_regs(struct axp288_fg_info *info)
{
int ret;
/*
* check if the config data is already
* programmed and if so just return.
*/
ret = fuel_gauge_reg_readb(info, AXP288_FG_DES_CAP1_REG);
if (ret < 0) {
dev_warn(&info->pdev->dev, "CAP1 reg read err!!\n");
} else if (!(ret & FG_DES_CAP1_VALID)) {
dev_info(&info->pdev->dev, "FG data needs to be initialized\n");
} else {
dev_info(&info->pdev->dev, "FG data is already initialized\n");
return;
}
ret = fuel_gauge_program_vbatt_full(info);
if (ret < 0)
dev_err(&info->pdev->dev, "set vbatt full fail:%d\n", ret);
ret = fuel_gauge_program_design_cap(info);
if (ret < 0)
dev_err(&info->pdev->dev, "set design cap fail:%d\n", ret);
ret = fuel_gauge_program_rdc_vals(info);
if (ret < 0)
dev_err(&info->pdev->dev, "set rdc fail:%d\n", ret);
ret = fuel_gauge_program_ocv_curve(info);
if (ret < 0)
dev_err(&info->pdev->dev, "set ocv curve fail:%d\n", ret);
ret = fuel_gauge_set_lowbatt_thresholds(info);
if (ret < 0)
dev_err(&info->pdev->dev, "lowbatt thr set fail:%d\n", ret);
ret = fuel_gauge_reg_writeb(info, AXP20X_CC_CTRL, 0xef);
if (ret < 0)
dev_err(&info->pdev->dev, "gauge cntl set fail:%d\n", ret);
}
static void fuel_gauge_init_irq(struct axp288_fg_info *info)
{
int ret, i, pirq;
@ -1054,17 +701,8 @@ static void fuel_gauge_init_irq(struct axp288_fg_info *info)
static void fuel_gauge_init_hw_regs(struct axp288_fg_info *info)
{
int ret;
unsigned int val;
ret = fuel_gauge_set_high_btemp_alert(info);
if (ret < 0)
dev_err(&info->pdev->dev, "high batt temp set fail:%d\n", ret);
ret = fuel_gauge_set_low_btemp_alert(info);
if (ret < 0)
dev_err(&info->pdev->dev, "low batt temp set fail:%d\n", ret);
/* enable interrupts */
val = fuel_gauge_reg_readb(info, AXP20X_IRQ3_EN);
val |= TEMP_IRQ_CFG_MASK;
@ -1090,15 +728,39 @@ static int axp288_fuel_gauge_probe(struct platform_device *pdev)
info->regmap = axp20x->regmap;
info->regmap_irqc = axp20x->regmap_irqc;
info->status = POWER_SUPPLY_STATUS_UNKNOWN;
info->pdata = pdev->dev.platform_data;
if (!info->pdata)
return -ENODEV;
platform_set_drvdata(pdev, info);
mutex_init(&info->lock);
INIT_DELAYED_WORK(&info->status_monitor, fuel_gauge_status_monitor);
ret = fuel_gauge_reg_readb(info, AXP288_FG_DES_CAP1_REG);
if (ret < 0)
return ret;
if (!(ret & FG_DES_CAP1_VALID)) {
dev_err(&pdev->dev, "axp288 not configured by firmware\n");
return -ENODEV;
}
ret = fuel_gauge_reg_readb(info, AXP20X_CHRG_CTRL1);
if (ret < 0)
return ret;
switch ((ret & CHRG_CCCV_CV_MASK) >> CHRG_CCCV_CV_BIT_POS) {
case CHRG_CCCV_CV_4100MV:
info->max_volt = 4100;
break;
case CHRG_CCCV_CV_4150MV:
info->max_volt = 4150;
break;
case CHRG_CCCV_CV_4200MV:
info->max_volt = 4200;
break;
case CHRG_CCCV_CV_4350MV:
info->max_volt = 4350;
break;
}
psy_cfg.drv_data = info;
info->bat = power_supply_register(&pdev->dev, &fuel_gauge_desc, &psy_cfg);
if (IS_ERR(info->bat)) {
@ -1108,12 +770,11 @@ static int axp288_fuel_gauge_probe(struct platform_device *pdev)
}
fuel_gauge_create_debugfs(info);
fuel_gauge_init_config_regs(info);
fuel_gauge_init_irq(info);
fuel_gauge_init_hw_regs(info);
schedule_delayed_work(&info->status_monitor, STATUS_MON_DELAY_JIFFIES);
return ret;
return 0;
}
static const struct platform_device_id axp288_fg_id_table[] = {

29
include/linux/mfd/axp20x.h
View File

@ -532,35 +532,6 @@ struct axp20x_dev {
const struct regmap_irq_chip *regmap_irq_chip;
};
#define BATTID_LEN 64
#define OCV_CURVE_SIZE 32
#define MAX_THERM_CURVE_SIZE 25
#define PD_DEF_MIN_TEMP 0
#define PD_DEF_MAX_TEMP 55
struct axp20x_fg_pdata {
char battid[BATTID_LEN + 1];
int design_cap;
int min_volt;
int max_volt;
int max_temp;
int min_temp;
int cap1;
int cap0;
int rdc1;
int rdc0;
int ocv_curve[OCV_CURVE_SIZE];
int tcsz;
int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
};
struct axp20x_chrg_pdata {
int max_cc;
int max_cv;
int def_cc;
int def_cv;
};
struct axp288_extcon_pdata {
/* GPIO pin control to switch D+/D- lines b/w PMIC and SOC */
struct gpio_desc *gpio_mux_cntl;

74
include/linux/mfd/cros_ec_commands.h
View File

@ -1839,18 +1839,69 @@ struct ec_response_tmp006_get_raw {
*
* Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
* expected response size.
*
* NOTE: This has been superseded by EC_CMD_MKBP_GET_NEXT_EVENT. If you wish
* to obtain the instantaneous state, use EC_CMD_MKBP_INFO with the type
* EC_MKBP_INFO_CURRENT and event EC_MKBP_EVENT_KEY_MATRIX.
*/
#define EC_CMD_MKBP_STATE 0x60
/* Provide information about the matrix : number of rows and columns */
/*
* Provide information about various MKBP things. See enum ec_mkbp_info_type.
*/
#define EC_CMD_MKBP_INFO 0x61
struct ec_response_mkbp_info {
uint32_t rows;
uint32_t cols;
uint8_t switches;
/* Formerly "switches", which was 0. */
uint8_t reserved;
} __packed;
struct ec_params_mkbp_info {
uint8_t info_type;
uint8_t event_type;
} __packed;
enum ec_mkbp_info_type {
/*
* Info about the keyboard matrix: number of rows and columns.
*
* Returns struct ec_response_mkbp_info.
*/
EC_MKBP_INFO_KBD = 0,
/*
* For buttons and switches, info about which specifically are
* supported. event_type must be set to one of the values in enum
* ec_mkbp_event.
*
* For EC_MKBP_EVENT_BUTTON and EC_MKBP_EVENT_SWITCH, returns a 4 byte
* bitmask indicating which buttons or switches are present. See the
* bit inidices below.
*/
EC_MKBP_INFO_SUPPORTED = 1,
/*
* Instantaneous state of buttons and switches.
*
* event_type must be set to one of the values in enum ec_mkbp_event.
*
* For EC_MKBP_EVENT_KEY_MATRIX, returns uint8_t key_matrix[13]
* indicating the current state of the keyboard matrix.
*
* For EC_MKBP_EVENT_HOST_EVENT, return uint32_t host_event, the raw
* event state.
*
* For EC_MKBP_EVENT_BUTTON, returns uint32_t buttons, indicating the
* state of supported buttons.
*
* For EC_MKBP_EVENT_SWITCH, returns uint32_t switches, indicating the
* state of supported switches.
*/
EC_MKBP_INFO_CURRENT = 2,
};
/* Simulate key press */
#define EC_CMD_MKBP_SIMULATE_KEY 0x62
@ -1983,6 +2034,12 @@ enum ec_mkbp_event {
/* New Sensor FIFO data. The event data is fifo_info structure. */
EC_MKBP_EVENT_SENSOR_FIFO = 2,
/* The state of the non-matrixed buttons have changed. */
EC_MKBP_EVENT_BUTTON = 3,
/* The state of the switches have changed. */
EC_MKBP_EVENT_SWITCH = 4,
/* Number of MKBP events */
EC_MKBP_EVENT_COUNT,
};
@ -1992,6 +2049,9 @@ union ec_response_get_next_data {
/* Unaligned */
uint32_t host_event;
uint32_t buttons;
uint32_t switches;
} __packed;
struct ec_response_get_next_event {
@ -2000,6 +2060,16 @@ struct ec_response_get_next_event {
union ec_response_get_next_data data;
} __packed;
/* Bit indices for buttons and switches.*/
/* Buttons */
#define EC_MKBP_POWER_BUTTON 0
#define EC_MKBP_VOL_UP 1
#define EC_MKBP_VOL_DOWN 2
/* Switches */
#define EC_MKBP_LID_OPEN 0
#define EC_MKBP_TABLET_MODE 1
/*****************************************************************************/
/* Temperature sensor commands */

3
include/linux/mfd/lpc_ich.h
View File

@ -20,6 +20,8 @@
#ifndef LPC_ICH_H
#define LPC_ICH_H
#include <linux/platform_data/intel-spi.h>
/* GPIO resources */
#define ICH_RES_GPIO 0
#define ICH_RES_GPE0 1
@ -40,6 +42,7 @@ struct lpc_ich_info {
char name[32];
unsigned int iTCO_version;
unsigned int gpio_version;
enum intel_spi_type spi_type;
u8 use_gpio;
};

31
include/linux/platform_data/intel-spi.h Normal file
View File

@ -0,0 +1,31 @@
/*
* Intel PCH/PCU SPI flash driver.
*
* Copyright (C) 2016, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef INTEL_SPI_PDATA_H
#define INTEL_SPI_PDATA_H
enum intel_spi_type {
INTEL_SPI_BYT = 1,
INTEL_SPI_LPT,
INTEL_SPI_BXT,
};
/**
* struct intel_spi_boardinfo - Board specific data for Intel SPI driver
* @type: Type which this controller is compatible with
* @writeable: The chip is writeable
*/
struct intel_spi_boardinfo {
enum intel_spi_type type;
bool writeable;
};
#endif /* INTEL_SPI_PDATA_H */