The rk3399 gets support for its emmc controller as well as thermal,
i2c and core io-domain nodes and some reasonable default rates for core clocks. The rk3368 also gets io-domains for its r88 board as well as a small fix for the gic's memory regions. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCAAGBQJXdbPUAAoJEPOmecmc0R2BiAUH/2UBBQ1f5A9W5bCtxe+kirFa R+4tDNske10/h3ey+igciC+6SG4RavHyQn/MoQvu2rzeZvAoPRYi2IVR3/RERf86 uuDNMqI9C0zQNujuiN/1eVMLAhAUoDZ9+uC1uEJ6ilzKwcsk6Sb+8Fo/zQnR8evd Z4GK+YnJtLvxQ3joEh5AcRbd+CaURjAXeJt1HGlDcLCG8HHKNNDpzaFPV2uaoVXp 1hwx7X8tY5u13K0W7yAzaAq5C4poKa+OpdxlE5g+ryOFWqnqco4l/BBaWg+XK0z5 XvPjtDE5Di8Wpgjeik/4KLwG/maD9ogdPAZGmg+U2SkGlwVdcOSZmSOE2mFHf3c= =W2eY -----END PGP SIGNATURE----- Merge tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 The rk3399 gets support for its emmc controller as well as thermal, i2c and core io-domain nodes and some reasonable default rates for core clocks. The rk3368 also gets io-domains for its r88 board as well as a small fix for the gic's memory regions. * tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399 arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368 arm64: dts: rockchip: add i2c nodes for rk3399 arm64: dts: rockchip: add thermal nodes for rk3399 SoCs arm64: dts: rockchip: add rk3399 io-domain core nodes arm64: dts: rockchip: add rk3368-r88 iodomains arm64: dts: rockchip: add rk3368 io-domain core nodes arm64: dts: rockchip: make rk3368 grf syscons simple-mfds arm64: dts: rockchip: enable eMMC for rk3399 EVB arm64: dts: rockchip: add sdhci/emmc for rk3399 arm64: dts: rockchip: make rk3399's grf a "simple-mfd" arm64: dts: rockchip: assign default rates for core rk3399 clocks Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
135a2f38fa
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@ -236,6 +236,15 @@ hym8563: hym8563@51 {
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|||
};
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||||
};
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||||
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||||
&io_domains {
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status = "ok";
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audio-supply = <&vcc_io>;
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gpio30-supply = <&vcc_io>;
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gpio1830-supply = <&vcc_io>;
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wifi-supply = <&vccio_wl>;
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};
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&sdio0 {
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assigned-clocks = <&cru SCLK_SDIO0>;
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assigned-clock-parents = <&cru PLL_CPLL>;
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@ -329,6 +338,13 @@ host_vbus_drv: host-vbus-drv {
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};
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};
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&pmu_io_domains {
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status = "okay";
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pmu-supply = <&vcc_io>;
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vop-supply = <&vcc_io>;
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};
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&saradc {
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vref-supply = <&vcc_18>;
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status = "okay";
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|
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@ -632,8 +632,13 @@ mbox: mbox@ff6b0000 {
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};
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pmugrf: syscon@ff738000 {
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compatible = "rockchip,rk3368-pmugrf", "syscon";
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compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xff738000 0x0 0x1000>;
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pmu_io_domains: io-domains {
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compatible = "rockchip,rk3368-pmu-io-voltage-domain";
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status = "disabled";
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};
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};
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cru: clock-controller@ff760000 {
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@ -645,8 +650,13 @@ cru: clock-controller@ff760000 {
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};
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3368-grf", "syscon";
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compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
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reg = <0x0 0xff770000 0x0 0x1000>;
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io_domains: io-domains {
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compatible = "rockchip,rk3368-io-voltage-domain";
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status = "disabled";
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};
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};
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wdt: watchdog@ff800000 {
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@ -670,7 +680,7 @@ gic: interrupt-controller@ffb71000 {
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#address-cells = <0>;
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reg = <0x0 0xffb71000 0x0 0x1000>,
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<0x0 0xffb72000 0x0 0x1000>,
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<0x0 0xffb72000 0x0 0x2000>,
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<0x0 0xffb74000 0x0 0x2000>,
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<0x0 0xffb76000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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@ -77,6 +77,10 @@ vcc_phy: vcc-phy-regulator {
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};
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};
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&emmc_phy {
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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};
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@ -89,6 +93,14 @@ &pwm3 {
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status = "okay";
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};
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&sdhci {
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bus-width = <8>;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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non-removable;
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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|
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@ -45,6 +45,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,rk3399";
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@ -54,6 +55,15 @@ / {
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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@ -215,6 +225,22 @@ sdmmc: dwmmc@fe320000 {
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status = "disabled";
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};
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sdhci: sdhci@fe330000 {
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compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
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reg = <0x0 0xfe330000 0x0 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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arasan,soc-ctl-syscon = <&grf>;
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assigned-clocks = <&cru SCLK_EMMC>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb";
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clock-output-names = "emmc_cardclock";
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#clock-cells = <0>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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status = "disabled";
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};
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usb_host0_ehci: usb@fe380000 {
|
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compatible = "generic-ehci";
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reg = <0x0 0xfe380000 0x0 0x20000>;
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@ -272,6 +298,96 @@ its: interrupt-controller@fee20000 {
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|||
};
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||||
};
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i2c1: i2c@ff110000 {
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compatible = "rockchip,rk3399-i2c";
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reg = <0x0 0xff110000 0x0 0x1000>;
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assigned-clocks = <&cru SCLK_I2C1>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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||||
};
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i2c2: i2c@ff120000 {
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compatible = "rockchip,rk3399-i2c";
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reg = <0x0 0xff120000 0x0 0x1000>;
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assigned-clocks = <&cru SCLK_I2C2>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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||||
};
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i2c3: i2c@ff130000 {
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compatible = "rockchip,rk3399-i2c";
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reg = <0x0 0xff130000 0x0 0x1000>;
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assigned-clocks = <&cru SCLK_I2C3>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
status = "disabled";
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||||
};
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i2c5: i2c@ff140000 {
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compatible = "rockchip,rk3399-i2c";
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reg = <0x0 0xff140000 0x0 0x1000>;
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assigned-clocks = <&cru SCLK_I2C5>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c6: i2c@ff150000 {
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compatible = "rockchip,rk3399-i2c";
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reg = <0x0 0xff150000 0x0 0x1000>;
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assigned-clocks = <&cru SCLK_I2C6>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c7: i2c@ff160000 {
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compatible = "rockchip,rk3399-i2c";
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reg = <0x0 0xff160000 0x0 0x1000>;
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assigned-clocks = <&cru SCLK_I2C7>;
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assigned-clock-rates = <200000000>;
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clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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||||
};
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uart0: serial@ff180000 {
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compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff180000 0x0 0x100>;
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@ -389,9 +505,105 @@ spi5: spi@ff200000 {
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status = "disabled";
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};
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thermal-zones {
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cpu_thermal: cpu {
|
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polling-delay-passive = <100>;
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polling-delay = <1000>;
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thermal-sensors = <&tsadc 0>;
|
||||
|
||||
trips {
|
||||
cpu_alert0: cpu_alert0 {
|
||||
temperature = <70000>;
|
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hysteresis = <2000>;
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type = "passive";
|
||||
};
|
||||
cpu_alert1: cpu_alert1 {
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
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type = "passive";
|
||||
};
|
||||
cpu_crit: cpu_crit {
|
||||
temperature = <95000>;
|
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hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu_alert1>;
|
||||
cooling-device =
|
||||
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu_thermal: gpu {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsadc 1>;
|
||||
|
||||
trips {
|
||||
gpu_alert0: gpu_alert0 {
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
gpu_crit: gpu_crit {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpu_alert0>;
|
||||
cooling-device =
|
||||
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tsadc: tsadc@ff260000 {
|
||||
compatible = "rockchip,rk3399-tsadc";
|
||||
reg = <0x0 0xff260000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&cru SCLK_TSADC>;
|
||||
assigned-clock-rates = <750000>;
|
||||
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
clock-names = "tsadc", "apb_pclk";
|
||||
resets = <&cru SRST_TSADC>;
|
||||
reset-names = "tsadc-apb";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,hw-tshut-temp = <95000>;
|
||||
pinctrl-names = "init", "default", "sleep";
|
||||
pinctrl-0 = <&otp_gpio>;
|
||||
pinctrl-1 = <&otp_out>;
|
||||
pinctrl-2 = <&otp_gpio>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmugrf: syscon@ff320000 {
|
||||
compatible = "rockchip,rk3399-pmugrf", "syscon";
|
||||
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff320000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pmu_io_domains: io-domains {
|
||||
compatible = "rockchip,rk3399-pmu-io-voltage-domain";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi3: spi@ff350000 {
|
||||
|
|
@ -420,6 +632,51 @@ uart4: serial@ff370000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@ff3c0000 {
|
||||
compatible = "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xff3c0000 0x0 0x1000>;
|
||||
assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_xfer>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@ff3d0000 {
|
||||
compatible = "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xff3d0000 0x0 0x1000>;
|
||||
assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_xfer>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c@ff3e0000 {
|
||||
compatible = "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xff3e0000 0x0 0x1000>;
|
||||
assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c8_xfer>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@ff420000 {
|
||||
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
|
||||
reg = <0x0 0xff420000 0x0 0x10>;
|
||||
|
|
@ -478,11 +735,43 @@ cru: clock-controller@ff760000 {
|
|||
reg = <0x0 0xff760000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks =
|
||||
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
|
||||
<&cru PLL_NPLL>,
|
||||
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
|
||||
<&cru PCLK_PERIHP>,
|
||||
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
|
||||
<&cru PCLK_PERILP0>,
|
||||
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
|
||||
assigned-clock-rates =
|
||||
<594000000>, <800000000>,
|
||||
<1000000000>,
|
||||
<150000000>, <75000000>,
|
||||
<37500000>,
|
||||
<100000000>, <100000000>,
|
||||
<50000000>,
|
||||
<100000000>, <50000000>;
|
||||
};
|
||||
|
||||
grf: syscon@ff770000 {
|
||||
compatible = "rockchip,rk3399-grf", "syscon";
|
||||
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff770000 0x0 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
io_domains: io-domains {
|
||||
compatible = "rockchip,rk3399-io-voltage-domain";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emmc_phy: phy@f780 {
|
||||
compatible = "rockchip,rk3399-emmc-phy";
|
||||
reg = <0xf780 0x24>;
|
||||
clocks = <&sdhci>;
|
||||
clock-names = "emmcclk";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@ff840000 {
|
||||
|
|
@ -756,6 +1045,16 @@ i2s1_2ch_bus: i2s1-2ch-bus {
|
|||
};
|
||||
};
|
||||
|
||||
sleep {
|
||||
ap_pwroff: ap-pwroff {
|
||||
rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
ddrio_pwroff: ddrio-pwroff {
|
||||
rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
spdif {
|
||||
spdif_bus: spdif-bus {
|
||||
rockchip,pins =
|
||||
|
|
@ -881,6 +1180,16 @@ spi5_tx: spi5-tx {
|
|||
};
|
||||
};
|
||||
|
||||
tsadc {
|
||||
otp_gpio: otp-gpio {
|
||||
rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
otp_out: otp-out {
|
||||
rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins =
|
||||
|
|
|
|||
Loading…
Reference in New Issue