clk/samsung updates for v5.17
- removal of all remaining uses of __clk_lookup() in drivers/clk/samsung,
- refactoring of the CPU clocks registration to use common interface,
- an update of the Exynos850 driver (support for more clock domains)
required by the E850-96 development board,
- initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8).
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Merge tag 'clk-v5.17-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- removal of all remaining uses of __clk_lookup() in drivers/clk/samsung
- refactoring of the CPU clocks registration to use common interface
- an update of the Exynos850 driver (support for more clock domains)
required by the E850-96 development board
- initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
* tag 'clk-v5.17-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Add initial Exynos7885 clock driver
clk: samsung: clk-pll: Add support for pll1417x
clk: samsung: Make exynos850_register_cmu shared
dt-bindings: clock: Document Exynos7885 CMU bindings
dt-bindings: clock: Add bindings definitions for Exynos7885 CMU
clk: samsung: exynos850: Add missing sysreg clocks
dt-bindings: clock: Add bindings for Exynos850 sysreg clocks
clk: samsung: exynos850: Register clocks early
clk: samsung: exynos850: Keep some crucial clocks running
clk: samsung: exynos850: Implement CMU_CMGP domain
dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP
clk: samsung: exynos850: Implement CMU_APM domain
dt-bindings: clock: Add bindings for Exynos850 CMU_APM
clk: samsung: Update CPU clk registration
clk: samsung: Remove meaningless __init and extern from header files
clk: samsung: remove __clk_lookup() usage
dt-bindings: clock: samsung: add IDs for some core clocks
This commit is contained in:
Stephen Boyd
commit
14350ed958
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|
@ -0,0 +1,166 @@
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|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos7885 SoC clock controller
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maintainers:
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- Dávid Virág <virag.david003@gmail.com>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Tomasz Figa <tomasz.figa@gmail.com>
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description: |
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Exynos7885 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. The root clock in that root tree
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is an external clock: OSCCLK (26 MHz). This external clock must be defined
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as a fixed-rate clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'dt-bindings/clock/exynos7885.h' header.
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properties:
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compatible:
|
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enum:
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- samsung,exynos7885-cmu-top
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- samsung,exynos7885-cmu-core
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- samsung,exynos7885-cmu-peri
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|
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clocks:
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minItems: 1
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maxItems: 10
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|
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clock-names:
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||||
minItems: 1
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||||
maxItems: 10
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||||
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"#clock-cells":
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const: 1
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|
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reg:
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||||
maxItems: 1
|
||||
|
||||
allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7885-cmu-top
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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||||
clock-names:
|
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items:
|
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- const: oscclk
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- if:
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properties:
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compatible:
|
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contains:
|
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const: samsung,exynos7885-cmu-core
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|
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then:
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properties:
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clocks:
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items:
|
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- description: External reference clock (26 MHz)
|
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- description: CMU_CORE bus clock (from CMU_TOP)
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- description: CCI clock (from CMU_TOP)
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- description: G3D clock (from CMU_TOP)
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||||
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clock-names:
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items:
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- const: oscclk
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- const: dout_core_bus
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- const: dout_core_cci
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- const: dout_core_g3d
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7885-cmu-peri
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|
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_PERI bus clock (from CMU_TOP)
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- description: SPI0 clock (from CMU_TOP)
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- description: SPI1 clock (from CMU_TOP)
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- description: UART0 clock (from CMU_TOP)
|
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- description: UART1 clock (from CMU_TOP)
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- description: UART2 clock (from CMU_TOP)
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- description: USI0 clock (from CMU_TOP)
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- description: USI1 clock (from CMU_TOP)
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- description: USI2 clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_peri_bus
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- const: dout_peri_spi0
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- const: dout_peri_spi1
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- const: dout_peri_uart0
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- const: dout_peri_uart1
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- const: dout_peri_uart2
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- const: dout_peri_usi0
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- const: dout_peri_usi1
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- const: dout_peri_usi2
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required:
|
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- compatible
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- "#clock-cells"
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- clocks
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- clock-names
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- reg
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additionalProperties: false
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examples:
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# Clock controller node for CMU_PERI
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- |
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#include <dt-bindings/clock/exynos7885.h>
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cmu_peri: clock-controller@10010000 {
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compatible = "samsung,exynos7885-cmu-peri";
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reg = <0x10010000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_PERI_BUS>,
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<&cmu_top CLK_DOUT_PERI_SPI0>,
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<&cmu_top CLK_DOUT_PERI_SPI1>,
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<&cmu_top CLK_DOUT_PERI_UART0>,
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<&cmu_top CLK_DOUT_PERI_UART1>,
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<&cmu_top CLK_DOUT_PERI_UART2>,
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<&cmu_top CLK_DOUT_PERI_USI0>,
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<&cmu_top CLK_DOUT_PERI_USI1>,
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<&cmu_top CLK_DOUT_PERI_USI2>;
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clock-names = "oscclk",
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"dout_peri_bus",
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"dout_peri_spi0",
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"dout_peri_spi1",
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"dout_peri_uart0",
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"dout_peri_uart1",
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"dout_peri_uart2",
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"dout_peri_usi0",
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"dout_peri_usi1",
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"dout_peri_usi2";
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};
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|
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...
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|
|
@ -32,6 +32,8 @@ properties:
|
|||
compatible:
|
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enum:
|
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- samsung,exynos850-cmu-top
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- samsung,exynos850-cmu-apm
|
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- samsung,exynos850-cmu-cmgp
|
||||
- samsung,exynos850-cmu-core
|
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- samsung,exynos850-cmu-dpu
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- samsung,exynos850-cmu-hsi
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|
|
@ -68,6 +70,42 @@ allOf:
|
|||
items:
|
||||
- const: oscclk
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- if:
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properties:
|
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compatible:
|
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contains:
|
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const: samsung,exynos850-cmu-apm
|
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|
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then:
|
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properties:
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||||
clocks:
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items:
|
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- description: External reference clock (26 MHz)
|
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- description: CMU_APM bus clock (from CMU_TOP)
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clock-names:
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items:
|
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- const: oscclk
|
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- const: dout_clkcmu_apm_bus
|
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|
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- if:
|
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properties:
|
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compatible:
|
||||
contains:
|
||||
const: samsung,exynos850-cmu-cmgp
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_CMGP bus clock (from CMU_APM)
|
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|
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clock-names:
|
||||
items:
|
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- const: oscclk
|
||||
- const: gout_clkcmu_cmgp_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -16,7 +16,9 @@ obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
|
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obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
|
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obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
|
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
|
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obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
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obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
|
||||
|
|
|
|||
|
|
@ -400,7 +400,7 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
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|||
}
|
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|
||||
/* helper function to register a CPU clock */
|
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int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
|
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static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
|
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unsigned int lookup_id, const char *name,
|
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const struct clk_hw *parent, const struct clk_hw *alt_parent,
|
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unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
|
||||
|
|
|
|||
|
|
@ -62,11 +62,4 @@ struct exynos_cpuclk {
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#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
|
||||
};
|
||||
|
||||
int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
|
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unsigned int lookup_id, const char *name,
|
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const struct clk_hw *parent, const struct clk_hw *alt_parent,
|
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unsigned long offset,
|
||||
const struct exynos_cpuclk_cfg_data *cfg,
|
||||
unsigned long num_cfgs, unsigned long flags);
|
||||
|
||||
#endif /* __SAMSUNG_CLK_CPU_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,94 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2021 Linaro Ltd.
|
||||
* Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
|
||||
* Author: Sam Protsenko <semen.protsenko@linaro.org>
|
||||
* Author: Dávid Virág <virag.david003@gmail.com>
|
||||
*
|
||||
* This file contains shared functions used by some arm64 Exynos SoCs,
|
||||
* such as Exynos7885 or Exynos850 to register and init CMUs.
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "clk-exynos-arm64.h"
|
||||
|
||||
/* Gate register bits */
|
||||
#define GATE_MANUAL BIT(20)
|
||||
#define GATE_ENABLE_HWACG BIT(28)
|
||||
|
||||
/* Gate register offsets range */
|
||||
#define GATE_OFF_START 0x2000
|
||||
#define GATE_OFF_END 0x2fff
|
||||
|
||||
/**
|
||||
* exynos_arm64_init_clocks - Set clocks initial configuration
|
||||
* @np: CMU device tree node with "reg" property (CMU addr)
|
||||
* @reg_offs: Register offsets array for clocks to init
|
||||
* @reg_offs_len: Number of register offsets in reg_offs array
|
||||
*
|
||||
* Set manual control mode for all gate clocks.
|
||||
*/
|
||||
static void __init exynos_arm64_init_clocks(struct device_node *np,
|
||||
const unsigned long *reg_offs, size_t reg_offs_len)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
size_t i;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
for (i = 0; i < reg_offs_len; ++i) {
|
||||
void __iomem *reg = reg_base + reg_offs[i];
|
||||
u32 val;
|
||||
|
||||
/* Modify only gate clock registers */
|
||||
if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
|
||||
continue;
|
||||
|
||||
val = readl(reg);
|
||||
val |= GATE_MANUAL;
|
||||
val &= ~GATE_ENABLE_HWACG;
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
iounmap(reg_base);
|
||||
}
|
||||
|
||||
/**
|
||||
* exynos_arm64_register_cmu - Register specified Exynos CMU domain
|
||||
* @dev: Device object; may be NULL if this function is not being
|
||||
* called from platform driver probe function
|
||||
* @np: CMU device tree node
|
||||
* @cmu: CMU data
|
||||
*
|
||||
* Register specified CMU domain, which includes next steps:
|
||||
*
|
||||
* 1. Enable parent clock of @cmu CMU
|
||||
* 2. Set initial registers configuration for @cmu CMU clocks
|
||||
* 3. Register @cmu CMU clocks using Samsung clock framework API
|
||||
*/
|
||||
void __init exynos_arm64_register_cmu(struct device *dev,
|
||||
struct device_node *np, const struct samsung_cmu_info *cmu)
|
||||
{
|
||||
/* Keep CMU parent clock running (needed for CMU registers access) */
|
||||
if (cmu->clk_name) {
|
||||
struct clk *parent_clk;
|
||||
|
||||
if (dev)
|
||||
parent_clk = clk_get(dev, cmu->clk_name);
|
||||
else
|
||||
parent_clk = of_clk_get_by_name(np, cmu->clk_name);
|
||||
|
||||
if (IS_ERR(parent_clk)) {
|
||||
pr_err("%s: could not find bus clock %s; err = %ld\n",
|
||||
__func__, cmu->clk_name, PTR_ERR(parent_clk));
|
||||
} else {
|
||||
clk_prepare_enable(parent_clk);
|
||||
}
|
||||
}
|
||||
|
||||
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
|
||||
samsung_cmu_register_one(np, cmu);
|
||||
}
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2021 Linaro Ltd.
|
||||
* Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
|
||||
* Author: Sam Protsenko <semen.protsenko@linaro.org>
|
||||
* Author: Dávid Virág <virag.david003@gmail.com>
|
||||
*
|
||||
* This file contains shared functions used by some arm64 Exynos SoCs,
|
||||
* such as Exynos7885 or Exynos850 to register and init CMUs.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_EXYNOS_ARM64_H
|
||||
#define __CLK_EXYNOS_ARM64_H
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
void exynos_arm64_register_cmu(struct device *dev,
|
||||
struct device_node *np, const struct samsung_cmu_info *cmu);
|
||||
|
||||
#endif /* __CLK_EXYNOS_ARM64_H */
|
||||
|
|
@ -748,6 +748,31 @@ static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
|
|||
UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
|
||||
};
|
||||
|
||||
#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
|
||||
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
|
||||
((corem) << 4))
|
||||
#define E3250_CPU_DIV1(hpm, copy) \
|
||||
(((hpm) << 4) | ((copy) << 0))
|
||||
|
||||
static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
|
||||
{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {
|
||||
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
|
||||
CLK_CPU_HAS_DIV1, 0x14200, e3250_armclk_d),
|
||||
};
|
||||
|
||||
static void __init exynos3_core_down_clock(void __iomem *reg_base)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
|
@ -780,46 +805,21 @@ static const struct samsung_cmu_info cmu_info __initconst = {
|
|||
.nr_gate_clks = ARRAY_SIZE(gate_clks),
|
||||
.fixed_factor_clks = fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
|
||||
.cpu_clks = exynos3250_cpu_clks,
|
||||
.nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),
|
||||
.nr_clk_ids = CLK_NR_CLKS,
|
||||
.clk_regs = exynos3250_cmu_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
|
||||
};
|
||||
|
||||
#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
|
||||
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
|
||||
((corem) << 4))
|
||||
#define E3250_CPU_DIV1(hpm, copy) \
|
||||
(((hpm) << 4) | ((copy) << 0))
|
||||
|
||||
static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
|
||||
{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static void __init exynos3250_cmu_init(struct device_node *np)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
|
||||
ctx = samsung_cmu_register_one(np, &cmu_info);
|
||||
if (!ctx)
|
||||
return;
|
||||
|
||||
hws = ctx->clk_data.hws;
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
|
||||
0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
|
||||
CLK_CPU_HAS_DIV1);
|
||||
|
||||
exynos3_core_down_clock(ctx->reg_base);
|
||||
}
|
||||
CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@ static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
|
|||
|
||||
/* list of mux clocks supported in exynos4210 soc */
|
||||
static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
|
||||
MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
|
||||
MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
|
||||
|
|
@ -603,7 +603,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
|
|||
DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
|
||||
DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
|
||||
DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
|
||||
DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
|
||||
DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
|
||||
DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
|
||||
DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
|
||||
DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
|
||||
|
|
@ -1228,6 +1228,16 @@ static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
|
|||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
|
||||
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),
|
||||
};
|
||||
|
||||
static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
|
||||
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
|
||||
};
|
||||
|
||||
/* register exynos4 clocks */
|
||||
static void __init exynos4_clk_init(struct device_node *np,
|
||||
enum exynos4_soc soc)
|
||||
|
|
@ -1254,21 +1264,21 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
samsung_clk_register_mux(ctx, exynos4210_mux_early,
|
||||
ARRAY_SIZE(exynos4210_mux_early));
|
||||
|
||||
if (_get_rate("fin_pll") == 24000000) {
|
||||
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
|
||||
exynos4210_plls[apll].rate_table =
|
||||
exynos4210_apll_rates;
|
||||
exynos4210_plls[epll].rate_table =
|
||||
exynos4210_epll_rates;
|
||||
}
|
||||
|
||||
if (_get_rate("mout_vpllsrc") == 24000000)
|
||||
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)
|
||||
exynos4210_plls[vpll].rate_table =
|
||||
exynos4210_vpll_rates;
|
||||
|
||||
samsung_clk_register_pll(ctx, exynos4210_plls,
|
||||
ARRAY_SIZE(exynos4210_plls), reg_base);
|
||||
} else {
|
||||
if (_get_rate("fin_pll") == 24000000) {
|
||||
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
|
||||
exynos4x12_plls[apll].rate_table =
|
||||
exynos4x12_apll_rates;
|
||||
exynos4x12_plls[epll].rate_table =
|
||||
|
|
@ -1304,10 +1314,8 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
samsung_clk_register_fixed_factor(ctx,
|
||||
exynos4210_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4210_fixed_factor_clks));
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
|
||||
e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
|
||||
samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
|
||||
ARRAY_SIZE(exynos4210_cpu_clks));
|
||||
} else {
|
||||
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
|
||||
ARRAY_SIZE(exynos4x12_mux_clks));
|
||||
|
|
@ -1318,11 +1326,8 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
samsung_clk_register_fixed_factor(ctx,
|
||||
exynos4x12_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
|
||||
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
|
||||
e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
|
||||
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
|
||||
ARRAY_SIZE(exynos4412_cpu_clks));
|
||||
}
|
||||
|
||||
if (soc == EXYNOS4X12)
|
||||
|
|
@ -1344,9 +1349,11 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
|
||||
"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
|
||||
exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
|
||||
_get_rate("sclk_apll"), _get_rate("sclk_mpll"),
|
||||
_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
|
||||
_get_rate("div_core2"));
|
||||
clk_hw_get_rate(hws[CLK_SCLK_APLL]),
|
||||
clk_hw_get_rate(hws[CLK_SCLK_MPLL]),
|
||||
clk_hw_get_rate(hws[CLK_SCLK_EPLL]),
|
||||
clk_hw_get_rate(hws[CLK_SCLK_VPLL]),
|
||||
clk_hw_get_rate(hws[CLK_DIV_CORE2]));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -239,7 +239,7 @@ static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __
|
|||
};
|
||||
|
||||
static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
|
||||
MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
|
||||
MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
|
||||
|
|
@ -351,7 +351,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
|
|||
*/
|
||||
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
|
||||
DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
|
||||
DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
|
||||
DIV(CLK_DIV_ARM2, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
|
||||
|
||||
/*
|
||||
* CMU_TOP
|
||||
|
|
@ -772,6 +772,11 @@ static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
|
|||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
|
||||
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200,
|
||||
exynos5250_armclk_d),
|
||||
};
|
||||
|
||||
static const struct of_device_id ext_clk_match[] __initconst = {
|
||||
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
|
||||
{ },
|
||||
|
|
@ -801,12 +806,12 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
|
||||
ARRAY_SIZE(exynos5250_pll_pmux_clks));
|
||||
|
||||
if (_get_rate("fin_pll") == 24 * MHZ) {
|
||||
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
|
||||
exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
|
||||
exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
|
||||
}
|
||||
|
||||
if (_get_rate("mout_vpllsrc") == 24 * MHZ)
|
||||
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)
|
||||
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
|
||||
|
||||
samsung_clk_register_pll(ctx, exynos5250_plls,
|
||||
|
|
@ -822,10 +827,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
ARRAY_SIZE(exynos5250_div_clks));
|
||||
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
|
||||
ARRAY_SIZE(exynos5250_gate_clks));
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
|
||||
exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
|
||||
CLK_CPU_HAS_DIV1);
|
||||
samsung_clk_register_cpu(ctx, exynos5250_cpu_clks,
|
||||
ARRAY_SIZE(exynos5250_cpu_clks));
|
||||
|
||||
/*
|
||||
* Enable arm clock down (in idle) and set arm divider
|
||||
|
|
@ -855,6 +858,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
|
||||
_get_rate("div_arm2"));
|
||||
clk_hw_get_rate(hws[CLK_DIV_ARM2]));
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
|
||||
|
|
|
|||
|
|
@ -1551,6 +1551,20 @@ static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
|
|||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {
|
||||
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
|
||||
exynos5420_eglclk_d),
|
||||
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
|
||||
exynos5420_kfcclk_d),
|
||||
};
|
||||
|
||||
static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {
|
||||
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
|
||||
exynos5800_eglclk_d),
|
||||
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
|
||||
exynos5420_kfcclk_d),
|
||||
};
|
||||
|
||||
static const struct of_device_id ext_clk_match[] __initconst = {
|
||||
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
|
||||
{ },
|
||||
|
|
@ -1580,7 +1594,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
|||
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
|
||||
ext_clk_match);
|
||||
|
||||
if (_get_rate("fin_pll") == 24 * MHZ) {
|
||||
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
|
||||
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
|
||||
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
|
||||
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
|
||||
|
|
@ -1625,17 +1639,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
|||
}
|
||||
|
||||
if (soc == EXYNOS5420) {
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
|
||||
exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
|
||||
samsung_clk_register_cpu(ctx, exynos5420_cpu_clks,
|
||||
ARRAY_SIZE(exynos5420_cpu_clks));
|
||||
} else {
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
|
||||
exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
|
||||
samsung_clk_register_cpu(ctx, exynos5800_cpu_clks,
|
||||
ARRAY_SIZE(exynos5800_cpu_clks));
|
||||
}
|
||||
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
|
||||
hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200,
|
||||
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
|
||||
|
||||
samsung_clk_extended_sleep_init(reg_base,
|
||||
exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
|
||||
|
|
|
|||
|
|
@ -0,0 +1,597 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
|
||||
* Author: Dávid Virág <virag.david003@gmail.com>
|
||||
*
|
||||
* Common Clock Framework support for Exynos7885 SoC.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <dt-bindings/clock/exynos7885.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-exynos-arm64.h"
|
||||
|
||||
/* ---- CMU_TOP ------------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_TOP (0x12060000) */
|
||||
#define PLL_LOCKTIME_PLL_SHARED0 0x0000
|
||||
#define PLL_LOCKTIME_PLL_SHARED1 0x0004
|
||||
#define PLL_CON0_PLL_SHARED0 0x0100
|
||||
#define PLL_CON0_PLL_SHARED1 0x0120
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890
|
||||
#define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894
|
||||
#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c
|
||||
#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0
|
||||
#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4
|
||||
#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8
|
||||
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac
|
||||
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0
|
||||
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4
|
||||
#define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098
|
||||
|
||||
static const unsigned long top_clk_regs[] __initconst = {
|
||||
PLL_LOCKTIME_PLL_SHARED0,
|
||||
PLL_LOCKTIME_PLL_SHARED1,
|
||||
PLL_CON0_PLL_SHARED0,
|
||||
PLL_CON0_PLL_SHARED1,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_UART0,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_UART1,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_UART2,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_USI0,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_USI1,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_USI2,
|
||||
CLK_CON_DIV_CLKCMU_CORE_BUS,
|
||||
CLK_CON_DIV_CLKCMU_CORE_CCI,
|
||||
CLK_CON_DIV_CLKCMU_CORE_G3D,
|
||||
CLK_CON_DIV_CLKCMU_PERI_BUS,
|
||||
CLK_CON_DIV_CLKCMU_PERI_SPI0,
|
||||
CLK_CON_DIV_CLKCMU_PERI_SPI1,
|
||||
CLK_CON_DIV_CLKCMU_PERI_UART0,
|
||||
CLK_CON_DIV_CLKCMU_PERI_UART1,
|
||||
CLK_CON_DIV_CLKCMU_PERI_UART2,
|
||||
CLK_CON_DIV_CLKCMU_PERI_USI0,
|
||||
CLK_CON_DIV_CLKCMU_PERI_USI1,
|
||||
CLK_CON_DIV_CLKCMU_PERI_USI2,
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV2,
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV3,
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV4,
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV5,
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV2,
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV3,
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV4,
|
||||
CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_UART0,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_UART2,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_USI0,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_USI1,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_USI2,
|
||||
};
|
||||
|
||||
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
|
||||
PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
|
||||
NULL),
|
||||
PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1,
|
||||
NULL),
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
|
||||
PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared0_div3", "dout_shared0_div3" };
|
||||
PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared0_div3", "dout_shared0_div3" };
|
||||
PNAME(mout_core_g3d_p) = { "dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared0_div3", "dout_shared0_div3" };
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
|
||||
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
|
||||
PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
|
||||
PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
|
||||
PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
|
||||
PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
|
||||
PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
|
||||
PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
|
||||
PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" };
|
||||
PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" };
|
||||
|
||||
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
|
||||
/* CORE */
|
||||
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
|
||||
MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
|
||||
MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
|
||||
|
||||
/* PERI */
|
||||
MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
|
||||
MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1),
|
||||
MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1),
|
||||
MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1),
|
||||
MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1),
|
||||
MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1),
|
||||
MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1),
|
||||
MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
|
||||
MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock top_div_clks[] __initconst = {
|
||||
/* TOP */
|
||||
DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
|
||||
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
|
||||
DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
|
||||
DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
|
||||
DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
|
||||
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
|
||||
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
|
||||
|
||||
/* CORE */
|
||||
DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
|
||||
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3),
|
||||
DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
|
||||
CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3),
|
||||
DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d",
|
||||
CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3),
|
||||
|
||||
/* PERI */
|
||||
DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
|
||||
CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
|
||||
DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0",
|
||||
CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6),
|
||||
DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1",
|
||||
CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6),
|
||||
DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0",
|
||||
CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4),
|
||||
DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1",
|
||||
CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4),
|
||||
DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2",
|
||||
CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4),
|
||||
DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0",
|
||||
CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4),
|
||||
DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1",
|
||||
CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
|
||||
DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
|
||||
CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
|
||||
/* CORE */
|
||||
GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0),
|
||||
|
||||
/* PERI */
|
||||
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0",
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1",
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0",
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1",
|
||||
CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2",
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0",
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1",
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info top_cmu_info __initconst = {
|
||||
.pll_clks = top_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
|
||||
.mux_clks = top_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
|
||||
.div_clks = top_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(top_div_clks),
|
||||
.gate_clks = top_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
|
||||
.nr_clk_ids = TOP_NR_CLK,
|
||||
.clk_regs = top_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7885_cmu_top_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_TOP early, as it's a dependency for other early domains */
|
||||
CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top",
|
||||
exynos7885_cmu_top_init);
|
||||
|
||||
/* ---- CMU_PERI ------------------------------------------------------------ */
|
||||
|
||||
/* Register Offset definitions for CMU_PERI (0x10010000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0
|
||||
#define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200
|
||||
#define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024
|
||||
#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
|
||||
#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c
|
||||
#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030
|
||||
#define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034
|
||||
#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038
|
||||
#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c
|
||||
#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040
|
||||
#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044
|
||||
#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048
|
||||
#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c
|
||||
#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050
|
||||
#define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054
|
||||
#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058
|
||||
#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c
|
||||
#define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060
|
||||
#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064
|
||||
#define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068
|
||||
#define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c
|
||||
#define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070
|
||||
#define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074
|
||||
#define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078
|
||||
#define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c
|
||||
#define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080
|
||||
#define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084
|
||||
#define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088
|
||||
#define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c
|
||||
#define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090
|
||||
#define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094
|
||||
#define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098
|
||||
#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0
|
||||
#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0
|
||||
#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4
|
||||
#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8
|
||||
|
||||
static const unsigned long peri_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_UART0_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_UART1_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_UART2_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_USI0_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_USI1_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_USI2_USER,
|
||||
CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK,
|
||||
CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK,
|
||||
CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_UART_0_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_UART_1_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_UART_2_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_USI0_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_USI0_SCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_USI1_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_USI1_SCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_USI2_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_USI2_SCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERI */
|
||||
PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
|
||||
PNAME(mout_peri_spi0_user_p) = { "oscclk", "dout_peri_spi0" };
|
||||
PNAME(mout_peri_spi1_user_p) = { "oscclk", "dout_peri_spi1" };
|
||||
PNAME(mout_peri_uart0_user_p) = { "oscclk", "dout_peri_uart0" };
|
||||
PNAME(mout_peri_uart1_user_p) = { "oscclk", "dout_peri_uart1" };
|
||||
PNAME(mout_peri_uart2_user_p) = { "oscclk", "dout_peri_uart2" };
|
||||
PNAME(mout_peri_usi0_user_p) = { "oscclk", "dout_peri_usi0" };
|
||||
PNAME(mout_peri_usi1_user_p) = { "oscclk", "dout_peri_usi1" };
|
||||
PNAME(mout_peri_usi2_user_p) = { "oscclk", "dout_peri_usi2" };
|
||||
|
||||
static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user",
|
||||
mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user",
|
||||
mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user",
|
||||
mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user",
|
||||
mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user",
|
||||
mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user",
|
||||
mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
|
||||
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
|
||||
GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk",
|
||||
"mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
|
||||
"mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user",
|
||||
CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user",
|
||||
CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user",
|
||||
CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user",
|
||||
CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user",
|
||||
CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user",
|
||||
CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user",
|
||||
CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user",
|
||||
CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
|
||||
"mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peri_cmu_info __initconst = {
|
||||
.mux_clks = peri_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
|
||||
.gate_clks = peri_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
|
||||
.nr_clk_ids = PERI_NR_CLK,
|
||||
.clk_regs = peri_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
|
||||
.clk_name = "dout_peri_bus",
|
||||
};
|
||||
|
||||
static void __init exynos7885_cmu_peri_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_PERI early, as it's needed for MCT timer */
|
||||
CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
|
||||
exynos7885_cmu_peri_init);
|
||||
|
||||
/* ---- CMU_CORE ------------------------------------------------------------ */
|
||||
|
||||
/* Register Offset definitions for CMU_CORE (0x12000000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100
|
||||
#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120
|
||||
#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140
|
||||
#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
|
||||
#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
|
||||
#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054
|
||||
#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058
|
||||
|
||||
static const unsigned long core_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
|
||||
PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
|
||||
PLL_CON0_MUX_CLKCMU_CORE_G3D_USER,
|
||||
CLK_CON_MUX_MUX_CLK_CORE_GIC,
|
||||
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
|
||||
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
|
||||
CLK_CON_GAT_GOUT_CORE_GIC400_CLK,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_CORE */
|
||||
PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
|
||||
PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
|
||||
PNAME(mout_core_g3d_user_p) = { "oscclk", "dout_core_g3d" };
|
||||
PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
|
||||
|
||||
static const struct samsung_mux_clock core_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
|
||||
MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
|
||||
MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1),
|
||||
MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
|
||||
CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock core_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
|
||||
CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock core_gate_clks[] __initconst = {
|
||||
/* CCI (interconnect) clock must be always running */
|
||||
GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
|
||||
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
|
||||
/* GIC (interrupt controller) clock must be always running */
|
||||
GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",
|
||||
CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info core_cmu_info __initconst = {
|
||||
.mux_clks = core_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(core_mux_clks),
|
||||
.div_clks = core_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(core_div_clks),
|
||||
.gate_clks = core_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
|
||||
.nr_clk_ids = CORE_NR_CLK,
|
||||
.clk_regs = core_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
|
||||
.clk_name = "dout_core_bus",
|
||||
};
|
||||
|
||||
/* ---- platform_driver ----------------------------------------------------- */
|
||||
|
||||
static int __init exynos7885_cmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct samsung_cmu_info *info;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
info = of_device_get_match_data(dev);
|
||||
exynos_arm64_register_cmu(dev, dev->of_node, info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id exynos7885_cmu_of_match[] = {
|
||||
{
|
||||
.compatible = "samsung,exynos7885-cmu-core",
|
||||
.data = &core_cmu_info,
|
||||
}, {
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_driver exynos7885_cmu_driver __refdata = {
|
||||
.driver = {
|
||||
.name = "exynos7885-cmu",
|
||||
.of_match_table = exynos7885_cmu_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = exynos7885_cmu_probe,
|
||||
};
|
||||
|
||||
static int __init exynos7885_cmu_init(void)
|
||||
{
|
||||
return platform_driver_register(&exynos7885_cmu_driver);
|
||||
}
|
||||
core_initcall(exynos7885_cmu_init);
|
||||
|
|
@ -9,56 +9,13 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <dt-bindings/clock/exynos850.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
/* Gate register bits */
|
||||
#define GATE_MANUAL BIT(20)
|
||||
#define GATE_ENABLE_HWACG BIT(28)
|
||||
|
||||
/* Gate register offsets range */
|
||||
#define GATE_OFF_START 0x2000
|
||||
#define GATE_OFF_END 0x2fff
|
||||
|
||||
/**
|
||||
* exynos850_init_clocks - Set clocks initial configuration
|
||||
* @np: CMU device tree node with "reg" property (CMU addr)
|
||||
* @reg_offs: Register offsets array for clocks to init
|
||||
* @reg_offs_len: Number of register offsets in reg_offs array
|
||||
*
|
||||
* Set manual control mode for all gate clocks.
|
||||
*/
|
||||
static void __init exynos850_init_clocks(struct device_node *np,
|
||||
const unsigned long *reg_offs, size_t reg_offs_len)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
size_t i;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
for (i = 0; i < reg_offs_len; ++i) {
|
||||
void __iomem *reg = reg_base + reg_offs[i];
|
||||
u32 val;
|
||||
|
||||
/* Modify only gate clock registers */
|
||||
if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
|
||||
continue;
|
||||
|
||||
val = readl(reg);
|
||||
val |= GATE_MANUAL;
|
||||
val &= ~GATE_ENABLE_HWACG;
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
iounmap(reg_base);
|
||||
}
|
||||
#include "clk-exynos-arm64.h"
|
||||
|
||||
/* ---- CMU_TOP ------------------------------------------------------------- */
|
||||
|
||||
|
|
@ -72,6 +29,7 @@ static void __init exynos850_init_clocks(struct device_node *np,
|
|||
#define PLL_CON3_PLL_SHARED0 0x014c
|
||||
#define PLL_CON0_PLL_SHARED1 0x0180
|
||||
#define PLL_CON3_PLL_SHARED1 0x018c
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
|
||||
|
|
@ -83,6 +41,7 @@ static void __init exynos850_init_clocks(struct device_node *np,
|
|||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
|
||||
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
|
||||
|
|
@ -100,6 +59,7 @@ static void __init exynos850_init_clocks(struct device_node *np,
|
|||
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
|
||||
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
|
||||
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
|
||||
|
|
@ -122,6 +82,7 @@ static const unsigned long top_clk_regs[] __initconst = {
|
|||
PLL_CON3_PLL_SHARED0,
|
||||
PLL_CON0_PLL_SHARED1,
|
||||
PLL_CON3_PLL_SHARED1,
|
||||
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
|
||||
|
|
@ -133,6 +94,7 @@ static const unsigned long top_clk_regs[] __initconst = {
|
|||
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
|
||||
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
|
||||
CLK_CON_DIV_CLKCMU_APM_BUS,
|
||||
CLK_CON_DIV_CLKCMU_CORE_BUS,
|
||||
CLK_CON_DIV_CLKCMU_CORE_CCI,
|
||||
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
|
||||
|
|
@ -150,6 +112,7 @@ static const unsigned long top_clk_regs[] __initconst = {
|
|||
CLK_CON_DIV_PLL_SHARED1_DIV2,
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV3,
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV4,
|
||||
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
|
||||
|
|
@ -183,6 +146,8 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
|
|||
PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
|
||||
PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
|
||||
PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
|
||||
/* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
|
||||
PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
|
||||
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
|
||||
PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
|
||||
"dout_shared1_div3", "dout_shared0_div4" };
|
||||
|
|
@ -222,6 +187,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
|
|||
MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
|
||||
PLL_CON0_PLL_MMC, 4, 1),
|
||||
|
||||
/* APM */
|
||||
MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
|
||||
mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
|
||||
|
||||
/* CORE */
|
||||
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
|
||||
|
|
@ -268,6 +237,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
|
|||
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
|
||||
|
||||
/* APM */
|
||||
DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
|
||||
"gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
|
||||
|
||||
/* CORE */
|
||||
DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
|
||||
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
|
||||
|
|
@ -310,6 +283,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
|
|||
GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
|
||||
|
||||
/* APM */
|
||||
GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
|
||||
"mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
|
||||
|
||||
/* DPU */
|
||||
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
|
||||
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
|
||||
|
|
@ -347,13 +324,248 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
|
|||
|
||||
static void __init exynos850_cmu_top_init(struct device_node *np)
|
||||
{
|
||||
exynos850_init_clocks(np, top_clk_regs, ARRAY_SIZE(top_clk_regs));
|
||||
samsung_cmu_register_one(np, &top_cmu_info);
|
||||
exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_TOP early, as it's a dependency for other early domains */
|
||||
CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
|
||||
exynos850_cmu_top_init);
|
||||
|
||||
/* ---- CMU_APM ------------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_APM (0x11800000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
|
||||
#define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
|
||||
#define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
|
||||
#define PLL_CON0_MUX_DLL_USER 0x0630
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
|
||||
#define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
|
||||
#define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
|
||||
#define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
|
||||
#define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
|
||||
#define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
|
||||
#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
|
||||
#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
|
||||
#define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
|
||||
#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
|
||||
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
|
||||
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
|
||||
#define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
|
||||
#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
|
||||
|
||||
static const unsigned long apm_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
|
||||
PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
|
||||
PLL_CON0_MUX_CLK_RCO_APM_USER,
|
||||
PLL_CON0_MUX_DLL_USER,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
|
||||
CLK_CON_MUX_MUX_CLK_APM_BUS,
|
||||
CLK_CON_MUX_MUX_CLK_APM_I3C,
|
||||
CLK_CON_DIV_CLKCMU_CHUB_BUS,
|
||||
CLK_CON_DIV_DIV_CLK_APM_BUS,
|
||||
CLK_CON_DIV_DIV_CLK_APM_I3C,
|
||||
CLK_CON_GAT_CLKCMU_CMGP_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
|
||||
CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
|
||||
CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
|
||||
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
|
||||
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
|
||||
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
|
||||
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
|
||||
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
|
||||
CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_APM */
|
||||
PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
|
||||
PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
|
||||
PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" };
|
||||
PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" };
|
||||
PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" };
|
||||
PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user",
|
||||
"mout_dll_user", "oscclk_rco_apm" };
|
||||
PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
|
||||
|
||||
static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
|
||||
FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
|
||||
FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
|
||||
FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
|
||||
FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
|
||||
};
|
||||
|
||||
static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
|
||||
MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
|
||||
mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
|
||||
MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
|
||||
PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
|
||||
MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
|
||||
PLL_CON0_MUX_DLL_USER, 4, 1),
|
||||
MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
|
||||
mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
|
||||
MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
|
||||
CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
|
||||
MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
|
||||
CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock apm_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
|
||||
"gout_clkcmu_chub_bus",
|
||||
CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
|
||||
DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
|
||||
CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
|
||||
DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
|
||||
CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
|
||||
CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
|
||||
"mout_clkcmu_chub_bus",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
|
||||
GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
|
||||
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
|
||||
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
|
||||
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
|
||||
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
|
||||
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
|
||||
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
|
||||
GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
|
||||
CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
|
||||
0),
|
||||
GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
|
||||
CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
|
||||
CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info apm_cmu_info __initconst = {
|
||||
.mux_clks = apm_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
|
||||
.div_clks = apm_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(apm_div_clks),
|
||||
.gate_clks = apm_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
|
||||
.fixed_clks = apm_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
|
||||
.nr_clk_ids = APM_NR_CLK,
|
||||
.clk_regs = apm_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
|
||||
.clk_name = "dout_clkcmu_apm_bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_CMGP ------------------------------------------------------------ */
|
||||
|
||||
/* Register Offset definitions for CMU_CMGP (0x11c00000) */
|
||||
#define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
|
||||
#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
|
||||
#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
|
||||
#define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
|
||||
#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
|
||||
#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
|
||||
#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
|
||||
#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
|
||||
#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
|
||||
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
|
||||
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
|
||||
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
|
||||
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
|
||||
|
||||
static const unsigned long cmgp_clk_regs[] __initconst = {
|
||||
CLK_CON_MUX_CLK_CMGP_ADC,
|
||||
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
|
||||
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
|
||||
CLK_CON_DIV_DIV_CLK_CMGP_ADC,
|
||||
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
|
||||
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
|
||||
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
|
||||
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
|
||||
CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
|
||||
CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
|
||||
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
|
||||
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
|
||||
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
|
||||
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_CMGP */
|
||||
PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
|
||||
PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
|
||||
PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
|
||||
|
||||
static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
|
||||
FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
|
||||
};
|
||||
|
||||
static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
|
||||
CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
|
||||
MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
|
||||
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
|
||||
MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
|
||||
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
|
||||
CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
|
||||
DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
|
||||
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
|
||||
DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
|
||||
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
|
||||
"gout_clkcmu_cmgp_bus",
|
||||
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
|
||||
"gout_clkcmu_cmgp_bus",
|
||||
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
|
||||
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
|
||||
GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
|
||||
"gout_clkcmu_cmgp_bus",
|
||||
CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
|
||||
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
|
||||
"gout_clkcmu_cmgp_bus",
|
||||
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
|
||||
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
|
||||
"gout_clkcmu_cmgp_bus",
|
||||
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
|
||||
"gout_clkcmu_cmgp_bus",
|
||||
CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
|
||||
.mux_clks = cmgp_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
|
||||
.div_clks = cmgp_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
|
||||
.gate_clks = cmgp_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
|
||||
.fixed_clks = cmgp_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
|
||||
.nr_clk_ids = CMGP_NR_CLK,
|
||||
.clk_regs = cmgp_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
|
||||
.clk_name = "gout_clkcmu_cmgp_bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_HSI ------------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_HSI (0x13400000) */
|
||||
|
|
@ -413,8 +625,9 @@ static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
|
|||
CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
|
||||
GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
|
||||
CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
|
||||
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
|
||||
GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
|
||||
CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, 0, 0),
|
||||
CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
|
||||
CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
|
||||
|
|
@ -597,9 +810,10 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
|
|||
CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
|
||||
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
|
||||
GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
|
||||
"mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, 0, 0),
|
||||
CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peri_cmu_info __initconst = {
|
||||
|
|
@ -615,6 +829,15 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
|
|||
.clk_name = "dout_peri_bus",
|
||||
};
|
||||
|
||||
static void __init exynos850_cmu_peri_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_PERI early, as it's needed for MCT timer */
|
||||
CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
|
||||
exynos850_cmu_peri_init);
|
||||
|
||||
/* ---- CMU_CORE ------------------------------------------------------------ */
|
||||
|
||||
/* Register Offset definitions for CMU_CORE (0x12000000) */
|
||||
|
|
@ -626,10 +849,12 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
|
|||
#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
|
||||
#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
|
||||
#define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
|
||||
#define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
|
||||
#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
|
||||
#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
|
||||
#define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
|
||||
#define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
|
||||
#define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
|
||||
|
||||
static const unsigned long core_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
|
||||
|
|
@ -640,10 +865,12 @@ static const unsigned long core_clk_regs[] __initconst = {
|
|||
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
|
||||
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
|
||||
CLK_CON_GAT_GOUT_CORE_GIC_CLK,
|
||||
CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
|
||||
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
|
||||
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
|
||||
CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
|
||||
CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
|
||||
CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_CORE */
|
||||
|
|
@ -673,10 +900,12 @@ static const struct samsung_div_clock core_div_clks[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct samsung_gate_clock core_gate_clks[] __initconst = {
|
||||
/* CCI (interconnect) clock must be always running */
|
||||
GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
|
||||
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, 0, 0),
|
||||
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
|
||||
/* GIC (interrupt controller) clock must be always running */
|
||||
GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
|
||||
CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, 0, 0),
|
||||
CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
|
||||
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
|
||||
|
|
@ -686,6 +915,12 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = {
|
|||
CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
|
||||
CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
|
||||
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
|
||||
GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
|
||||
CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
|
||||
"dout_core_busp",
|
||||
CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info core_cmu_info __initconst = {
|
||||
|
|
@ -742,8 +977,10 @@ static const struct samsung_div_clock dpu_div_clks[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
|
||||
/* TODO: Should be enabled in DSIM driver */
|
||||
GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
|
||||
"dout_dpu_busp", CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, 0, 0),
|
||||
"dout_dpu_busp",
|
||||
CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
|
||||
CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
|
||||
GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
|
||||
|
|
@ -779,36 +1016,23 @@ static int __init exynos850_cmu_probe(struct platform_device *pdev)
|
|||
{
|
||||
const struct samsung_cmu_info *info;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
|
||||
info = of_device_get_match_data(dev);
|
||||
exynos850_init_clocks(np, info->clk_regs, info->nr_clk_regs);
|
||||
samsung_cmu_register_one(np, info);
|
||||
|
||||
/* Keep bus clock running, so it's possible to access CMU registers */
|
||||
if (info->clk_name) {
|
||||
struct clk *bus_clk;
|
||||
|
||||
bus_clk = clk_get(dev, info->clk_name);
|
||||
if (IS_ERR(bus_clk)) {
|
||||
pr_err("%s: could not find bus clock %s; err = %ld\n",
|
||||
__func__, info->clk_name, PTR_ERR(bus_clk));
|
||||
} else {
|
||||
clk_prepare_enable(bus_clk);
|
||||
}
|
||||
}
|
||||
exynos_arm64_register_cmu(dev, dev->of_node, info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* CMUs which belong to Power Domains and need runtime PM to be implemented */
|
||||
static const struct of_device_id exynos850_cmu_of_match[] = {
|
||||
{
|
||||
.compatible = "samsung,exynos850-cmu-apm",
|
||||
.data = &apm_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynos850-cmu-cmgp",
|
||||
.data = &cmgp_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynos850-cmu-hsi",
|
||||
.data = &hsi_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynos850-cmu-peri",
|
||||
.data = &peri_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynos850-cmu-core",
|
||||
.data = &core_cmu_info,
|
||||
|
|
|
|||
|
|
@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
|||
else
|
||||
init.ops = &samsung_pll35xx_clk_ops;
|
||||
break;
|
||||
case pll_1417x:
|
||||
case pll_0822x:
|
||||
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
|
||||
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ enum samsung_pll_type {
|
|||
pll_2550xx,
|
||||
pll_2650x,
|
||||
pll_2650xx,
|
||||
pll_1417x,
|
||||
pll_1450x,
|
||||
pll_1451x,
|
||||
pll_1452x,
|
||||
|
|
|
|||
|
|
@ -323,6 +323,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
|
|||
void __iomem *base)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
reg_base = base;
|
||||
|
||||
if (np) {
|
||||
|
|
@ -332,13 +333,14 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
|
|||
}
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
/* Register external clocks only in non-dt cases */
|
||||
if (!np)
|
||||
s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
|
||||
|
||||
if (current_soc == S3C2410) {
|
||||
if (_get_rate("xti") == 12 * MHZ) {
|
||||
if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
|
||||
s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
|
||||
s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
|
||||
}
|
||||
|
|
@ -348,7 +350,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
|
|||
ARRAY_SIZE(s3c2410_plls), reg_base);
|
||||
|
||||
} else { /* S3C2440, S3C2442 */
|
||||
if (_get_rate("xti") == 12 * MHZ) {
|
||||
if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
|
||||
/*
|
||||
* plls follow different calculation schemes, with the
|
||||
* upll following the same scheme as the s3c2410 plls
|
||||
|
|
|
|||
|
|
@ -394,6 +394,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
|||
void __iomem *base)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
|
||||
reg_base = base;
|
||||
is_s3c6400 = s3c6400;
|
||||
|
|
@ -405,6 +406,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
|||
}
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
/* Register external clocks. */
|
||||
if (!np)
|
||||
|
|
@ -459,8 +461,10 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
|||
pr_info("%s clocks: apll = %lu, mpll = %lu\n"
|
||||
"\tepll = %lu, arm_clk = %lu\n",
|
||||
is_s3c6400 ? "S3C6400" : "S3C6410",
|
||||
_get_rate("fout_apll"), _get_rate("fout_mpll"),
|
||||
_get_rate("fout_epll"), _get_rate("armclk"));
|
||||
clk_hw_get_rate(hws[MOUT_APLL]),
|
||||
clk_hw_get_rate(hws[MOUT_MPLL]),
|
||||
clk_hw_get_rate(hws[MOUT_EPLL]),
|
||||
clk_hw_get_rate(hws[ARMCLK]));
|
||||
}
|
||||
|
||||
static void __init s3c6400_clk_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -741,8 +741,10 @@ static void __init __s5pv210_clk_init(struct device_node *np,
|
|||
bool is_s5p6442)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
samsung_clk_register_mux(ctx, early_mux_clks,
|
||||
ARRAY_SIZE(early_mux_clks));
|
||||
|
|
@ -789,8 +791,10 @@ static void __init __s5pv210_clk_init(struct device_node *np,
|
|||
pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
|
||||
"\tmout_epll = %ld, mout_vpll = %ld\n",
|
||||
is_s5p6442 ? "S5P6442" : "S5PV210",
|
||||
_get_rate("mout_apll"), _get_rate("mout_mpll"),
|
||||
_get_rate("mout_epll"), _get_rate("mout_vpll"));
|
||||
clk_hw_get_rate(hws[MOUT_APLL]),
|
||||
clk_hw_get_rate(hws[MOUT_MPLL]),
|
||||
clk_hw_get_rate(hws[MOUT_EPLL]),
|
||||
clk_hw_get_rate(hws[MOUT_VPLL]));
|
||||
}
|
||||
|
||||
static void __init s5pv210_clk_dt_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -268,20 +268,6 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
|
|||
samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
|
||||
}
|
||||
|
||||
/* utility function to get the rate of a specified clock */
|
||||
unsigned long _get_rate(const char *clk_name)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = __clk_lookup(clk_name);
|
||||
if (!clk) {
|
||||
pr_err("%s: could not find clock %s\n", __func__, clk_name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return clk_get_rate(clk);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int samsung_clk_suspend(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -337,54 +337,52 @@ struct samsung_cmu_info {
|
|||
const char *clk_name;
|
||||
};
|
||||
|
||||
extern struct samsung_clk_provider *__init samsung_clk_init(
|
||||
struct samsung_clk_provider * samsung_clk_init(
|
||||
struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks);
|
||||
extern void __init samsung_clk_of_add_provider(struct device_node *np,
|
||||
void samsung_clk_of_add_provider(struct device_node *np,
|
||||
struct samsung_clk_provider *ctx);
|
||||
extern void __init samsung_clk_of_register_fixed_ext(
|
||||
void samsung_clk_of_register_fixed_ext(
|
||||
struct samsung_clk_provider *ctx,
|
||||
struct samsung_fixed_rate_clock *fixed_rate_clk,
|
||||
unsigned int nr_fixed_rate_clk,
|
||||
const struct of_device_id *clk_matches);
|
||||
|
||||
extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
|
||||
void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
|
||||
struct clk_hw *clk_hw, unsigned int id);
|
||||
|
||||
extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
|
||||
void samsung_clk_register_alias(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_clock_alias *list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_fixed_rate(
|
||||
void samsung_clk_register_fixed_rate(
|
||||
struct samsung_clk_provider *ctx,
|
||||
const struct samsung_fixed_rate_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_fixed_factor(
|
||||
void samsung_clk_register_fixed_factor(
|
||||
struct samsung_clk_provider *ctx,
|
||||
const struct samsung_fixed_factor_clock *list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
|
||||
void samsung_clk_register_mux(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_mux_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
|
||||
void samsung_clk_register_div(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_div_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
|
||||
void samsung_clk_register_gate(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_gate_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
void samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_pll_clock *pll_list,
|
||||
unsigned int nr_clk, void __iomem *base);
|
||||
extern void samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
|
||||
void samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_cpu_clock *list, unsigned int nr_clk);
|
||||
|
||||
extern struct samsung_clk_provider __init *samsung_cmu_register_one(
|
||||
struct samsung_clk_provider *samsung_cmu_register_one(
|
||||
struct device_node *,
|
||||
const struct samsung_cmu_info *);
|
||||
|
||||
extern unsigned long _get_rate(const char *clk_name);
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
extern void samsung_clk_extended_sleep_init(void __iomem *reg_base,
|
||||
void samsung_clk_extended_sleep_init(void __iomem *reg_base,
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump,
|
||||
const struct samsung_clk_reg_dump *rsuspend,
|
||||
|
|
@ -399,13 +397,13 @@ static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base,
|
|||
#define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \
|
||||
samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0)
|
||||
|
||||
extern void samsung_clk_save(void __iomem *base,
|
||||
void samsung_clk_save(void __iomem *base,
|
||||
struct samsung_clk_reg_dump *rd,
|
||||
unsigned int num_regs);
|
||||
extern void samsung_clk_restore(void __iomem *base,
|
||||
void samsung_clk_restore(void __iomem *base,
|
||||
const struct samsung_clk_reg_dump *rd,
|
||||
unsigned int num_regs);
|
||||
extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
|
||||
struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump);
|
||||
|
||||
|
|
|
|||
|
|
@ -209,6 +209,7 @@
|
|||
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
|
||||
#define CLK_MOUT_HDMI 396
|
||||
#define CLK_MOUT_MIXER 397
|
||||
#define CLK_MOUT_VPLLSRC 398
|
||||
|
||||
/* gate clocks - ppmu */
|
||||
#define CLK_PPMULEFT 400
|
||||
|
|
@ -236,9 +237,10 @@
|
|||
#define CLK_DIV_C2C 458 /* Exynos4x12 only */
|
||||
#define CLK_DIV_GDL 459
|
||||
#define CLK_DIV_GDR 460
|
||||
#define CLK_DIV_CORE2 461
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 461
|
||||
#define CLK_NR_CLKS 462
|
||||
|
||||
/* Exynos4x12 ISP clocks */
|
||||
#define CLK_ISP_FIMC_ISP 1
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#define CLK_FOUT_EPLL 7
|
||||
#define CLK_FOUT_VPLL 8
|
||||
#define CLK_ARM_CLK 9
|
||||
#define CLK_DIV_ARM2 10
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
#define CLK_SCLK_CAM_BAYER 128
|
||||
|
|
@ -174,8 +175,9 @@
|
|||
#define CLK_MOUT_ACLK300_DISP1_SUB 1027
|
||||
#define CLK_MOUT_APLL 1028
|
||||
#define CLK_MOUT_MPLL 1029
|
||||
#define CLK_MOUT_VPLLSRC 1030
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 1030
|
||||
#define CLK_NR_CLKS 1031
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,115 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021 Dávid Virág
|
||||
*
|
||||
* Device Tree binding constants for Exynos7885 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_FOUT_SHARED1_PLL 2
|
||||
#define CLK_DOUT_SHARED0_DIV2 3
|
||||
#define CLK_DOUT_SHARED0_DIV3 4
|
||||
#define CLK_DOUT_SHARED0_DIV4 5
|
||||
#define CLK_DOUT_SHARED0_DIV5 6
|
||||
#define CLK_DOUT_SHARED1_DIV2 7
|
||||
#define CLK_DOUT_SHARED1_DIV3 8
|
||||
#define CLK_DOUT_SHARED1_DIV4 9
|
||||
#define CLK_MOUT_CORE_BUS 10
|
||||
#define CLK_MOUT_CORE_CCI 11
|
||||
#define CLK_MOUT_CORE_G3D 12
|
||||
#define CLK_DOUT_CORE_BUS 13
|
||||
#define CLK_DOUT_CORE_CCI 14
|
||||
#define CLK_DOUT_CORE_G3D 15
|
||||
#define CLK_GOUT_CORE_BUS 16
|
||||
#define CLK_GOUT_CORE_CCI 17
|
||||
#define CLK_GOUT_CORE_G3D 18
|
||||
#define CLK_MOUT_PERI_BUS 19
|
||||
#define CLK_MOUT_PERI_SPI0 20
|
||||
#define CLK_MOUT_PERI_SPI1 21
|
||||
#define CLK_MOUT_PERI_UART0 22
|
||||
#define CLK_MOUT_PERI_UART1 23
|
||||
#define CLK_MOUT_PERI_UART2 24
|
||||
#define CLK_MOUT_PERI_USI0 25
|
||||
#define CLK_MOUT_PERI_USI1 26
|
||||
#define CLK_MOUT_PERI_USI2 27
|
||||
#define CLK_DOUT_PERI_BUS 28
|
||||
#define CLK_DOUT_PERI_SPI0 29
|
||||
#define CLK_DOUT_PERI_SPI1 30
|
||||
#define CLK_DOUT_PERI_UART0 31
|
||||
#define CLK_DOUT_PERI_UART1 32
|
||||
#define CLK_DOUT_PERI_UART2 33
|
||||
#define CLK_DOUT_PERI_USI0 34
|
||||
#define CLK_DOUT_PERI_USI1 35
|
||||
#define CLK_DOUT_PERI_USI2 36
|
||||
#define CLK_GOUT_PERI_BUS 37
|
||||
#define CLK_GOUT_PERI_SPI0 38
|
||||
#define CLK_GOUT_PERI_SPI1 39
|
||||
#define CLK_GOUT_PERI_UART0 40
|
||||
#define CLK_GOUT_PERI_UART1 41
|
||||
#define CLK_GOUT_PERI_UART2 42
|
||||
#define CLK_GOUT_PERI_USI0 43
|
||||
#define CLK_GOUT_PERI_USI1 44
|
||||
#define CLK_GOUT_PERI_USI2 45
|
||||
#define TOP_NR_CLK 46
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
#define CLK_MOUT_CORE_CCI_USER 2
|
||||
#define CLK_MOUT_CORE_G3D_USER 3
|
||||
#define CLK_MOUT_CORE_GIC 4
|
||||
#define CLK_DOUT_CORE_BUSP 5
|
||||
#define CLK_GOUT_CCI_ACLK 6
|
||||
#define CLK_GOUT_GIC400_CLK 7
|
||||
#define CORE_NR_CLK 8
|
||||
|
||||
/* CMU_PERI */
|
||||
#define CLK_MOUT_PERI_BUS_USER 1
|
||||
#define CLK_MOUT_PERI_SPI0_USER 2
|
||||
#define CLK_MOUT_PERI_SPI1_USER 3
|
||||
#define CLK_MOUT_PERI_UART0_USER 4
|
||||
#define CLK_MOUT_PERI_UART1_USER 5
|
||||
#define CLK_MOUT_PERI_UART2_USER 6
|
||||
#define CLK_MOUT_PERI_USI0_USER 7
|
||||
#define CLK_MOUT_PERI_USI1_USER 8
|
||||
#define CLK_MOUT_PERI_USI2_USER 9
|
||||
#define CLK_GOUT_GPIO_TOP_PCLK 10
|
||||
#define CLK_GOUT_HSI2C0_PCLK 11
|
||||
#define CLK_GOUT_HSI2C1_PCLK 12
|
||||
#define CLK_GOUT_HSI2C2_PCLK 13
|
||||
#define CLK_GOUT_HSI2C3_PCLK 14
|
||||
#define CLK_GOUT_I2C0_PCLK 15
|
||||
#define CLK_GOUT_I2C1_PCLK 16
|
||||
#define CLK_GOUT_I2C2_PCLK 17
|
||||
#define CLK_GOUT_I2C3_PCLK 18
|
||||
#define CLK_GOUT_I2C4_PCLK 19
|
||||
#define CLK_GOUT_I2C5_PCLK 20
|
||||
#define CLK_GOUT_I2C6_PCLK 21
|
||||
#define CLK_GOUT_I2C7_PCLK 22
|
||||
#define CLK_GOUT_PWM_MOTOR_PCLK 23
|
||||
#define CLK_GOUT_SPI0_PCLK 24
|
||||
#define CLK_GOUT_SPI0_EXT_CLK 25
|
||||
#define CLK_GOUT_SPI1_PCLK 26
|
||||
#define CLK_GOUT_SPI1_EXT_CLK 27
|
||||
#define CLK_GOUT_UART0_EXT_UCLK 28
|
||||
#define CLK_GOUT_UART0_PCLK 29
|
||||
#define CLK_GOUT_UART1_EXT_UCLK 30
|
||||
#define CLK_GOUT_UART1_PCLK 31
|
||||
#define CLK_GOUT_UART2_EXT_UCLK 32
|
||||
#define CLK_GOUT_UART2_PCLK 33
|
||||
#define CLK_GOUT_USI0_PCLK 34
|
||||
#define CLK_GOUT_USI0_SCLK 35
|
||||
#define CLK_GOUT_USI1_PCLK 36
|
||||
#define CLK_GOUT_USI1_SCLK 37
|
||||
#define CLK_GOUT_USI2_PCLK 38
|
||||
#define CLK_GOUT_USI2_SCLK 39
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||||
#define CLK_GOUT_MCT_PCLK 40
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||||
#define CLK_GOUT_SYSREG_PERI_PCLK 41
|
||||
#define CLK_GOUT_WDT0_PCLK 42
|
||||
#define CLK_GOUT_WDT1_PCLK 43
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||||
#define PERI_NR_CLK 44
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||||
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||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
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||||
|
|
@ -55,7 +55,55 @@
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|||
#define CLK_GOUT_PERI_BUS 43
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||||
#define CLK_GOUT_PERI_UART 44
|
||||
#define CLK_GOUT_PERI_IP 45
|
||||
#define TOP_NR_CLK 46
|
||||
#define CLK_MOUT_CLKCMU_APM_BUS 46
|
||||
#define CLK_DOUT_CLKCMU_APM_BUS 47
|
||||
#define CLK_GOUT_CLKCMU_APM_BUS 48
|
||||
#define TOP_NR_CLK 49
|
||||
|
||||
/* CMU_APM */
|
||||
#define CLK_RCO_I3C_PMIC 1
|
||||
#define OSCCLK_RCO_APM 2
|
||||
#define CLK_RCO_APM__ALV 3
|
||||
#define CLK_DLL_DCO 4
|
||||
#define CLK_MOUT_APM_BUS_USER 5
|
||||
#define CLK_MOUT_RCO_APM_I3C_USER 6
|
||||
#define CLK_MOUT_RCO_APM_USER 7
|
||||
#define CLK_MOUT_DLL_USER 8
|
||||
#define CLK_MOUT_CLKCMU_CHUB_BUS 9
|
||||
#define CLK_MOUT_APM_BUS 10
|
||||
#define CLK_MOUT_APM_I3C 11
|
||||
#define CLK_DOUT_CLKCMU_CHUB_BUS 12
|
||||
#define CLK_DOUT_APM_BUS 13
|
||||
#define CLK_DOUT_APM_I3C 14
|
||||
#define CLK_GOUT_CLKCMU_CMGP_BUS 15
|
||||
#define CLK_GOUT_CLKCMU_CHUB_BUS 16
|
||||
#define CLK_GOUT_RTC_PCLK 17
|
||||
#define CLK_GOUT_TOP_RTC_PCLK 18
|
||||
#define CLK_GOUT_I3C_PCLK 19
|
||||
#define CLK_GOUT_I3C_SCLK 20
|
||||
#define CLK_GOUT_SPEEDY_PCLK 21
|
||||
#define CLK_GOUT_GPIO_ALIVE_PCLK 22
|
||||
#define CLK_GOUT_PMU_ALIVE_PCLK 23
|
||||
#define CLK_GOUT_SYSREG_APM_PCLK 24
|
||||
#define APM_NR_CLK 25
|
||||
|
||||
/* CMU_CMGP */
|
||||
#define CLK_RCO_CMGP 1
|
||||
#define CLK_MOUT_CMGP_ADC 2
|
||||
#define CLK_MOUT_CMGP_USI0 3
|
||||
#define CLK_MOUT_CMGP_USI1 4
|
||||
#define CLK_DOUT_CMGP_ADC 5
|
||||
#define CLK_DOUT_CMGP_USI0 6
|
||||
#define CLK_DOUT_CMGP_USI1 7
|
||||
#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
|
||||
#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
|
||||
#define CLK_GOUT_CMGP_GPIO_PCLK 10
|
||||
#define CLK_GOUT_CMGP_USI0_IPCLK 11
|
||||
#define CLK_GOUT_CMGP_USI0_PCLK 12
|
||||
#define CLK_GOUT_CMGP_USI1_IPCLK 13
|
||||
#define CLK_GOUT_CMGP_USI1_PCLK 14
|
||||
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
|
||||
#define CMGP_NR_CLK 16
|
||||
|
||||
/* CMU_HSI */
|
||||
#define CLK_MOUT_HSI_BUS_USER 1
|
||||
|
|
@ -123,7 +171,9 @@
|
|||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 10
|
||||
#define CLK_GOUT_SSS_ACLK 11
|
||||
#define CLK_GOUT_SSS_PCLK 12
|
||||
#define CORE_NR_CLK 13
|
||||
#define CLK_GOUT_GPIO_CORE_PCLK 13
|
||||
#define CLK_GOUT_SYSREG_CORE_PCLK 14
|
||||
#define CORE_NR_CLK 15
|
||||
|
||||
/* CMU_DPU */
|
||||
#define CLK_MOUT_DPU_USER 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue