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drm/amd/powerplay: implement fw image related smum interface for tonga. 

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2016-08-11 11:01:01 +08:00 committed by Alex Deucher
parent b859c20703
commit 1486022088
6 changed files with 3329 additions and 3 deletions
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2
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
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@ -800,7 +800,7 @@ static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
if (0 == result) {
data->soft_regs_start = tmp;
tonga_smu->ulSoftRegsStart = tmp;
tonga_smu->soft_regs_start = tmp;
}
error |= (0 != result);

2
drivers/gpu/drm/amd/powerplay/smumgr/Makefile
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@ -3,7 +3,7 @@
# It provides the smu management services for the driver.
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o\
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))

3214
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c Normal file
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File diff suppressed because it is too large Load Diff

60
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h Normal file
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@ -0,0 +1,60 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _TONGA_SMC_H
#define _TONGA_SMC_H
#include "smumgr.h"
#include "smu72.h"
#define ASICID_IS_TONGA_P(wDID, bRID) \
(((wDID == 0x6930) && ((bRID == 0xF0) || (bRID == 0xF1) || (bRID == 0xFF))) \
|| ((wDID == 0x6920) && ((bRID == 0) || (bRID == 1))))
struct tonga_pt_defaults {
uint8_t svi_load_line_en;
uint8_t svi_load_line_vddC;
uint8_t tdc_vddc_throttle_release_limit_perc;
uint8_t tdc_mawt;
uint8_t tdc_waterfall_ctl;
uint8_t dte_ambient_temp_base;
uint32_t display_cac;
uint32_t bamp_temp_gradient;
uint16_t bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
uint16_t bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
};
int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
int tonga_init_smc_table(struct pp_hwmgr *hwmgr);
int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr);
uint32_t tonga_get_offsetof(uint32_t type, uint32_t member);
uint32_t tonga_get_mac_definition(uint32_t value);
int tonga_process_firmware_header(struct pp_hwmgr *hwmgr);
int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr);
#endif

17
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
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@ -33,6 +33,7 @@
#include "smu/smu_7_1_2_d.h"
#include "smu/smu_7_1_2_sh_mask.h"
#include "cgs_common.h"
#include "tonga_smc.h"
#define TONGA_SMC_SIZE 0x20000
#define BUFFER_SIZE 80000
@ -749,6 +750,8 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
struct tonga_smumgr *tonga_smu;
uint8_t *internal_buf;
uint64_t mc_addr = 0;
int i;
/* Allocate memory for backend private data */
tonga_smu = (struct tonga_smumgr *)(smumgr->backend);
tonga_smu->header_buffer.data_size =
@ -793,6 +796,9 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
(cgs_handle_t)tonga_smu->smu_buffer.handle);
return -1;);
for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
tonga_smu->activity_target[i] = 30;
return 0;
}
@ -807,6 +813,17 @@ static const struct pp_smumgr_func tonga_smu_funcs = {
.send_msg_to_smc_with_parameter = &tonga_send_msg_to_smc_with_parameter,
.download_pptable_settings = NULL,
.upload_pptable_settings = NULL,
.update_smc_table = tonga_update_smc_table,
.get_offsetof = tonga_get_offsetof,
.process_firmware_header = tonga_process_firmware_header,
.init_smc_table = tonga_init_smc_table,
.update_sclk_threshold = tonga_update_sclk_threshold,
.thermal_setup_fan_table = tonga_thermal_setup_fan_table,
.populate_all_graphic_levels = tonga_populate_all_graphic_levels,
.populate_all_memory_levels = tonga_populate_all_memory_levels,
.get_mac_definition = tonga_get_mac_definition,
.initialize_mc_reg_table = tonga_initialize_mc_reg_table,
.is_dpm_running = tonga_is_dpm_running,
};
int tonga_smum_init(struct pp_smumgr *smumgr)

37
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
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@ -24,6 +24,10 @@
#ifndef _TONGA_SMUMGR_H_
#define _TONGA_SMUMGR_H_
#include "smu72_discrete.h"
#define SMC_RAM_END 0x40000
struct tonga_buffer_entry {
uint32_t data_size;
uint32_t mc_addr_low;
@ -32,13 +36,44 @@ struct tonga_buffer_entry {
unsigned long handle;
};
struct tonga_mc_reg_entry {
uint32_t mclk_max;
uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
struct tonga_mc_reg_table {
uint8_t last; /* number of registers*/
uint8_t num_entries; /* number of entries in mc_reg_table_entry used*/
uint16_t validflag; /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
struct tonga_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
struct tonga_smumgr {
uint8_t *pHeader;
uint8_t *pMecImage;
uint32_t ulSoftRegsStart;
uint32_t soft_regs_start;
uint32_t dpm_table_start;
uint32_t mc_reg_table_start;
uint32_t fan_table_start;
uint32_t arb_table_start;
struct tonga_buffer_entry header_buffer;
struct tonga_buffer_entry smu_buffer;
struct SMU72_Discrete_DpmTable smc_state_table;
struct SMU72_Discrete_Ulv ulv_setting;
struct SMU72_Discrete_PmFuses power_tune_table;
struct tonga_pt_defaults *power_tune_defaults;
SMU72_Discrete_MCRegisters mc_regs;
struct tonga_mc_reg_table mc_reg_table;
uint32_t activity_target[SMU72_MAX_LEVELS_GRAPHICS];
};
extern int tonga_smum_init(struct pp_smumgr *smumgr);