scsi: ncr5380: Reduce #include files
The NCR5380 wrapper drivers don't export symbols or declarations and don't actually need separate header files. Most of these header files were removed already; only sun3_scsi.h and g_NCR5380.h remain. Move the remaining definitions to the corresponding .c files to improve readability and proximity. The #defines which influence the #included core driver are no longer mixed up with unrelated #defines and #includes. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Tested-by: Ondrej Zary <linux@rainbow-software.org> Tested-by: Michael Schmitz <schmitzmic@gmail.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Finn Thain
Martin K. Petersen
parent
9507037304
commit
14d739f640
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@ -26,14 +26,55 @@
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#include <linux/blkdev.h>
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#include <linux/module.h>
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#include <scsi/scsi_host.h>
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#include "g_NCR5380.h"
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#include "NCR5380.h"
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/isa.h>
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#include <linux/pnp.h>
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#include <linux/interrupt.h>
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/* Definitions for the core NCR5380 driver. */
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#define NCR5380_read(reg) \
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ioread8(hostdata->io + hostdata->offset + (reg))
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#define NCR5380_write(reg, value) \
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iowrite8(value, hostdata->io + hostdata->offset + (reg))
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#define NCR5380_implementation_fields \
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int offset; \
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int c400_ctl_status; \
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int c400_blk_cnt; \
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int c400_host_buf; \
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int io_width
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#define NCR5380_dma_xfer_len generic_NCR5380_dma_xfer_len
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#define NCR5380_dma_recv_setup generic_NCR5380_pread
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#define NCR5380_dma_send_setup generic_NCR5380_pwrite
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#define NCR5380_dma_residual NCR5380_dma_residual_none
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#define NCR5380_intr generic_NCR5380_intr
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#define NCR5380_queue_command generic_NCR5380_queue_command
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#define NCR5380_abort generic_NCR5380_abort
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#define NCR5380_bus_reset generic_NCR5380_bus_reset
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#define NCR5380_info generic_NCR5380_info
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#define NCR5380_io_delay(x) udelay(x)
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#include "NCR5380.h"
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#define DRV_MODULE_NAME "g_NCR5380"
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#define NCR53C400_mem_base 0x3880
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#define NCR53C400_host_buffer 0x3900
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#define NCR53C400_region_size 0x3a00
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#define BOARD_NCR5380 0
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#define BOARD_NCR53C400 1
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#define BOARD_NCR53C400A 2
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#define BOARD_DTC3181E 3
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#define BOARD_HP_C2502 4
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#define IRQ_AUTO 254
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#define MAX_CARDS 8
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/* old-style parameters for compatibility */
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@ -1,56 +0,0 @@
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/*
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* Generic Generic NCR5380 driver defines
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*
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix and Linux consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 440-4894
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*
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* NCR53C400 extensions (c) 1994,1995,1996, Kevin Lentin
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* K.Lentin@cs.monash.edu.au
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*/
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#ifndef GENERIC_NCR5380_H
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#define GENERIC_NCR5380_H
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#define DRV_MODULE_NAME "g_NCR5380"
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#define NCR5380_read(reg) \
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ioread8(hostdata->io + hostdata->offset + (reg))
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#define NCR5380_write(reg, value) \
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iowrite8(value, hostdata->io + hostdata->offset + (reg))
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#define NCR5380_implementation_fields \
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int offset; \
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int c400_ctl_status; \
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int c400_blk_cnt; \
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int c400_host_buf; \
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int io_width;
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#define NCR53C400_mem_base 0x3880
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#define NCR53C400_host_buffer 0x3900
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#define NCR53C400_region_size 0x3a00
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#define NCR5380_dma_xfer_len generic_NCR5380_dma_xfer_len
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#define NCR5380_dma_recv_setup generic_NCR5380_pread
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#define NCR5380_dma_send_setup generic_NCR5380_pwrite
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#define NCR5380_dma_residual NCR5380_dma_residual_none
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#define NCR5380_intr generic_NCR5380_intr
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#define NCR5380_queue_command generic_NCR5380_queue_command
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#define NCR5380_abort generic_NCR5380_abort
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#define NCR5380_bus_reset generic_NCR5380_bus_reset
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#define NCR5380_info generic_NCR5380_info
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#define NCR5380_io_delay(x) udelay(x)
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#define BOARD_NCR5380 0
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#define BOARD_NCR53C400 1
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#define BOARD_NCR53C400A 2
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#define BOARD_DTC3181E 3
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#define BOARD_HP_C2502 4
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#define IRQ_AUTO 254
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#endif /* GENERIC_NCR5380_H */
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@ -34,7 +34,6 @@
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#include <asm/dvma.h>
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#include <scsi/scsi_host.h>
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#include "sun3_scsi.h"
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/* minimum number of bytes to do dma on */
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#define DMA_MIN_SIZE 129
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@ -58,6 +57,85 @@
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#include "NCR5380.h"
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/* dma regs start at regbase + 8, directly after the NCR regs */
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struct sun3_dma_regs {
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unsigned short dma_addr_hi; /* vme only */
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unsigned short dma_addr_lo; /* vme only */
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unsigned short dma_count_hi; /* vme only */
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unsigned short dma_count_lo; /* vme only */
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unsigned short udc_data; /* udc dma data reg (obio only) */
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unsigned short udc_addr; /* uda dma addr reg (obio only) */
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unsigned short fifo_data; /* fifo data reg,
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* holds extra byte on odd dma reads
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*/
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unsigned short fifo_count;
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unsigned short csr; /* control/status reg */
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unsigned short bpack_hi; /* vme only */
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unsigned short bpack_lo; /* vme only */
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unsigned short ivect; /* vme only */
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unsigned short fifo_count_hi; /* vme only */
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};
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/* ucd chip specific regs - live in dvma space */
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struct sun3_udc_regs {
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unsigned short rsel; /* select regs to load */
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unsigned short addr_hi; /* high word of addr */
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unsigned short addr_lo; /* low word */
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unsigned short count; /* words to be xfer'd */
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unsigned short mode_hi; /* high word of channel mode */
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unsigned short mode_lo; /* low word of channel mode */
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};
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/* addresses of the udc registers */
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#define UDC_MODE 0x38
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#define UDC_CSR 0x2e /* command/status */
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#define UDC_CHN_HI 0x26 /* chain high word */
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#define UDC_CHN_LO 0x22 /* chain lo word */
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#define UDC_CURA_HI 0x1a /* cur reg A high */
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#define UDC_CURA_LO 0x0a /* cur reg A low */
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#define UDC_CURB_HI 0x12 /* cur reg B high */
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#define UDC_CURB_LO 0x02 /* cur reg B low */
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#define UDC_MODE_HI 0x56 /* mode reg high */
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#define UDC_MODE_LO 0x52 /* mode reg low */
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#define UDC_COUNT 0x32 /* words to xfer */
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/* some udc commands */
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#define UDC_RESET 0
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#define UDC_CHN_START 0xa0 /* start chain */
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#define UDC_INT_ENABLE 0x32 /* channel 1 int on */
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/* udc mode words */
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#define UDC_MODE_HIWORD 0x40
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#define UDC_MODE_LSEND 0xc2
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#define UDC_MODE_LRECV 0xd2
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/* udc reg selections */
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#define UDC_RSEL_SEND 0x282
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#define UDC_RSEL_RECV 0x182
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/* bits in csr reg */
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#define CSR_DMA_ACTIVE 0x8000
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#define CSR_DMA_CONFLICT 0x4000
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#define CSR_DMA_BUSERR 0x2000
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#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
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#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
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#define CSR_DMA_INT 0x100 /* dma interrupt pending */
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#define CSR_LEFT 0xc0
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#define CSR_LEFT_3 0xc0
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#define CSR_LEFT_2 0x80
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#define CSR_LEFT_1 0x40
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#define CSR_PACK_ENABLE 0x20
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#define CSR_DMA_ENABLE 0x10
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#define CSR_SEND 0x8 /* 1 = send 0 = recv */
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#define CSR_FIFO 0x2 /* reset fifo */
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#define CSR_INTR 0x4 /* interrupt enable */
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#define CSR_SCSI 0x1
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#define VME_DATA24 0x3d00
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extern int sun3_map_test(unsigned long, char *);
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@ -1,102 +0,0 @@
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/*
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* Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
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*
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* Sun3 DMA additions by Sam Creasey (sammy@sammy.net)
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*
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* Adapted from mac_scsinew.h:
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*/
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/*
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* Cumana Generic NCR5380 driver defines
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*
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix and Linux consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 440-4894
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*/
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#ifndef SUN3_SCSI_H
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#define SUN3_SCSI_H
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/* additional registers - mainly DMA control regs */
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/* these start at regbase + 8 -- directly after the NCR regs */
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struct sun3_dma_regs {
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unsigned short dma_addr_hi; /* vme only */
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unsigned short dma_addr_lo; /* vme only */
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unsigned short dma_count_hi; /* vme only */
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unsigned short dma_count_lo; /* vme only */
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unsigned short udc_data; /* udc dma data reg (obio only) */
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unsigned short udc_addr; /* uda dma addr reg (obio only) */
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unsigned short fifo_data; /* fifo data reg, holds extra byte on
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odd dma reads */
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unsigned short fifo_count;
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unsigned short csr; /* control/status reg */
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unsigned short bpack_hi; /* vme only */
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unsigned short bpack_lo; /* vme only */
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unsigned short ivect; /* vme only */
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unsigned short fifo_count_hi; /* vme only */
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};
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/* ucd chip specific regs - live in dvma space */
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struct sun3_udc_regs {
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unsigned short rsel; /* select regs to load */
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unsigned short addr_hi; /* high word of addr */
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unsigned short addr_lo; /* low word */
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unsigned short count; /* words to be xfer'd */
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unsigned short mode_hi; /* high word of channel mode */
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unsigned short mode_lo; /* low word of channel mode */
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};
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/* addresses of the udc registers */
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#define UDC_MODE 0x38
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#define UDC_CSR 0x2e /* command/status */
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#define UDC_CHN_HI 0x26 /* chain high word */
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#define UDC_CHN_LO 0x22 /* chain lo word */
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#define UDC_CURA_HI 0x1a /* cur reg A high */
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#define UDC_CURA_LO 0x0a /* cur reg A low */
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#define UDC_CURB_HI 0x12 /* cur reg B high */
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#define UDC_CURB_LO 0x02 /* cur reg B low */
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#define UDC_MODE_HI 0x56 /* mode reg high */
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#define UDC_MODE_LO 0x52 /* mode reg low */
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#define UDC_COUNT 0x32 /* words to xfer */
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/* some udc commands */
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#define UDC_RESET 0
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#define UDC_CHN_START 0xa0 /* start chain */
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#define UDC_INT_ENABLE 0x32 /* channel 1 int on */
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/* udc mode words */
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#define UDC_MODE_HIWORD 0x40
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#define UDC_MODE_LSEND 0xc2
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#define UDC_MODE_LRECV 0xd2
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/* udc reg selections */
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#define UDC_RSEL_SEND 0x282
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#define UDC_RSEL_RECV 0x182
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/* bits in csr reg */
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#define CSR_DMA_ACTIVE 0x8000
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#define CSR_DMA_CONFLICT 0x4000
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#define CSR_DMA_BUSERR 0x2000
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#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
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#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
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#define CSR_DMA_INT 0x100 /* dma interrupt pending */
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#define CSR_LEFT 0xc0
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#define CSR_LEFT_3 0xc0
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#define CSR_LEFT_2 0x80
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#define CSR_LEFT_1 0x40
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#define CSR_PACK_ENABLE 0x20
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#define CSR_DMA_ENABLE 0x10
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#define CSR_SEND 0x8 /* 1 = send 0 = recv */
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#define CSR_FIFO 0x2 /* reset fifo */
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#define CSR_INTR 0x4 /* interrupt enable */
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#define CSR_SCSI 0x1
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#define VME_DATA24 0x3d00
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#endif /* SUN3_SCSI_H */
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