MIPS: Octeon: Initialize CN68XX PKO
CN68XX requires a different PKO configuration. This patch provides just enough setup to get the XAUI interfaces on CN6880 working with default parameters. Signed-off-by: Janne Huttunen <janne.huttunen@nsn.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10974/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Janne Huttunen
Ralf Baechle
parent
f8023da8ae
commit
153bfe3813
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@ -39,6 +39,143 @@
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* Internal state of packet output
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*/
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static int __cvmx_pko_int(int interface, int index)
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{
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switch (interface) {
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case 0:
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return index;
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case 1:
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return 4;
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case 2:
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return index + 0x08;
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case 3:
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return index + 0x0c;
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case 4:
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return index + 0x10;
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case 5:
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return 0x1c;
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case 6:
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return 0x1d;
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case 7:
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return 0x1e;
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case 8:
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return 0x1f;
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default:
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return -1;
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}
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}
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static void __cvmx_pko_iport_config(int pko_port)
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{
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int queue;
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const int num_queues = 1;
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const int base_queue = pko_port;
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const int static_priority_end = 1;
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const int static_priority_base = 1;
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for (queue = 0; queue < num_queues; queue++) {
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union cvmx_pko_mem_iqueue_ptrs config;
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cvmx_cmd_queue_result_t cmd_res;
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uint64_t *buf_ptr;
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config.u64 = 0;
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config.s.index = queue;
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config.s.qid = base_queue + queue;
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config.s.ipid = pko_port;
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config.s.tail = (queue == (num_queues - 1));
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config.s.s_tail = (queue == static_priority_end);
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config.s.static_p = (static_priority_base >= 0);
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config.s.static_q = (queue <= static_priority_end);
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config.s.qos_mask = 0xff;
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cmd_res = cvmx_cmd_queue_initialize(
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CVMX_CMD_QUEUE_PKO(base_queue + queue),
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CVMX_PKO_MAX_QUEUE_DEPTH,
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CVMX_FPA_OUTPUT_BUFFER_POOL,
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(CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE -
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CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST * 8));
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WARN(cmd_res,
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"%s: cmd_res=%d pko_port=%d base_queue=%d num_queues=%d queue=%d\n",
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__func__, (int)cmd_res, pko_port, base_queue,
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num_queues, queue);
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buf_ptr = (uint64_t *)cvmx_cmd_queue_buffer(
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CVMX_CMD_QUEUE_PKO(base_queue + queue));
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config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr) >> 7;
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CVMX_SYNCWS;
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cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);
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}
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}
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static void __cvmx_pko_queue_alloc_o68(void)
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{
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int port;
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for (port = 0; port < 48; port++)
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__cvmx_pko_iport_config(port);
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}
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static void __cvmx_pko_port_map_o68(void)
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{
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int port;
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int interface, index;
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cvmx_helper_interface_mode_t mode;
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union cvmx_pko_mem_iport_ptrs config;
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/*
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* Initialize every iport with the invalid eid.
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*/
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config.u64 = 0;
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config.s.eid = 31; /* Invalid */
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for (port = 0; port < 128; port++) {
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config.s.ipid = port;
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cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
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}
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/*
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* Set up PKO_MEM_IPORT_PTRS
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*/
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for (port = 0; port < 48; port++) {
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interface = cvmx_helper_get_interface_num(port);
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index = cvmx_helper_get_interface_index_num(port);
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mode = cvmx_helper_interface_get_mode(interface);
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if (mode == CVMX_HELPER_INTERFACE_MODE_DISABLED)
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continue;
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config.s.ipid = port;
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config.s.qos_mask = 0xff;
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config.s.crc = 1;
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config.s.min_pkt = 1;
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config.s.intr = __cvmx_pko_int(interface, index);
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config.s.eid = config.s.intr;
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config.s.pipe = (mode == CVMX_HELPER_INTERFACE_MODE_LOOP) ?
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index : port;
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cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
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}
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}
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static void __cvmx_pko_chip_init(void)
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{
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int i;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
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__cvmx_pko_port_map_o68();
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__cvmx_pko_queue_alloc_o68();
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return;
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}
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/*
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* Initialize queues
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*/
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for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) {
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const uint64_t priority = 8;
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cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
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&priority);
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}
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}
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/**
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* Call before any other calls to initialize the packet
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* output system. This does chip global config, and should only be
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@ -47,8 +184,6 @@
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void cvmx_pko_initialize_global(void)
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{
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int i;
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uint64_t priority = 8;
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union cvmx_pko_reg_cmd_buf config;
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/*
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@ -62,9 +197,10 @@ void cvmx_pko_initialize_global(void)
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cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
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for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
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cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
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&priority);
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/*
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* Chip-specific setup.
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*/
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__cvmx_pko_chip_init();
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/*
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* If we aren't using all of the queues optimize PKO's
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@ -212,6 +348,9 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
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int static_priority_base = -1;
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int static_priority_end = -1;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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return CVMX_PKO_SUCCESS;
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if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS)
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&& (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) {
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n",
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