- New driver: Armada 37xx mailbox controller
- Misc: Use devm_ api for imx and platform_get_irq for stm32 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6EwehDt/SOnwFyTyf9lkf8eYP5UFAlzTv38ACgkQf9lkf8eY P5VOQQ//d2rKhGB1GjVZQlezRa+AOLWr69cbN4mcxUvXp+PJmrcnqn1Ld7QzPXCl /Xc/2+KxtZ5WX7vtmGu45eSFiCqf2apXfDaQf89ZrtCbUKT1GBJRUvvBeCmFv4pZ bnA0PTCsHkpdvttmM2W++ZHFmgVxKOTQmtTZFsmwohJNfALkoQaw9NgKUuBKzPdI DutmXNBLXm+EkEjuIjvsKdgE63g49BTio9BRzX85+PKYmRohOa5xb05pW4KLOvOW WJ4KeUDHdWinIoedBg+FGlgWjACP3at6h3sKVqDsv76NmsCZHWjh3OV2pqQSp1ta n7HD/xPoGKNRDb+8r1CL3YLgwY4Hdvkq73koX8BGJ1jkB7LmikofGz0tnigcjrY/ D4QIPu+nIsi7hZs4S2nSMvvLWcdhUkDFa1F0hf3shYV+tPqUAFMYeG5MwMEQ4zqW KMUieCPRA4n5jiwQ3CBZgfcB+tCNJnsEkDtLoJydKNvgawpTanff7IJO2vALN64K PnIcPkHzFlbQj8lOLffCTFqqnOabkwaxeyV5r9oiT0OAg0paRBXrAo3VyVONzwqK vMAhNSygqeKudQ8EQcQS+0ymyjfSCJXa1M93lVG679VKcyVVrs0uEhjvub1abv3v Co08qKk18lsqYc55E8BzZ4T+F/mifzmEIPblM6EA9DnooSSrE/o= =rUxA -----END PGP SIGNATURE----- Merge tag 'mailbox-v5.2' of git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - New driver: Armada 37xx mailbox controller - Misc: Use devm_ api for imx and platform_get_irq for stm32 * tag 'mailbox-v5.2' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: Add support for Armada 37xx rWTM mailbox dt-bindings: mailbox: Document armada-3700-rwtm-mailbox binding mailbox: stm32-ipcc: check invalid irq mailbox: imx: use devm_platform_ioremap_resource() to simplify code
This commit is contained in:
Linus Torvalds
commit
15500c0a50
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@ -0,0 +1,16 @@
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* rWTM BIU Mailbox driver for Armada 37xx
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Required properties:
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- compatible: must be "marvell,armada-3700-rwtm-mailbox"
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- reg: physical base address of the mailbox and length of memory mapped
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region
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- interrupts: the IRQ line for the mailbox
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- #mbox-cells: must be 1
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Example:
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rwtm: mailbox@b0000 {
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compatible = "marvell,armada-3700-rwtm-mailbox";
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reg = <0xb0000 0x100>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};
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@ -41,6 +41,16 @@ config PL320_MBOX
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Management Engine, primarily for cpufreq. Say Y here if you want
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to use the PL320 IPCM support.
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config ARMADA_37XX_RWTM_MBOX
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tristate "Armada 37xx rWTM BIU Mailbox"
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depends on ARCH_MVEBU || COMPILE_TEST
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depends on OF
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help
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Mailbox implementation for communication with the the firmware
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running on the Cortex-M3 rWTM secure processor of the Armada 37xx
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SOC. Say Y here if you are building for such a device (for example
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the Turris Mox router).
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config OMAP2PLUS_MBOX
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tristate "OMAP2+ Mailbox framework support"
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depends on ARCH_OMAP2PLUS
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@ -9,6 +9,8 @@ obj-$(CONFIG_ARM_MHU) += arm_mhu.o
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obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
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obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o
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obj-$(CONFIG_PLATFORM_MHU) += platform_mhu.o
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obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
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@ -0,0 +1,225 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* rWTM BIU Mailbox driver for Armada 37xx
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*
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* Author: Marek Behun <marek.behun@nic.cz>
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/armada-37xx-rwtm-mailbox.h>
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#define DRIVER_NAME "armada-37xx-rwtm-mailbox"
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/* relative to rWTM BIU Mailbox Registers */
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#define RWTM_MBOX_PARAM(i) (0x0 + ((i) << 2))
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#define RWTM_MBOX_COMMAND 0x40
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#define RWTM_MBOX_RETURN_STATUS 0x80
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#define RWTM_MBOX_STATUS(i) (0x84 + ((i) << 2))
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#define RWTM_MBOX_FIFO_STATUS 0xc4
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#define FIFO_STS_RDY 0x100
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#define FIFO_STS_CNTR_MASK 0x7
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#define FIFO_STS_CNTR_MAX 4
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#define RWTM_HOST_INT_RESET 0xc8
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#define RWTM_HOST_INT_MASK 0xcc
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#define SP_CMD_COMPLETE BIT(0)
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#define SP_CMD_QUEUE_FULL_ACCESS BIT(17)
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#define SP_CMD_QUEUE_FULL BIT(18)
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struct a37xx_mbox {
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struct device *dev;
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struct mbox_controller controller;
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void __iomem *base;
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int irq;
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};
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static void a37xx_mbox_receive(struct mbox_chan *chan)
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{
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struct a37xx_mbox *mbox = chan->con_priv;
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struct armada_37xx_rwtm_rx_msg rx_msg;
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int i;
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rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS);
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for (i = 0; i < 16; ++i)
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rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i));
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mbox_chan_received_data(chan, &rx_msg);
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}
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static irqreturn_t a37xx_mbox_irq_handler(int irq, void *data)
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{
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struct mbox_chan *chan = data;
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struct a37xx_mbox *mbox = chan->con_priv;
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u32 reg;
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reg = readl(mbox->base + RWTM_HOST_INT_RESET);
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if (reg & SP_CMD_COMPLETE)
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a37xx_mbox_receive(chan);
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if (reg & (SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL))
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dev_err(mbox->dev, "Secure processor command queue full\n");
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writel(reg, mbox->base + RWTM_HOST_INT_RESET);
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if (reg)
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mbox_chan_txdone(chan, 0);
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return reg ? IRQ_HANDLED : IRQ_NONE;
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}
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static int a37xx_mbox_send_data(struct mbox_chan *chan, void *data)
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{
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struct a37xx_mbox *mbox = chan->con_priv;
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struct armada_37xx_rwtm_tx_msg *msg = data;
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int i;
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u32 reg;
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if (!data)
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return -EINVAL;
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reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS);
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if (!(reg & FIFO_STS_RDY))
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dev_warn(mbox->dev, "Secure processor not ready\n");
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if ((reg & FIFO_STS_CNTR_MASK) >= FIFO_STS_CNTR_MAX) {
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dev_err(mbox->dev, "Secure processor command queue full\n");
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return -EBUSY;
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}
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for (i = 0; i < 16; ++i)
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writel(msg->args[i], mbox->base + RWTM_MBOX_PARAM(i));
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writel(msg->command, mbox->base + RWTM_MBOX_COMMAND);
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return 0;
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}
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static int a37xx_mbox_startup(struct mbox_chan *chan)
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{
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struct a37xx_mbox *mbox = chan->con_priv;
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u32 reg;
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int ret;
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ret = devm_request_irq(mbox->dev, mbox->irq, a37xx_mbox_irq_handler, 0,
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DRIVER_NAME, chan);
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if (ret < 0) {
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dev_err(mbox->dev, "Cannot request irq\n");
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return ret;
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}
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/* enable IRQ generation */
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reg = readl(mbox->base + RWTM_HOST_INT_MASK);
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reg &= ~(SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL);
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writel(reg, mbox->base + RWTM_HOST_INT_MASK);
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return 0;
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}
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static void a37xx_mbox_shutdown(struct mbox_chan *chan)
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{
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u32 reg;
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struct a37xx_mbox *mbox = chan->con_priv;
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/* disable interrupt generation */
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reg = readl(mbox->base + RWTM_HOST_INT_MASK);
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reg |= SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL;
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writel(reg, mbox->base + RWTM_HOST_INT_MASK);
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devm_free_irq(mbox->dev, mbox->irq, chan);
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}
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static const struct mbox_chan_ops a37xx_mbox_ops = {
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.send_data = a37xx_mbox_send_data,
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.startup = a37xx_mbox_startup,
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.shutdown = a37xx_mbox_shutdown,
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};
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static int armada_37xx_mbox_probe(struct platform_device *pdev)
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{
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struct a37xx_mbox *mbox;
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struct resource *regs;
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struct mbox_chan *chans;
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int ret;
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mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
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if (!mbox)
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return -ENOMEM;
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/* Allocated one channel */
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chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL);
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if (!chans)
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return -ENOMEM;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mbox->base = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(mbox->base)) {
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dev_err(&pdev->dev, "ioremap failed\n");
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return PTR_ERR(mbox->base);
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}
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mbox->irq = platform_get_irq(pdev, 0);
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if (mbox->irq < 0) {
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dev_err(&pdev->dev, "Cannot get irq\n");
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return mbox->irq;
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}
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mbox->dev = &pdev->dev;
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/* Hardware supports only one channel. */
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chans[0].con_priv = mbox;
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mbox->controller.dev = mbox->dev;
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mbox->controller.num_chans = 1;
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mbox->controller.chans = chans;
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mbox->controller.ops = &a37xx_mbox_ops;
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mbox->controller.txdone_irq = true;
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ret = mbox_controller_register(&mbox->controller);
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if (ret) {
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dev_err(&pdev->dev, "Could not register mailbox controller\n");
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return ret;
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}
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platform_set_drvdata(pdev, mbox);
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return ret;
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}
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static int armada_37xx_mbox_remove(struct platform_device *pdev)
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{
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struct a37xx_mbox *mbox = platform_get_drvdata(pdev);
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if (!mbox)
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return -EINVAL;
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mbox_controller_unregister(&mbox->controller);
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return 0;
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}
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static const struct of_device_id armada_37xx_mbox_match[] = {
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{ .compatible = "marvell,armada-3700-rwtm-mailbox" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, armada_37xx_mbox_match);
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static struct platform_driver armada_37xx_mbox_driver = {
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.probe = armada_37xx_mbox_probe,
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.remove = armada_37xx_mbox_remove,
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = armada_37xx_mbox_match,
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},
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};
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module_platform_driver(armada_37xx_mbox_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("rWTM BIU Mailbox driver for Armada 37xx");
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MODULE_AUTHOR("Marek Behun <marek.behun@nic.cz>");
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@ -264,7 +264,6 @@ static int imx_mu_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct resource *iomem;
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struct imx_mu_priv *priv;
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unsigned int i;
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int ret;
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@ -275,8 +274,7 @@ static int imx_mu_probe(struct platform_device *pdev)
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priv->dev = dev;
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iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(&pdev->dev, iomem);
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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@ -8,9 +8,9 @@
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_wakeirq.h>
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@ -240,9 +240,11 @@ static int stm32_ipcc_probe(struct platform_device *pdev)
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/* irq */
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for (i = 0; i < IPCC_IRQ_NUM; i++) {
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ipcc->irqs[i] = of_irq_get_byname(dev->of_node, irq_name[i]);
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ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
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if (ipcc->irqs[i] < 0) {
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dev_err(dev, "no IRQ specified %s\n", irq_name[i]);
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if (ipcc->irqs[i] != -EPROBE_DEFER)
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dev_err(dev, "no IRQ specified %s\n",
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irq_name[i]);
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ret = ipcc->irqs[i];
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goto err_clk;
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}
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@ -263,9 +265,10 @@ static int stm32_ipcc_probe(struct platform_device *pdev)
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/* wakeup */
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if (of_property_read_bool(np, "wakeup-source")) {
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ipcc->wkp = of_irq_get_byname(dev->of_node, "wakeup");
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ipcc->wkp = platform_get_irq_byname(pdev, "wakeup");
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if (ipcc->wkp < 0) {
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dev_err(dev, "could not get wakeup IRQ\n");
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if (ipcc->wkp != -EPROBE_DEFER)
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dev_err(dev, "could not get wakeup IRQ\n");
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ret = ipcc->wkp;
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goto err_clk;
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}
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* rWTM BIU Mailbox driver for Armada 37xx
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*
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* Author: Marek Behun <marek.behun@nic.cz>
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*/
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#ifndef _LINUX_ARMADA_37XX_RWTM_MAILBOX_H_
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#define _LINUX_ARMADA_37XX_RWTM_MAILBOX_H_
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#include <linux/types.h>
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struct armada_37xx_rwtm_tx_msg {
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u16 command;
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u32 args[16];
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};
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struct armada_37xx_rwtm_rx_msg {
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u32 retval;
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u32 status[16];
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};
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#endif /* _LINUX_ARMADA_37XX_RWTM_MAILBOX_H_ */
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