parisc: Optimize timer interrupt function
Restructure the timer interrupt function to better cope with missed timer irqs. Optimize the calculation when the next interrupt should happen and skip irqs if they would happen too shortly after exit of the irq function. The update_process_times() call is done anyway at every timer irq, so we can safely drop the prof_counter and prof_multiplier variables from the per_cpu structure. Signed-off-by: Helge Deller <deller@gmx.de>
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Helge Deller
parent
82cbd568bc
commit
160494d381
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@ -93,9 +93,7 @@ struct system_cpuinfo_parisc {
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/* Per CPU data structure - ie varies per CPU. */
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struct cpuinfo_parisc {
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unsigned long it_value; /* Interval Timer at last timer Intr */
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unsigned long it_delta; /* Interval delta (tic_10ms / HZ * 100) */
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unsigned long irq_count; /* number of IRQ's since boot */
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unsigned long irq_max_cr16; /* longest time to handle a single IRQ */
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unsigned long cpuid; /* aka slot_number or set to NO_PROC_ID */
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unsigned long hpa; /* Host Physical address */
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unsigned long txn_addr; /* MMIO addr of EIR or id_eid */
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@ -103,8 +101,6 @@ struct cpuinfo_parisc {
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unsigned long pending_ipi; /* bitmap of type ipi_message_type */
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#endif
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unsigned long bh_count; /* number of times bh was invoked */
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unsigned long prof_counter; /* per CPU profiling support */
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unsigned long prof_multiplier; /* per CPU profiling support */
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unsigned long fp_rev;
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unsigned long fp_model;
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unsigned int state;
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@ -78,11 +78,6 @@ DEFINE_PER_CPU(struct cpuinfo_parisc, cpu_data);
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static void
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init_percpu_prof(unsigned long cpunum)
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{
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struct cpuinfo_parisc *p;
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p = &per_cpu(cpu_data, cpunum);
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p->prof_counter = 1;
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p->prof_multiplier = 1;
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}
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@ -59,10 +59,9 @@ static unsigned long clocktick __read_mostly; /* timer cycles per tick */
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*/
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irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
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{
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unsigned long now, now2;
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unsigned long now;
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unsigned long next_tick;
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unsigned long cycles_elapsed, ticks_elapsed = 1;
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unsigned long cycles_remainder;
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unsigned long ticks_elapsed = 0;
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unsigned int cpu = smp_processor_id();
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struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
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@ -71,102 +70,49 @@ irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
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profile_tick(CPU_PROFILING);
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/* Initialize next_tick to the expected tick time. */
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/* Initialize next_tick to the old expected tick time. */
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next_tick = cpuinfo->it_value;
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/* Get current cycle counter (Control Register 16). */
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now = mfctl(16);
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cycles_elapsed = now - next_tick;
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if ((cycles_elapsed >> 6) < cpt) {
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/* use "cheap" math (add/subtract) instead
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* of the more expensive div/mul method
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*/
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cycles_remainder = cycles_elapsed;
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while (cycles_remainder > cpt) {
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cycles_remainder -= cpt;
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ticks_elapsed++;
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}
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} else {
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/* TODO: Reduce this to one fdiv op */
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cycles_remainder = cycles_elapsed % cpt;
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ticks_elapsed += cycles_elapsed / cpt;
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}
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/* convert from "division remainder" to "remainder of clock tick" */
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cycles_remainder = cpt - cycles_remainder;
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/* Determine when (in CR16 cycles) next IT interrupt will fire.
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* We want IT to fire modulo clocktick even if we miss/skip some.
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* But those interrupts don't in fact get delivered that regularly.
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*/
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next_tick = now + cycles_remainder;
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/* Calculate how many ticks have elapsed. */
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do {
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++ticks_elapsed;
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next_tick += cpt;
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now = mfctl(16);
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} while (next_tick - now > cpt);
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/* Store (in CR16 cycles) up to when we are accounting right now. */
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cpuinfo->it_value = next_tick;
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/* Program the IT when to deliver the next interrupt.
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* Only bottom 32-bits of next_tick are writable in CR16!
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*/
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mtctl(next_tick, 16);
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/* Go do system house keeping. */
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if (cpu == 0)
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xtime_update(ticks_elapsed);
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/* Skip one clocktick on purpose if we missed next_tick.
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update_process_times(user_mode(get_irq_regs()));
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/* Skip clockticks on purpose if we know we would miss those.
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* The new CR16 must be "later" than current CR16 otherwise
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* itimer would not fire until CR16 wrapped - e.g 4 seconds
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* later on a 1Ghz processor. We'll account for the missed
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* tick on the next timer interrupt.
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* ticks on the next timer interrupt.
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* We want IT to fire modulo clocktick even if we miss/skip some.
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* But those interrupts don't in fact get delivered that regularly.
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*
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* "next_tick - now" will always give the difference regardless
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* if one or the other wrapped. If "now" is "bigger" we'll end up
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* with a very large unsigned number.
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*/
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now2 = mfctl(16);
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if (next_tick - now2 > cpt)
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mtctl(next_tick+cpt, 16);
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while (next_tick - mfctl(16) > cpt)
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next_tick += cpt;
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#if 1
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/*
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* GGG: DEBUG code for how many cycles programming CR16 used.
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*/
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if (unlikely(now2 - now > 0x3000)) /* 12K cycles */
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printk (KERN_CRIT "timer_interrupt(CPU %d): SLOW! 0x%lx cycles!"
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" cyc %lX rem %lX "
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" next/now %lX/%lX\n",
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cpu, now2 - now, cycles_elapsed, cycles_remainder,
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next_tick, now );
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#endif
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/* Can we differentiate between "early CR16" (aka Scenario 1) and
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* "long delay" (aka Scenario 3)? I don't think so.
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*
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* Timer_interrupt will be delivered at least a few hundred cycles
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* after the IT fires. But it's arbitrary how much time passes
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* before we call it "late". I've picked one second.
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*
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* It's important NO printk's are between reading CR16 and
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* setting up the next value. May introduce huge variance.
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/* Program the IT when to deliver the next interrupt.
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* Only bottom 32-bits of next_tick are writable in CR16!
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* Timer interrupt will be delivered at least a few hundred cycles
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* after the IT fires, so if we are too close (<= 500 cycles) to the
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* next cycle, simply skip it.
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*/
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if (unlikely(ticks_elapsed > HZ)) {
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/* Scenario 3: very long delay? bad in any case */
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printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!"
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" cycles %lX rem %lX "
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" next/now %lX/%lX\n",
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cpu,
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cycles_elapsed, cycles_remainder,
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next_tick, now );
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}
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/* Done mucking with unreliable delivery of interrupts.
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* Go do system house keeping.
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*/
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if (!--cpuinfo->prof_counter) {
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cpuinfo->prof_counter = cpuinfo->prof_multiplier;
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update_process_times(user_mode(get_irq_regs()));
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}
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if (cpu == 0)
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xtime_update(ticks_elapsed);
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if (next_tick - mfctl(16) <= 500)
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next_tick += cpt;
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mtctl(next_tick, 16);
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return IRQ_HANDLED;
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}
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