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ARM: SoC platform updates for 4.17 

This release brings up a new platform based on the old ARM9 core: the
 Nuvoton NPCM is used as a baseboard management controller, competing
 with the better known ASpeed AST2xx series.
 
 Another important change is the addition of ARMv7-A based chips
 in mach-stm32. The older parts in this platform are ARMv7-M based
 microcontrollers, now they are expanding to general-purpose workloads.
 
 The other changes are the usual defconfig updates to enable additional
 drivers, lesser bugfixes. The largest updates as often are the ongoing
 OMAP cleanups, but we also have a number of changes for the older
 PXA and davinci platforms this time.
 
 For the Renesas shmobile/r-car platform, some new infrastructure
 is needed to make the watchdog work correctly.
 
 Supporting Multiprocessing on Allwinner A80 required a significant
 amount of new code, but is not doing anything unexpected.
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "This release brings up a new platform based on the old ARM9 core: the
  Nuvoton NPCM is used as a baseboard management controller, competing
  with the better known ASpeed AST2xx series.

  Another important change is the addition of ARMv7-A based chips in
  mach-stm32. The older parts in this platform are ARMv7-M based
  microcontrollers, now they are expanding to general-purpose workloads.

  The other changes are the usual defconfig updates to enable additional
  drivers, lesser bugfixes. The largest updates as often are the ongoing
  OMAP cleanups, but we also have a number of changes for the older PXA
  and davinci platforms this time.

  For the Renesas shmobile/r-car platform, some new infrastructure is
  needed to make the watchdog work correctly.

  Supporting Multiprocessing on Allwinner A80 required a significant
  amount of new code, but is not doing anything unexpected"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (179 commits)
  arm: npcm: modify configuration for the NPCM7xx BMC.
  MAINTAINERS: update entry for ARM/berlin
  ARM: omap2: fix am43xx build without L2X0
  ARM: davinci: da8xx: simplify CFGCHIP regmap_config
  ARM: davinci: da8xx: fix oops in USB PHY driver due to stack allocated platform_data
  ARM: multi_v7_defconfig: add NXP FlexCAN IP support
  ARM: multi_v7_defconfig: enable thermal driver for i.MX devices
  ARM: multi_v7_defconfig: add RN5T618 PMIC family support
  ARM: multi_v7_defconfig: add NXP graphics drivers
  ARM: multi_v7_defconfig: add GPMI NAND controller support
  ARM: multi_v7_defconfig: add OCOTP driver for NXP SoCs
  ARM: multi_v7_defconfig: configure I2C driver built-in
  arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and CONFIG_SNI_AVE
  ARM: imx: fix imx6sll-only build
  ARM: imx: select ARM_CPU_SUSPEND for CPU_IDLE as well
  ARM: mxs_defconfig: Re-sync defconfig
  ARM: imx_v4_v5_defconfig: Use the generic fsl-asoc-card driver
  ARM: imx_v4_v5_defconfig: Re-sync defconfig
  arm64: defconfig: enable stmmac ethernet to defconfig
  ARM: EXYNOS: Simplify code in coupled CPU idle hot path
  ...
This commit is contained in:
Linus Torvalds 2018-04-05 21:21:08 -07:00
parent b240b419db cd903711fd
commit 167569343f
189 changed files with 4979 additions and 3966 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
Documentation/arm/Atmel/README → Documentation/arm/Microchip/README
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@ -1,54 +1,54 @@
ARM Atmel SoCs (aka AT91)
=========================
ARM Microchip SoCs (aka AT91)
=============================
Introduction
------------
This document gives useful information about the ARM Atmel SoCs that are
This document gives useful information about the ARM Microchip SoCs that are
currently supported in Linux Mainline (you know, the one on kernel.org).
It is important to note that the Atmel | SMART ARM-based MPU product line is
historically named "AT91" or "at91" throughout the Linux kernel development
process even if this product prefix has completely disappeared from the
official Atmel product name. Anyway, files, directories, git trees,
It is important to note that the Microchip (previously Atmel) ARM-based MPU
product line is historically named "AT91" or "at91" throughout the Linux kernel
development process even if this product prefix has completely disappeared from
the official Microchip product name. Anyway, files, directories, git trees,
git branches/tags and email subject always contain this "at91" sub-string.
AT91 SoCs
---------
Documentation and detailed datasheet for each product are available on
the Atmel website: http://www.atmel.com.
the Microchip website: http://www.microchip.com.
Flavors:
* ARM 920 based SoC
- at91rm9200
+ Datasheet
http://www.atmel.com/Images/doc1768.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-1768-32-bit-ARM920T-Embedded-Microprocessor-AT91RM9200_Datasheet.pdf
* ARM 926 based SoCs
- at91sam9260
+ Datasheet
http://www.atmel.com/Images/doc6221.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6221-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9260_Datasheet.pdf
- at91sam9xe
+ Datasheet
http://www.atmel.com/Images/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9XE_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9XE_Datasheet.pdf
- at91sam9261
+ Datasheet
http://www.atmel.com/Images/doc6062.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6062-ARM926EJ-S-Microprocessor-SAM9261_Datasheet.pdf
- at91sam9263
+ Datasheet
http://www.atmel.com/Images/Atmel_6249_32-bit-ARM926EJ-S-Microcontroller_SAM9263_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6249-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9263_Datasheet.pdf
- at91sam9rl
+ Datasheet
http://www.atmel.com/Images/doc6289.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/doc6289.pdf
- at91sam9g20
+ Datasheet
http://www.atmel.com/Images/doc6384.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001516A.pdf
- at91sam9g45 family
- at91sam9g45
@ -56,7 +56,7 @@ the Atmel website: http://www.atmel.com.
- at91sam9m10
- at91sam9m11 (device superset)
+ Datasheet
http://www.atmel.com/Images/Atmel-6437-32-bit-ARM926-Embedded-Microprocessor-SAM9M11_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6437-32-bit-ARM926-Embedded-Microprocessor-SAM9M11_Datasheet.pdf
- at91sam9x5 family (aka "The 5 series")
- at91sam9g15
@ -65,11 +65,11 @@ the Atmel website: http://www.atmel.com.
- at91sam9x25
- at91sam9x35
+ Datasheet (can be considered as covering the whole family)
http://www.atmel.com/Images/Atmel_11055_32-bit-ARM926EJ-S-Microcontroller_SAM9X35_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11055-32-bit-ARM926EJ-S-Microcontroller-SAM9X35_Datasheet.pdf
- at91sam9n12
+ Datasheet
http://www.atmel.com/Images/Atmel_11063_32-bit-ARM926EJ-S-Microcontroller_SAM9N12CN11CN12_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001517A.pdf
* ARM Cortex-A5 based SoCs
- sama5d3 family
@ -79,7 +79,7 @@ the Atmel website: http://www.atmel.com.
- sama5d35
- sama5d36 (device superset)
+ Datasheet
http://www.atmel.com/Images/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
* ARM Cortex-A5 + NEON based SoCs
- sama5d4 family
@ -88,7 +88,7 @@ the Atmel website: http://www.atmel.com.
- sama5d43
- sama5d44 (device superset)
+ Datasheet
http://www.atmel.com/Images/Atmel-11238-32-bit-Cortex-A5-Microcontroller-SAMA5D4_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/60001525A.pdf
- sama5d2 family
- sama5d21
@ -99,7 +99,7 @@ the Atmel website: http://www.atmel.com.
- sama5d27 (device superset)
- sama5d28 (device superset + environmental monitors)
+ Datasheet
http://www.atmel.com/Images/Atmel-11267-32-bit-Cortex-A5-Microcontroller-SAMA5D2_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001476B.pdf
* ARM Cortex-M7 MCUs
- sams70 family
@ -112,8 +112,6 @@ the Atmel website: http://www.atmel.com.
- sams70q19
- sams70q20
- sams70q21
+ Datasheet
http://www.atmel.com/Images/Atmel-11242-32-bit-Cortex-M7-Microcontroller-SAM-S70Q-SAM-S70N-SAM-S70J_Datasheet.pdf
- samv70 family
- samv70j19
@ -122,8 +120,6 @@ the Atmel website: http://www.atmel.com.
- samv70n20
- samv70q19
- samv70q20
+ Datasheet
http://www.atmel.com/Images/Atmel-11297-32-bit-Cortex-M7-Microcontroller-SAM-V70Q-SAM-V70N-SAM-V70J_Datasheet.pdf
- samv71 family
- samv71j19
@ -135,13 +131,15 @@ the Atmel website: http://www.atmel.com.
- samv71q19
- samv71q20
- samv71q21
+ Datasheet
http://www.atmel.com/Images/Atmel-44003-32-bit-Cortex-M7-Microcontroller-SAM-V71Q-SAM-V71N-SAM-V71J_Datasheet.pdf
http://ww1.microchip.com/downloads/en/DeviceDoc/60001527A.pdf
Linux kernel information
------------------------
Linux kernel mach directory: arch/arm/mach-at91
MAINTAINERS entry is: "ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES"
MAINTAINERS entry is: "ARM/Microchip (AT91) SoC support"
Device Tree for AT91 SoCs and boards

34
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@ -0,0 +1,34 @@
========================
STM32 ARM Linux Overview
========================
Introduction
------------
The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and
Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
ARM Linux.
Configuration
-------------
For MCUs, use the provided default configuration:
make stm32_defconfig
For MPUs, use multi_v7 configuration:
make multi_v7_defconfig
Layout
------
All the files for multiple machine families are located in the platform code
contained in arch/arm/mach-stm32
There is a generic board board-dt.c in the mach folder which support
Flattened Device Tree, which means, it works with any compatible board with
Device Trees.
:Authors:
- Maxime Coquelin <mcoquelin.stm32@gmail.com>
- Ludovic Barre <ludovic.barre@st.com>
- Gerald Baeza <gerald.baeza@st.com>

33
Documentation/arm/stm32/overview.txt
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@ -1,33 +0,0 @@
STM32 ARM Linux Overview
========================
Introduction
------------
The STMicroelectronics family of Cortex-M based MCUs are supported by the
'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4)
and STM32F746 (Cortex-M7) are supported.
Configuration
-------------
A generic configuration is provided for STM32 family, and can be used as the
default by
make stm32_defconfig
Layout
------
All the files for multiple machine families are located in the platform code
contained in arch/arm/mach-stm32
There is a generic board board-dt.c in the mach folder which support
Flattened Device Tree, which means, it works with any compatible board with
Device Trees.
Document Author
---------------
Maxime Coquelin <mcoquelin.stm32@gmail.com>

26
Documentation/arm/stm32/stm32f429-overview.rst Normal file
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@ -0,0 +1,26 @@
STM32F429 Overview
==================
Introduction
------------
The STM32F429 is a Cortex-M4 MCU aimed at various applications.
It features:
- ARM Cortex-M4 up to 180MHz with FPU
- 2MB internal Flash Memory
- External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
- I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
- LCD controller & Camera interface
- Cryptographic processor
Resources
---------
Datasheet and reference manual are publicly available on ST website (STM32F429_).
.. _STM32F429: http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
:Authors:
Maxime Coquelin <mcoquelin.stm32@gmail.com>

22
Documentation/arm/stm32/stm32f429-overview.txt
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@ -1,22 +0,0 @@
STM32F429 Overview
==================
Introduction
------------
The STM32F429 is a Cortex-M4 MCU aimed at various applications.
It features:
- ARM Cortex-M4 up to 180MHz with FPU
- 2MB internal Flash Memory
- External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
- I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
- LCD controller & Camera interface
- Cryptographic processor
Resources
---------
Datasheet and reference manual are publicly available on ST website:
- http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
Document Author
---------------
Maxime Coquelin <mcoquelin.stm32@gmail.com>

33
Documentation/arm/stm32/stm32f746-overview.rst Normal file
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@ -0,0 +1,33 @@
STM32F746 Overview
==================
Introduction
------------
The STM32F746 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @216MHz
- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
Resources
---------
Datasheet and reference manual are publicly available on ST website (STM32F746_).
.. _STM32F746: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
:Authors:
Alexandre Torgue <alexandre.torgue@st.com>

34
Documentation/arm/stm32/stm32f746-overview.txt
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@ -1,34 +0,0 @@
STM32F746 Overview
==================
Introduction
------------
The STM32F746 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @216MHz
- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
Resources
---------
Datasheet and reference manual are publicly available on ST website:
- http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
Document Author
---------------
Alexandre Torgue <alexandre.torgue@st.com>

35
Documentation/arm/stm32/stm32f769-overview.rst Normal file
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@ -0,0 +1,35 @@
STM32F769 Overview
==================
Introduction
------------
The STM32F769 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @216MHz
- 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support*2
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C*4, SPI*6, CAN*3 busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface*2
- LCD controller
- HDMI-CEC
- DSI
- SPDIFRX
- MDIO salave interface
Resources
---------
Datasheet and reference manual are publicly available on ST website (STM32F769_).
.. _STM32F769: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html
:Authors:
Alexandre Torgue <alexandre.torgue@st.com>

34
Documentation/arm/stm32/stm32h743-overview.rst Normal file
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@ -0,0 +1,34 @@
STM32H743 Overview
==================
Introduction
------------
The STM32H743 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @400MHz
- 2MB internal flash, 1MBytes internal RAM
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
- DFSDM
Resources
---------
Datasheet and reference manual are publicly available on ST website (STM32H743_).
.. _STM32H743: http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
:Authors:
Alexandre Torgue <alexandre.torgue@st.com>

30
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@ -1,30 +0,0 @@
STM32H743 Overview
==================
Introduction
------------
The STM32H743 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @400MHz
- 2MB internal flash, 1MBytes internal RAM
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
- DFSDM
Resources
---------
Datasheet and reference manual are publicly available on ST website:
- http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
Document Author
---------------
Alexandre Torgue <alexandre.torgue@st.com>

19
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@ -0,0 +1,19 @@
STM32MP157 Overview
===================
Introduction
------------
The STM32MP157 is a Cortex-A MPU aimed at various applications.
It features:
- Dual core Cortex-A7 application core
- 2D/3D image composition with GPU
- Standard memories interface support
- Standard connectivity, widely inherited from the STM32 MCU family
- Comprehensive security support
:Authors:
- Ludovic Barre <ludovic.barre@st.com>
- Gerald Baeza <gerald.baeza@st.com>

1
Documentation/devicetree/bindings/arm/cpus.txt
View File

@ -199,6 +199,7 @@ described below.
"actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"allwinner,sun9i-a80-smp"
"amlogic,meson8-smp"
"amlogic,meson8b-smp"
"arm,realview-smp"

16
Documentation/devicetree/bindings/arm/omap/mpu.txt
View File

@ -13,6 +13,13 @@ Required properties:
Optional properties:
- sram: Phandle to the ocmcram node
am335x and am437x only:
- pm-sram: Phandles to ocmcram nodes to be used for power management.
First should be type 'protect-exec' for the driver to use to copy
and run PM functions, second should be regular pool to be used for
data region for code. See Documentation/devicetree/bindings/sram/sram.txt
for more details.
Examples:
- For an OMAP5 SMP system:
@ -36,3 +43,12 @@ mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
- For an AM335x system:
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};

44
Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt Normal file
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@ -0,0 +1,44 @@
Allwinner SRAM for smp bringup:
------------------------------------------------
Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
primary core (cpu0). Once the core gets powered up it checks if a magic
value is set at a specific location. If it is then the BROM will jump
to the software entry address, instead of executing a standard boot.
Therefore a reserved section sub-node has to be added to the mmio-sram
declaration.
Note that this is separate from the Allwinner SRAM controller found in
../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
any device.
Also there are no "secure-only" properties. The implementation should
check if this SRAM is usable first.
Required sub-node properties:
- compatible : depending on the SoC this should be one of:
"allwinner,sun9i-a80-smp-sram"
The rest of the properties should follow the generic mmio-sram discription
found in ../../misc/sram.txt
Example:
sram_b: sram@20000 {
/* 256 KiB secure SRAM at 0x20000 */
compatible = "mmio-sram";
reg = <0x00020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00020000 0x40000>;
smp-sram@1000 {
/*
* This is checked by BROM to determine if
* cpu0 should jump to SMP entry vector
*/
compatible = "allwinner,sun9i-a80-smp-sram";
reg = <0x1000 0x8>;
};
};

50
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
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@ -1,50 +0,0 @@
PXA3xx NAND DT bindings
Required properties:
- compatible: Should be set to one of the following:
marvell,pxa3xx-nand
marvell,armada370-nand
marvell,armada-8k-nand
- reg: The register base for the controller
- interrupts: The interrupt to map
- #address-cells: Set to <1> if the node includes partitions
- marvell,system-controller: Set to retrieve the syscon node that handles
NAND controller related registers (only required
with marvell,armada-8k-nand compatible).
Optional properties:
- dmas: dma data channel, see dma.txt binding doc
- marvell,nand-enable-arbiter: Set to enable the bus arbiter
- marvell,nand-keep-config: Set to keep the NAND controller config as set
by the bootloader
- num-cs: Number of chipselect lines to use
- nand-on-flash-bbt: boolean to enable on flash bbt option if
not present false
- nand-ecc-strength: number of bits to correct per ECC step
- nand-ecc-step-size: number of data bytes covered by a single ECC step
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <1>, nand-ecc-step-size = <512>
- nand-ecc-strength = <4>, nand-ecc-step-size = <512>
- nand-ecc-strength = <8>, nand-ecc-step-size = <512>
Example:
nand0: nand@43100000 {
compatible = "marvell,pxa3xx-nand";
reg = <0x43100000 90>;
interrupts = <45>;
dmas = <&pdma 97 0>;
dma-names = "data";
#address-cells = <1>;
marvell,nand-enable-arbiter;
marvell,nand-keep-config;
num-cs = <1>;
/* partitions (optional) */
};

2
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
View File

@ -17,7 +17,9 @@ Required properties:
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- "renesas,r8a7796-sysc" (R-Car M3-W)
- "renesas,r8a77965-sysc" (R-Car M3-N)
- "renesas,r8a77970-sysc" (R-Car V3M)
- "renesas,r8a77980-sysc" (R-Car V3H)
- "renesas,r8a77995-sysc" (R-Car D3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.

2
Documentation/devicetree/bindings/reset/renesas,rst.txt
View File

@ -26,7 +26,9 @@ Required properties:
- "renesas,r8a7794-rst" (R-Car E2)
- "renesas,r8a7795-rst" (R-Car H3)
- "renesas,r8a7796-rst" (R-Car M3-W)
- "renesas,r8a77965-rst" (R-Car M3-N)
- "renesas,r8a77970-rst" (R-Car V3M)
- "renesas,r8a77980-rst" (R-Car V3H)
- "renesas,r8a77995-rst" (R-Car D3)
- reg: Address start and address range for the device.

88
MAINTAINERS
View File

@ -1242,27 +1242,6 @@ M: Boris Brezillon <boris.brezillon@free-electrons.com>
S: Maintained
F: drivers/clk/at91
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Alexandre Belloni <alexandre.belloni@bootlin.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.linux4sam.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
S: Supported
N: at91
N: atmel
F: arch/arm/mach-at91/
F: include/soc/at91/
F: arch/arm/boot/dts/at91*.dts
F: arch/arm/boot/dts/at91*.dtsi
F: arch/arm/boot/dts/sama*.dts
F: arch/arm/boot/dts/sama*.dtsi
F: arch/arm/include/debug/at91.S
F: drivers/memory/atmel*
F: drivers/watchdog/sama5d4_wdt.c
X: drivers/input/touchscreen/atmel_mxt_ts.c
X: drivers/net/wireless/atmel/
ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Rob Herring <robh@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -1583,15 +1562,6 @@ ARM/MAGICIAN MACHINE SUPPORT
M: Philipp Zabel <philipp.zabel@gmail.com>
S: Maintained
ARM/Marvell Berlin SoC support
M: Jisheng Zhang <jszhang@marvell.com>
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-berlin/
F: arch/arm/boot/dts/berlin*
F: arch/arm64/boot/dts/marvell/berlin*
ARM/Marvell Dove/MV78xx0/Orion SOC support
M: Jason Cooper <jason@lakedaemon.net>
M: Andrew Lunn <andrew@lunn.ch>
@ -1662,6 +1632,27 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
F: arch/arm/mach-ks8695/
S: Odd Fixes
ARM/Microchip (AT91) SoC support
M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Alexandre Belloni <alexandre.belloni@bootlin.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.linux4sam.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
S: Supported
N: at91
N: atmel
F: arch/arm/mach-at91/
F: include/soc/at91/
F: arch/arm/boot/dts/at91*.dts
F: arch/arm/boot/dts/at91*.dtsi
F: arch/arm/boot/dts/sama*.dts
F: arch/arm/boot/dts/sama*.dtsi
F: arch/arm/include/debug/at91.S
F: drivers/memory/atmel*
F: drivers/watchdog/sama5d4_wdt.c
X: drivers/input/touchscreen/atmel_mxt_ts.c
X: drivers/net/wireless/atmel/
ARM/MIOA701 MACHINE SUPPORT
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -1706,6 +1697,20 @@ F: Documentation/devicetree/bindings/arm/ste-*
F: Documentation/devicetree/bindings/arm/ux500/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
ARM/NUVOTON NPCM ARCHITECTURE
M: Avi Fishman <avifishman70@gmail.com>
M: Tomer Maimon <tmaimon77@gmail.com>
R: Patrick Venture <venture@google.com>
R: Nancy Yuen <yuenn@google.com>
R: Brendan Higgins <brendanhiggins@google.com>
L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
S: Supported
F: arch/arm/mach-npcm/
F: arch/arm/boot/dts/nuvoton-npcm*
F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
F: drivers/*/*npcm*
F: Documentation/*/*npcm*
ARM/NUVOTON W90X900 ARM ARCHITECTURE
M: Wan ZongShun <mcuos.com@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -1968,6 +1973,14 @@ M: Thor Thayer <thor.thayer@linux.intel.com>
S: Maintained
F: drivers/edac/altera_edac.
ARM/SPREADTRUM SoC SUPPORT
M: Orson Zhai <orsonzhai@gmail.com>
M: Baolin Wang <baolin.wang@linaro.org>
M: Chunyan Zhang <zhang.lyra@gmail.com>
S: Maintained
F: arch/arm64/boot/dts/sprd
N: sprd
ARM/STI ARCHITECTURE
M: Patrice Chotard <patrice.chotard@st.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2010,6 +2023,15 @@ F: arch/arm/boot/dts/stm32*
F: arch/arm/mach-stm32/
F: drivers/clocksource/armv7m_systick.c
ARM/Synaptics Berlin SoC support
M: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-berlin/
F: arch/arm/boot/dts/berlin*
F: arch/arm64/boot/dts/marvell/berlin*
ARM/TANGO ARCHITECTURE
M: Marc Gonzalez <marc.w.gonzalez@free.fr>
M: Mans Rullgard <mans@mansr.com>
@ -11416,12 +11438,6 @@ F: include/sound/pxa2xx-lib.h
F: sound/arm/pxa*
F: sound/soc/pxa/
PXA3xx NAND FLASH DRIVER
M: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
L: linux-mtd@lists.infradead.org
S: Maintained
F: drivers/mtd/nand/pxa3xx_nand.c
QAT DRIVER
M: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
L: qat-linux@intel.com

54
arch/arm/Kconfig
View File

@ -709,8 +709,6 @@ config ARCH_VIRT
# Kconfigs may be included either alphabetically (according to the
# plat- suffix) or along side the corresponding mach-* source.
#
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-actions/Kconfig"
source "arch/arm/mach-alpine/Kconfig"
@ -719,6 +717,8 @@ source "arch/arm/mach-artpec/Kconfig"
source "arch/arm/mach-asm9260/Kconfig"
source "arch/arm/mach-aspeed/Kconfig"
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-axxia/Kconfig"
@ -739,6 +739,9 @@ source "arch/arm/mach-dove/Kconfig"
source "arch/arm/mach-ep93xx/Kconfig"
source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/mach-footbridge/Kconfig"
source "arch/arm/mach-gemini/Kconfig"
@ -747,31 +750,33 @@ source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-hisi/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop13xx/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-iop33x/Kconfig"
source "arch/arm/mach-iop13xx/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-moxart/Kconfig"
source "arch/arm/mach-aspeed/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-mxs/Kconfig"
@ -779,6 +784,8 @@ source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/mach-npcm/Kconfig"
source "arch/arm/mach-nspire/Kconfig"
source "arch/arm/plat-omap/Kconfig"
@ -789,23 +796,31 @@ source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-oxnas/Kconfig"
source "arch/arm/mach-picoxcell/Kconfig"
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-oxnas/Kconfig"
source "arch/arm/mach-qcom/Kconfig"
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-s3c24xx/Kconfig"
source "arch/arm/mach-s3c64xx/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
source "arch/arm/mach-sa1100/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
source "arch/arm/mach-spear/Kconfig"
@ -814,21 +829,8 @@ source "arch/arm/mach-sti/Kconfig"
source "arch/arm/mach-stm32/Kconfig"
source "arch/arm/mach-s3c24xx/Kconfig"
source "arch/arm/mach-s3c64xx/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-tango/Kconfig"
source "arch/arm/mach-tegra/Kconfig"

1
arch/arm/Makefile
View File

@ -196,6 +196,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX) += netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_NSPIRE) += nspire
machine-$(CONFIG_ARCH_OXNAS) += oxnas
machine-$(CONFIG_ARCH_OMAP1) += omap1

6
arch/arm/boot/dts/pxa3xx.dtsi
View File

@ -117,15 +117,15 @@ pwri2c: i2c@40f500c0 {
status = "disabled";
};
nand0: nand@43100000 {
compatible = "marvell,pxa3xx-nand";
nand_controller: nand-controller@43100000 {
compatible = "marvell,pxa3xx-nand-controller";
reg = <0x43100000 90>;
interrupts = <45>;
clocks = <&clks CLK_NAND>;
dmas = <&pdma 97 3>;
dma-names = "data";
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

4
arch/arm/configs/bcm2835_defconfig
View File

@ -49,6 +49,9 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NETFILTER=y
CONFIG_BT=y
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_BCM=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_DEVTMPFS=y
@ -74,6 +77,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_BCM2835AUX=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_TTY_PRINTK=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_BCM2835=y

2
arch/arm/configs/cm_x300_defconfig
View File

@ -49,7 +49,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_PXA3xx=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y

3
arch/arm/configs/davinci_all_defconfig
View File

@ -126,9 +126,10 @@ CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_SYSCON_REBOOT_MODE=m
CONFIG_BATTERY_LEGO_EV3=m
CONFIG_WATCHDOG=y
CONFIG_DAVINCI_WATCHDOG=m
CONFIG_DAVINCI_WATCHDOG=y
CONFIG_MFD_DM355EVM_MSP=y
CONFIG_TPS6507X=y
CONFIG_REGULATOR=y

9
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -1,7 +1,6 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
@ -78,7 +77,6 @@ CONFIG_SMC91X=y
CONFIG_SMC911X=y
CONFIG_SMSC911X=y
CONFIG_SMSC_PHY=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_IMX=y
@ -105,8 +103,8 @@ CONFIG_HWMON=m
CONFIG_SENSORS_MC13783_ADC=m
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_MX25_TSADC=y
CONFIG_MFD_MC13XXX_SPI=y
CONFIG_MFD_MX25_TSADC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
@ -116,10 +114,8 @@ CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_VIDEO_MX2=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_CODA=y
CONFIG_SOC_CAMERA_OV2640=y
CONFIG_FB=y
CONFIG_FB_IMX=y
CONFIG_LCD_L4F00242T03=y
@ -134,8 +130,9 @@ CONFIG_SND_IMX_SOC=y
CONFIG_SND_SOC_MX27VIS_AIC32X4=y
CONFIG_SND_SOC_PHYCORE_AC97=y
CONFIG_SND_SOC_EUKREA_TLV320=y
CONFIG_SND_SOC_IMX_SGTL5000=y
CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_SND_SOC_FSL_ASOC_CARD=y
CONFIG_SND_SOC_SGTL5000=y
CONFIG_USB_HID=m
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y

30
arch/arm/configs/imx_v6_v7_defconfig
View File

@ -48,9 +48,7 @@ CONFIG_PCI_IMX6=y
CONFIG_SMP=y
CONFIG_ARM_PSCI=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_CMA=y
CONFIG_FORCE_MAX_ZONEORDER=14
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_KEXEC=y
@ -60,6 +58,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPUFREQ_DT=y
CONFIG_ARM_IMX6Q_CPUFREQ=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
@ -81,7 +80,6 @@ CONFIG_CAN=y
CONFIG_CAN_FLEXCAN=y
CONFIG_BT=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_LL=y
CONFIG_CFG80211=y
@ -92,7 +90,6 @@ CONFIG_RFKILL_INPUT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_IMX_WEIM=y
CONFIG_CONNECTOR=y
@ -170,9 +167,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_EGALAX=y
CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_MC13783=y
CONFIG_TOUCHSCREEN_TSC2004=y
CONFIG_TOUCHSCREEN_TSC2007=y
@ -181,7 +178,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MMA8450=y
CONFIG_HID_MULTITOUCH=y
CONFIG_SERIO_SERPORT=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_IMX=y
@ -189,7 +185,6 @@ CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
@ -209,19 +204,19 @@ CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_74X164=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_IMX=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_IIO_HWMON=y
CONFIG_THERMAL=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_CPU_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_DA9062_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_DA9052_I2C=y
CONFIG_MFD_DA9062=y
CONFIG_MFD_MC13XXX_SPI=y
CONFIG_MFD_MC13XXX_I2C=y
CONFIG_MFD_STMPE=y
@ -229,17 +224,18 @@ CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ANATOP=y
CONFIG_REGULATOR_DA9052=y
CONFIG_REGULATOR_DA9062=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_RC_CORE=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_RC_DEVICES=y
CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
@ -250,7 +246,6 @@ CONFIG_VIDEO_CODA=m
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_OV5640=m
CONFIG_SOC_CAMERA_OV2640=y
CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_LVDS=y
@ -285,10 +280,13 @@ CONFIG_SND_SOC_IMX_SGTL5000=y
CONFIG_SND_SOC_IMX_SPDIF=y
CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_SND_SOC_FSL_ASOC_CARD=y
CONFIG_SND_SOC_AC97_CODEC=y
CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SOC_WM8962=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_HID_MULTITOUCH=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
@ -354,6 +352,7 @@ CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_PCF8523=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_M41T80=y
CONFIG_RTC_DRV_DA9063=y
CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y
CONFIG_RTC_DRV_MXC_V2=y
@ -369,11 +368,14 @@ CONFIG_COMMON_CLK_PWM=y
CONFIG_IIO=y
CONFIG_IMX7D_ADC=y
CONFIG_VF610_ADC=y
CONFIG_MAG3110=y
CONFIG_MPL3115=y
CONFIG_PWM=y
CONFIG_PWM_FSL_FTM=y
CONFIG_PWM_IMX=y
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MUX_MMIO=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y

64
arch/arm/configs/multi_v7_defconfig
View File

@ -80,6 +80,7 @@ CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
CONFIG_ARCH_STI=y
CONFIG_ARCH_STM32=y
CONFIG_ARCH_EXYNOS=y
CONFIG_EXYNOS5420_MCPM=y
CONFIG_ARCH_RENESAS=y
@ -174,6 +175,7 @@ CONFIG_CAN_RAW=y
CONFIG_CAN_BCM=y
CONFIG_CAN_DEV=y
CONFIG_CAN_AT91=m
CONFIG_CAN_FLEXCAN=m
CONFIG_CAN_RCAR=m
CONFIG_CAN_XILINXCAN=y
CONFIG_CAN_MCP251X=y
@ -208,6 +210,7 @@ CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_BRCMNAND=y
CONFIG_MTD_NAND_VF610_NFC=y
CONFIG_MTD_NAND_DAVINCI=y
@ -307,11 +310,15 @@ CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MAX77693_HAPTIC=m
CONFIG_INPUT_MAX8997_HAPTIC=m
CONFIG_INPUT_CPCAP_PWRBUTTON=m
CONFIG_INPUT_AXP20X_PEK=m
CONFIG_INPUT_ADXL34X=m
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_BCM2835AUX=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_8250_MT6577=y
@ -351,6 +358,8 @@ CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
CONFIG_SERIAL_ST_ASC=y
CONFIG_SERIAL_ST_ASC_CONSOLE=y
CONFIG_SERIAL_STM32=y
CONFIG_SERIAL_STM32_CONSOLE=y
CONFIG_HVC_DRIVER=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_I2C_CHARDEV=y
@ -368,7 +377,7 @@ CONFIG_I2C_DIGICOLOR=m
CONFIG_I2C_EMEV2=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_EXYNOS5=y
CONFIG_I2C_IMX=m
CONFIG_I2C_IMX=y
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_RIIC=y
CONFIG_I2C_RK3X=y
@ -438,9 +447,11 @@ CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
CONFIG_BATTERY_ACT8945A=y
CONFIG_BATTERY_CPCAP=m
CONFIG_BATTERY_SBS=y
CONFIG_BATTERY_MAX17040=m
CONFIG_BATTERY_MAX17042=m
CONFIG_CHARGER_CPCAP=m
CONFIG_CHARGER_MAX14577=m
CONFIG_CHARGER_MAX77693=m
CONFIG_CHARGER_MAX8997=m
@ -462,7 +473,9 @@ CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_PWM_FAN=m
CONFIG_SENSORS_INA2XX=m
CONFIG_CPU_THERMAL=y
CONFIG_BCM2835_THERMAL=m
CONFIG_BRCMSTB_THERMAL=m
CONFIG_IMX_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_ARMADA_THERMAL=y
@ -476,6 +489,7 @@ CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_SAMA5D4_WATCHDOG=y
CONFIG_ORION_WATCHDOG=y
CONFIG_RN5T618_WATCHDOG=y
CONFIG_ST_LPC_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
CONFIG_IMX2_WDT=y
@ -508,9 +522,11 @@ CONFIG_MFD_MAX8907=y
CONFIG_MFD_MAX8997=y
CONFIG_MFD_MAX8998=y
CONFIG_MFD_RK808=y
CONFIG_MFD_CPCAP=y
CONFIG_MFD_PM8XXX=y
CONFIG_MFD_QCOM_RPM=y
CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_RN5T618=y
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_STMPE=y
CONFIG_MFD_PALMAS=y
@ -527,6 +543,7 @@ CONFIG_REGULATOR_AS3711=y
CONFIG_REGULATOR_AS3722=y
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_BCM590XX=y
CONFIG_REGULATOR_CPCAP=y
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_RK808=y
@ -547,6 +564,7 @@ CONFIG_REGULATOR_PBIAS=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_RPM=y
CONFIG_REGULATOR_QCOM_SMD_RPM=y
CONFIG_REGULATOR_RN5T618=y
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_TI_ABB=y
@ -617,6 +635,7 @@ CONFIG_DRM_ATMEL_HLCDC=m
CONFIG_DRM_RCAR_DU=m
CONFIG_DRM_RCAR_LVDS=y
CONFIG_DRM_SUN4I=m
CONFIG_DRM_FSL_DCU=m
CONFIG_DRM_TEGRA=y
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
@ -624,6 +643,8 @@ CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_SII9234=m
CONFIG_DRM_STI=m
CONFIG_DRM_VC4=y
CONFIG_DRM_ETNAVIV=m
CONFIG_DRM_MXSFB=m
CONFIG_FB_ARMCLCD=y
CONFIG_FB_EFI=y
CONFIG_FB_WM8505=y
@ -674,6 +695,7 @@ CONFIG_SND_SOC_TEGRA_WM8903=m
CONFIG_SND_SOC_TEGRA_WM9712=m
CONFIG_SND_SOC_TEGRA_TRIMSLICE=m
CONFIG_SND_SOC_TEGRA_ALC5632=m
CONFIG_SND_SOC_CPCAP=m
CONFIG_SND_SOC_TEGRA_MAX98090=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_SGTL5000=m
@ -683,6 +705,7 @@ CONFIG_SND_SOC_STI=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_XHCI_RCAR=m
@ -704,6 +727,15 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=m
CONFIG_USB_MUSB_HDRC=m
CONFIG_USB_MUSB_SUNXI=m
CONFIG_USB_MUSB_TUSB6010=m
CONFIG_USB_MUSB_OMAP2PLUS=m
CONFIG_USB_MUSB_AM35X=m
CONFIG_USB_MUSB_DSPS=m
CONFIG_USB_MUSB_UX500=m
CONFIG_USB_UX500_DMA=y
CONFIG_USB_INVENTRA_DMA=y
CONFIG_USB_TI_CPPI41_DMA=y
CONFIG_USB_TUSB_OMAP_DMA=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC2=y
CONFIG_USB_HSIC_USB3503=y
@ -712,6 +744,9 @@ CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_AB8500_USB=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
CONFIG_AM335X_PHY_USB=m
CONFIG_TWL6030_USB=m
CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_ISP1301=y
CONFIG_USB_MSM_OTG=m
@ -719,6 +754,25 @@ CONFIG_USB_MXS_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_FSL_USB2=y
CONFIG_USB_RENESAS_USBHS_UDC=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_ETH=m
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
@ -755,6 +809,7 @@ CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
CONFIG_LEDS_CPCAP=m
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_MAX77693=m
@ -805,6 +860,7 @@ CONFIG_RTC_DRV_SUN6I=y
CONFIG_RTC_DRV_SUNXI=y
CONFIG_RTC_DRV_MV=y
CONFIG_RTC_DRV_TEGRA=y
CONFIG_RTC_DRV_CPCAP=m
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_AT_HDMAC=y
@ -877,6 +933,7 @@ CONFIG_IIO_SW_TRIGGER=y
CONFIG_AT91_ADC=m
CONFIG_AT91_SAMA5D2_ADC=m
CONFIG_BERLIN2_ADC=m
CONFIG_CPCAP_ADC=m
CONFIG_EXYNOS_ADC=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=y
@ -902,9 +959,12 @@ CONFIG_E1000E=y
CONFIG_PWM_STI=y
CONFIG_PWM_BCM2835=y
CONFIG_PWM_BRCMSTB=m
CONFIG_PHY_DM816X_USB=m
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_TWL4030_USB=m
CONFIG_PHY_BERLIN_USB=y
CONFIG_PHY_CPCAP_USB=m
CONFIG_PHY_BERLIN_SATA=y
CONFIG_PHY_ROCKCHIP_DP=m
CONFIG_PHY_ROCKCHIP_USB=y
@ -918,7 +978,9 @@ CONFIG_PHY_SAMSUNG_USB2=m
CONFIG_PHY_TEGRA_XUSB=y
CONFIG_PHY_BRCM_SATA=y
CONFIG_NVMEM=y
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_VF610_OCOTP=y
CONFIG_BCM2835_MBOX=y
CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_EFI_VARS=m

14
arch/arm/configs/mxs_defconfig
View File

@ -1,5 +1,4 @@
CONFIG_SYSVIPC=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_TASKSTATS=y
@ -62,14 +61,13 @@ CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_ENC28J60=y
CONFIG_SMSC_PHY=y
CONFIG_ICPLUS_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC95XX=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
@ -77,9 +75,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_MXS_LRADC=y
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_SERIO is not set
CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_MXS_AUART=y
@ -138,11 +134,10 @@ CONFIG_RTC_DRV_STMP=y
CONFIG_DMADEVICES=y
CONFIG_MXS_DMA=y
CONFIG_IIO=y
CONFIG_IIO_SYSFS_TRIGGER=y
CONFIG_MXS_LRADC_ADC=y
CONFIG_IIO_SYSFS_TRIGGER=y
CONFIG_PWM=y
CONFIG_PWM_MXS=y
CONFIG_NVMEM=y
CONFIG_NVMEM_MXS_OCOTP=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
@ -172,8 +167,7 @@ CONFIG_FRAME_WARN=2048
CONFIG_UNUSED_SYMBOLS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_TIMER_STATS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_PROVE_LOCKING=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_STRICT_DEVMEM=y

96
arch/arm/configs/omap2plus_defconfig
View File

@ -50,7 +50,6 @@ CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_DRA7XX=y
CONFIG_PCI_DRA7XX_EP=y
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
@ -71,9 +70,10 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPUFREQ_DT=m
CONFIG_ARM_TI_CPUFREQ=y
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
CONFIG_ARM_TI_CPUFREQ=y
CONFIG_CPU_IDLE=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_BINFMT_MISC=y
CONFIG_PM_DEBUG=y
CONFIG_NET=y
@ -103,9 +103,11 @@ CONFIG_BT_HIDP=m
CONFIG_BT_HCIBTUSB=m
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
@ -232,7 +234,9 @@ CONFIG_INPUT_MISC=y
CONFIG_INPUT_CPCAP_PWRBUTTON=m
CONFIG_INPUT_TPS65218_PWRBUTTON=m
CONFIG_INPUT_TWL4030_PWRBUTTON=m
CONFIG_INPUT_UINPUT=m
CONFIG_INPUT_PALMAS_PWRBUTTON=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_SERIO=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
@ -244,9 +248,11 @@ CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_8250_OMAP=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_OMAP=y
CONFIG_SERIAL_OMAP_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
CONFIG_SPI_OMAP24XX=y
@ -291,6 +297,7 @@ CONFIG_OMAP_WATCHDOG=m
CONFIG_TWL4030_WATCHDOG=m
CONFIG_MFD_CPCAP=y
CONFIG_MFD_TI_AM335X_TSCADC=m
CONFIG_MFD_TI_LMU=m
CONFIG_MFD_PALMAS=y
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TI_LP873X=y
@ -314,40 +321,47 @@ CONFIG_REGULATOR_TPS65217=y
CONFIG_REGULATOR_TPS65218=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_REGULATOR_TWL4030=y
CONFIG_MEDIA_SUPPORT=m
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_RC_CORE=m
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_LIRC=y
CONFIG_RC_DEVICES=y
CONFIG_IR_SPI=m
CONFIG_IR_RX51=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_PWM_TX=m
CONFIG_MEDIA_SUPPORT=m
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_OMAP3=m
CONFIG_CEC_PLATFORM_DRIVERS=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_TVP5150=m
CONFIG_DRM=m
CONFIG_DRM_OMAP=m
CONFIG_OMAP5_DSS_HDMI=y
CONFIG_OMAP2_DSS_SDI=y
CONFIG_OMAP2_DSS_DSI=y
CONFIG_DRM_OMAP_ENCODER_OPA362=m
CONFIG_DRM_OMAP_ENCODER_TFP410=m
CONFIG_DRM_OMAP_ENCODER_TPD12S015=m
CONFIG_DRM_OMAP_CONNECTOR_DVI=m
CONFIG_DRM_OMAP_CONNECTOR_HDMI=m
CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m
CONFIG_DRM_OMAP_PANEL_DPI=m
CONFIG_DRM_OMAP_PANEL_DSI_CM=m
CONFIG_DRM_OMAP_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_OMAP_PANEL_LGPHILIPS_LB035Q02=m
CONFIG_DRM_OMAP_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_OMAP_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_TILCDC=m
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
CONFIG_FB_OMAP2=m
CONFIG_FB_OMAP5_DSS_HDMI=y
CONFIG_FB_OMAP2_DSS_SDI=y
CONFIG_FB_OMAP2_DSS_DSI=y
CONFIG_FB_OMAP2_ENCODER_TFP410=m
CONFIG_FB_OMAP2_ENCODER_TPD12S015=m
CONFIG_FB_OMAP2_CONNECTOR_DVI=m
CONFIG_FB_OMAP2_CONNECTOR_HDMI=m
CONFIG_FB_OMAP2_CONNECTOR_ANALOG_TV=m
CONFIG_FB_OMAP2_PANEL_DPI=m
CONFIG_FB_OMAP2_PANEL_DSI_CM=m
CONFIG_FB_OMAP2_PANEL_SONY_ACX565AKM=m
CONFIG_FB_OMAP2_PANEL_LGPHILIPS_LB035Q02=m
CONFIG_FB_OMAP2_PANEL_SHARP_LS037V7DW01=m
CONFIG_FB_OMAP2_PANEL_TPO_TD028TTEC1=m
CONFIG_FB_OMAP2_PANEL_TPO_TD043MTEA1=m
CONFIG_FB_OMAP2_PANEL_NEC_NL8048HL11=m
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
@ -356,11 +370,11 @@ CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_PANDORA=m
CONFIG_BACKLIGHT_GPIO=m
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_VERBOSE_PRINTK=y
@ -374,7 +388,9 @@ CONFIG_SND_OMAP_SOC_HDMI_AUDIO=m
CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
CONFIG_SND_SOC_CPCAP=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_HID_GENERIC=m
CONFIG_USB_HIDDEV=y
CONFIG_USB_KBD=m
@ -385,7 +401,6 @@ CONFIG_USB_MON=m
CONFIG_USB_XHCI_HCD=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_WDM=m
CONFIG_USB_ACM=m
CONFIG_USB_STORAGE=m
CONFIG_USB_MUSB_HDRC=m
@ -462,10 +477,16 @@ CONFIG_DMADEVICES=y
CONFIG_DMA_OMAP=y
CONFIG_TI_EDMA=y
CONFIG_OMAP_IOMMU=y
CONFIG_EXTCON=m
CONFIG_REMOTEPROC=m
CONFIG_OMAP_REMOTEPROC=m
CONFIG_WKUP_M3_RPROC=m
CONFIG_SOC_TI=y
CONFIG_AMX3_PM=m
CONFIG_WKUP_M3_IPC=m
CONFIG_EXTCON_PALMAS=m
CONFIG_EXTCON_USB_GPIO=m
CONFIG_TI_EMIF=m
CONFIG_TI_EMIF_SRAM=m
CONFIG_IIO=m
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
@ -480,6 +501,7 @@ CONFIG_PWM_TIEHRPWM=m
CONFIG_PWM_TWL=m
CONFIG_PWM_TWL_LED=m
CONFIG_PHY_CPCAP_USB=m
CONFIG_PHY_MAPPHONE_MDM6600=m
CONFIG_PHY_DM816X_USB=m
CONFIG_OMAP_USB2=m
CONFIG_TI_PIPE3=y
@ -494,7 +516,6 @@ CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CONFIGFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
@ -515,11 +536,18 @@ CONFIG_DEBUG_INFO_SPLIT=y
CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_PROVE_LOCKING=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_SECURITY=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_ARM_CRYPTO=y
CONFIG_CRYPTO_SHA1_ARM_NEON=m
CONFIG_CRYPTO_SHA256_ARM=m
CONFIG_CRYPTO_SHA512_ARM=m
CONFIG_CRYPTO_AES_ARM=m
CONFIG_CRYPTO_AES_ARM_BS=m
CONFIG_CRYPTO_GHASH_ARM_CE=m
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRC_CCITT=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
@ -528,13 +556,3 @@ CONFIG_LIBCRC32C=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_ARM_CRYPTO=y
CONFIG_CRYPTO_SHA1_ARM=m
CONFIG_CRYPTO_SHA1_ARM_NEON=m
CONFIG_CRYPTO_SHA256_ARM=m
CONFIG_CRYPTO_SHA512_ARM=m
CONFIG_CRYPTO_AES_ARM=m
CONFIG_CRYPTO_AES_ARM_BS=m
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_GHASH_ARM_CE=m

93
arch/arm/configs/oxnas_v6_defconfig Normal file
View File

@ -0,0 +1,93 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_CMDLINE_PARTITION=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_OXNAS=y
CONFIG_MACH_OX820=y
CONFIG_SMP=y
CONFIG_NR_CPUS=16
CONFIG_CMA=y
CONFIG_FORCE_MAX_ZONEORDER=12
CONFIG_SECCOMP=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_KEXEC=y
CONFIG_EFI=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_SIMPLE_PM_BUS=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_OXNAS=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_NETDEVICES=y
CONFIG_STMMAC_ETH=y
CONFIG_REALTEK_PHY=y
CONFIG_INPUT_EVDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_ARM_TIMER_SP804=y
CONFIG_EXT4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_UBIFS_FS=y
CONFIG_PSTORE=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_RAM=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y

3
arch/arm/configs/pxa3xx_defconfig
View File

@ -32,8 +32,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_PXA3xx=y
CONFIG_MTD_NAND_PXA3xx_BUILTIN=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=y

2
arch/arm/configs/pxa_defconfig
View File

@ -197,7 +197,7 @@ CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
CONFIG_MTD_NAND_SHARPSL=m
CONFIG_MTD_NAND_PXA3xx=m
CONFIG_MTD_NAND_MARVELL=m
CONFIG_MTD_NAND_CM_X270=m
CONFIG_MTD_NAND_TMIO=m
CONFIG_MTD_NAND_BRCMNAND=m

2
arch/arm/configs/raumfeld_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_NFTL=y
CONFIG_NFTL_RW=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_PXA3xx=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_ISL29003=y

21
arch/arm/configs/realview_defconfig
View File

@ -11,19 +11,17 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_REALVIEW=y
CONFIG_REALVIEW_DT=y
CONFIG_MACH_REALVIEW_EB=y
CONFIG_REALVIEW_EB_ARM1136=y
CONFIG_REALVIEW_EB_ARM1176=y
CONFIG_REALVIEW_EB_A9MP=y
CONFIG_REALVIEW_EB_ARM11MP=y
CONFIG_REALVIEW_EB_ARM11MP_REVB=y
CONFIG_MACH_REALVIEW_PB11MP=y
CONFIG_MACH_REALVIEW_PB1176=y
CONFIG_MACH_REALVIEW_PBA8=y
CONFIG_MACH_REALVIEW_PBX=y
CONFIG_SMP=y
CONFIG_AEABI=y
CONFIG_CMA=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M"
@ -46,7 +44,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ROM=y
CONFIG_MTD_PHYSMAP=y
CONFIG_ARM_CHARLCD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
@ -59,21 +57,21 @@ CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_VERSATILE=y
CONFIG_SPI=y
CONFIG_GPIOLIB=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_DRIVERS is not set
CONFIG_SND_ARMAACI=y
CONFIG_USB=y
@ -83,13 +81,14 @@ CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_VERSATILE=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_PL031=y
CONFIG_AUXDISPLAY=y
CONFIG_ARM_CHARLCD=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y

9
arch/arm/configs/shmobile_defconfig
View File

@ -5,8 +5,6 @@ CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_ARCH_RENESAS=y
@ -34,7 +32,6 @@ CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_NR_CPUS=8
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_CMA=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@ -104,9 +101,6 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=20
CONFIG_SERIAL_SH_SCI_CONSOLE=y
CONFIG_SERIAL_SH_SCI_DMA=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_DEMUX_PINCTRL=y
@ -120,6 +114,7 @@ CONFIG_SPI=y
CONFIG_SPI_RSPI=y
CONFIG_SPI_SH_MSIOF=y
CONFIG_SPI_SH_HSPI=y
CONFIG_PINCTRL_RZA1=y
CONFIG_GPIO_EM=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_PCF857X=y
@ -166,7 +161,6 @@ CONFIG_FB_SH_MOBILE_MERAM=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
@ -227,4 +221,5 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_ARM_UNWIND is not set

3
arch/arm/configs/stm32_defconfig
View File

@ -57,6 +57,8 @@ CONFIG_MFD_STMPE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
@ -71,6 +73,7 @@ CONFIG_STM32_MDMA=y
CONFIG_IIO=y
CONFIG_STM32_ADC_CORE=y
CONFIG_STM32_ADC=y
CONFIG_EXT3_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set

18
arch/arm/configs/versatile_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_VERSATILE=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_CMA=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=1f03 mem=32M"
@ -32,7 +33,9 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_RAM=y
CONFIG_EEPROM_LEGACY=m
CONFIG_NETDEVICES=y
@ -47,21 +50,22 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_VERSATILE=y
CONFIG_SPI=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
CONFIG_MFD_SYSCON=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_ARM_VERSATILE=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=m
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_ARMAACI=m
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y

7
arch/arm/include/debug/exynos.S
View File

@ -1,11 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/
/* pull in the relevant register and map files. */

10
arch/arm/include/debug/samsung.S
View File

@ -1,13 +1,9 @@
/* arch/arm/plat-samsung/include/plat/debug-macro.S
*
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2005, 2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/
#include <linux/serial_s3c.h>

14
arch/arm/mach-at91/Kconfig
View File

@ -1,5 +1,5 @@
menuconfig ARCH_AT91
bool "Atmel SoCs"
bool "AT91/Microchip SoCs"
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7
select COMMON_CLK_AT91
@ -13,7 +13,7 @@ config SOC_SAMV7
select COMMON_CLK_AT91
select PINCTRL_AT91
help
Select this if you are using an SoC from Atmel's SAME7, SAMS7 or SAMV7
Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
families.
config SOC_SAMA5D2
@ -29,7 +29,7 @@ config SOC_SAMA5D2
select HAVE_AT91_AUDIO_PLL
select PINCTRL_AT91PIO4
help
Select this if ou are using one of Atmel's SAMA5D2 family SoC.
Select this if ou are using one of Microchip's SAMA5D2 family SoC.
config SOC_SAMA5D3
bool "SAMA5D3 family"
@ -41,7 +41,7 @@ config SOC_SAMA5D3
select HAVE_AT91_USB_CLK
select PINCTRL_AT91
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
Select this if you are using one of Microchip's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
config SOC_SAMA5D4
@ -56,7 +56,7 @@ config SOC_SAMA5D4
select HAVE_AT91_H32MX
select PINCTRL_AT91
help
Select this if you are using one of Atmel's SAMA5D4 family SoC.
Select this if you are using one of Microchip's SAMA5D4 family SoC.
config SOC_AT91RM9200
bool "AT91RM9200"
@ -70,7 +70,7 @@ config SOC_AT91RM9200
select SOC_SAM_V4_V5
select SRAM if PM
help
Select this if you are using Atmel's AT91RM9200 SoC.
Select this if you are using Microchip's AT91RM9200 SoC.
config SOC_AT91SAM9
bool "AT91SAM9"
@ -88,7 +88,7 @@ config SOC_AT91SAM9
select SOC_SAM_V4_V5
select SRAM if PM
help
Select this if you are using one of those Atmel SoC:
Select this if you are using one of those Microchip SoC:
AT91SAM9260
AT91SAM9261
AT91SAM9263

35
arch/arm/mach-davinci/board-da830-evm.c
View File

@ -239,20 +239,6 @@ static inline void da830_evm_init_mmc(void)
}
}
/*
* UI board NAND/NOR flashes only use 8-bit data bus.
*/
static const short da830_evm_emif25_pins[] = {
DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
-1
};
#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
#ifdef CONFIG_DA830_UI_NAND
@ -357,6 +343,20 @@ static struct platform_device da830_evm_nand_device = {
.resource = da830_evm_nand_resources,
};
/*
* UI board NAND/NOR flashes only use 8-bit data bus.
*/
static const short da830_evm_emif25_pins[] = {
DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
-1
};
static inline void da830_evm_init_nand(int mux_mode)
{
int ret;
@ -551,10 +551,6 @@ static __init void da830_evm_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
int ret;
ret = da8xx_register_cfgchip();
if (ret)
pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
ret = da830_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@ -638,9 +634,8 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
.atag_offset = 0x100,
.map_io = da830_evm_map_io,
.init_irq = cp_intc_init,
.init_time = davinci_timer_init,
.init_time = da830_init_time,
.init_machine = da830_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = da8xx_restart,
MACHINE_END

7
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -1334,10 +1334,6 @@ static __init void da850_evm_init(void)
{
int ret;
ret = da8xx_register_cfgchip();
if (ret)
pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
ret = da850_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@ -1481,10 +1477,9 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
.atag_offset = 0x100,
.map_io = da850_evm_map_io,
.init_irq = cp_intc_init,
.init_time = davinci_timer_init,
.init_time = da850_init_time,
.init_machine = da850_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = da8xx_restart,
.reserve = da8xx_rproc_reserve_cma,
MACHINE_END

3
arch/arm/mach-davinci/board-dm355-evm.c
View File

@ -427,9 +427,8 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
.atag_offset = 0x100,
.map_io = dm355_evm_map_io,
.init_irq = davinci_irq_init,
.init_time = davinci_timer_init,
.init_time = dm355_init_time,
.init_machine = dm355_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END

3
arch/arm/mach-davinci/board-dm355-leopard.c
View File

@ -271,9 +271,8 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
.atag_offset = 0x100,
.map_io = dm355_leopard_map_io,
.init_irq = davinci_irq_init,
.init_time = davinci_timer_init,
.init_time = dm355_init_time,
.init_machine = dm355_leopard_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END

3
arch/arm/mach-davinci/board-dm365-evm.c
View File

@ -774,10 +774,9 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
.atag_offset = 0x100,
.map_io = dm365_evm_map_io,
.init_irq = davinci_irq_init,
.init_time = davinci_timer_init,
.init_time = dm365_init_time,
.init_machine = dm365_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END

3
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -828,9 +828,8 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
.atag_offset = 0x100,
.map_io = davinci_evm_map_io,
.init_irq = davinci_irq_init,
.init_time = davinci_timer_init,
.init_time = dm644x_init_time,
.init_machine = davinci_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END

21
arch/arm/mach-davinci/board-dm646x-evm.c
View File

@ -44,10 +44,8 @@
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/serial.h>
#include <mach/clock.h>
#include "davinci.h"
#include "clock.h"
#define NAND_BLOCK_SIZE SZ_128K
@ -716,14 +714,23 @@ static void __init evm_init_i2c(void)
}
#endif
#define DM646X_REF_FREQ 27000000
#define DM646X_AUX_FREQ 24000000
#define DM6467T_EVM_REF_FREQ 33000000
static void __init davinci_map_io(void)
{
dm646x_init();
}
if (machine_is_davinci_dm6467tevm())
davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
static void __init dm646x_evm_init_time(void)
{
dm646x_init_time(DM646X_REF_FREQ, DM646X_AUX_FREQ);
}
static void __init dm6467t_evm_init_time(void)
{
dm646x_init_time(DM6467T_EVM_REF_FREQ, DM646X_AUX_FREQ);
}
#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
@ -797,21 +804,19 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
.init_time = davinci_timer_init,
.init_time = dm646x_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END
MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
.init_time = davinci_timer_init,
.init_time = dm6467t_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END

7
arch/arm/mach-davinci/board-mityomapl138.c
View File

@ -502,10 +502,6 @@ static void __init mityomapl138_init(void)
{
int ret;
ret = da8xx_register_cfgchip();
if (ret)
pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
/* for now, no special EDMA channels are reserved */
ret = da850_register_edma(NULL);
if (ret)
@ -570,9 +566,8 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
.atag_offset = 0x100,
.map_io = mityomapl138_map_io,
.init_irq = cp_intc_init,
.init_time = davinci_timer_init,
.init_time = da850_init_time,
.init_machine = mityomapl138_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = da8xx_restart,
MACHINE_END

3
arch/arm/mach-davinci/board-neuros-osd2.c
View File

@ -227,9 +227,8 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
.atag_offset = 0x100,
.map_io = davinci_ntosd2_map_io,
.init_irq = davinci_irq_init,
.init_time = davinci_timer_init,
.init_time = dm644x_init_time,
.init_machine = davinci_ntosd2_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END

7
arch/arm/mach-davinci/board-omapl138-hawk.c
View File

@ -281,10 +281,6 @@ static __init void omapl138_hawk_init(void)
{
int ret;
ret = da8xx_register_cfgchip();
if (ret)
pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
ret = da850_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@ -334,10 +330,9 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
.atag_offset = 0x100,
.map_io = omapl138_hawk_map_io,
.init_irq = cp_intc_init,
.init_time = davinci_timer_init,
.init_time = da850_init_time,
.init_machine = omapl138_hawk_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = da8xx_restart,
.reserve = da8xx_rproc_reserve_cma,
MACHINE_END

3
arch/arm/mach-davinci/board-sffsdr.c
View File

@ -150,9 +150,8 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
.atag_offset = 0x100,
.map_io = davinci_sffsdr_map_io,
.init_irq = davinci_irq_init,
.init_time = davinci_timer_init,
.init_time = dm644x_init_time,
.init_machine = davinci_sffsdr_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = davinci_restart,
MACHINE_END

3
arch/arm/mach-davinci/clock.h
View File

@ -135,9 +135,6 @@ int davinci_clk_reset(struct clk *clk, bool reset);
void davinci_clk_enable(struct clk *clk);
void davinci_clk_disable(struct clk *clk);
extern struct platform_device davinci_wdt_device;
extern void davinci_watchdog_reset(struct platform_device *);
#endif
#endif

9
arch/arm/mach-davinci/da830.c
View File

@ -1200,7 +1200,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
.ids = da830_ids,
.ids_num = ARRAY_SIZE(da830_ids),
.cpu_clks = da830_clks,
.psc_bases = da830_psc_bases,
.psc_bases_num = ARRAY_SIZE(da830_psc_bases),
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
@ -1220,6 +1219,10 @@ void __init da830_init(void)
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
davinci_clk_init(davinci_soc_info_da830.cpu_clks);
}
void __init da830_init_time(void)
{
davinci_clk_init(da830_clks);
davinci_timer_init();
}

9
arch/arm/mach-davinci/da850.c
View File

@ -1353,7 +1353,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
.ids = da850_ids,
.ids_num = ARRAY_SIZE(da850_ids),
.cpu_clks = da850_clks,
.psc_bases = da850_psc_bases,
.psc_bases_num = ARRAY_SIZE(da850_psc_bases),
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
@ -1392,6 +1391,10 @@ void __init da850_init(void)
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
davinci_clk_init(davinci_soc_info_da850.cpu_clks);
}
void __init da850_init_time(void)
{
davinci_clk_init(da850_clks);
davinci_timer_init();
}

3
arch/arm/mach-davinci/da8xx-dt.c
View File

@ -96,11 +96,10 @@ static const char *const da850_boards_compat[] __initconst = {
DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
.map_io = da850_init,
.init_time = davinci_timer_init,
.init_time = da850_init_time,
.init_machine = da850_init_machine,
.dt_compat = da850_boards_compat,
.init_late = davinci_init_late,
.restart = da8xx_restart,
MACHINE_END
#endif

4
arch/arm/mach-davinci/davinci.h
View File

@ -83,6 +83,7 @@ int davinci_init_wdt(void);
/* DM355 function declarations */
void dm355_init(void);
void dm355_init_time(void);
void dm355_init_spi0(unsigned chipselect_mask,
const struct spi_board_info *info, unsigned len);
void dm355_init_asp1(u32 evt_enable);
@ -91,6 +92,7 @@ int dm355_gpio_register(void);
/* DM365 function declarations */
void dm365_init(void);
void dm365_init_time(void);
void dm365_init_asp(void);
void dm365_init_vc(void);
void dm365_init_ks(struct davinci_ks_platform_data *pdata);
@ -102,12 +104,14 @@ int dm365_gpio_register(void);
/* DM644x function declarations */
void dm644x_init(void);
void dm644x_init_time(void);
void dm644x_init_asp(void);
int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
int dm644x_gpio_register(void);
/* DM646x function declarations */
void dm646x_init(void);
void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
void dm646x_init_mcasp0(struct snd_platform_data *pdata);
void dm646x_init_mcasp1(struct snd_platform_data *pdata);
int dm646x_init_edma(struct edma_rsv_info *rsv);

59
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -11,7 +11,6 @@
* (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/platform_data/syscon.h>
#include <linux/platform_device.h>
#include <linux/dma-contiguous.h>
#include <linux/serial_8250.h>
@ -371,19 +370,6 @@ static struct platform_device da8xx_wdt_device = {
.resource = da8xx_watchdog_resources,
};
void da8xx_restart(enum reboot_mode mode, const char *cmd)
{
struct device *dev;
dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
if (!dev) {
pr_err("%s: failed to find watchdog device\n", __func__);
return;
}
davinci_watchdog_reset(to_platform_device(dev));
}
int __init da8xx_register_watchdog(void)
{
return platform_device_register(&da8xx_wdt_device);
@ -1118,29 +1104,30 @@ int __init da850_register_sata(unsigned long refclkpn)
}
#endif
static struct syscon_platform_data da8xx_cfgchip_platform_data = {
.label = "cfgchip",
static struct regmap *da8xx_cfgchip;
static const struct regmap_config da8xx_cfgchip_config __initconst = {
.name = "cfgchip",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
};
static struct resource da8xx_cfgchip_resources[] = {
{
.start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG,
.end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device da8xx_cfgchip_device = {
.name = "syscon",
.id = -1,
.dev = {
.platform_data = &da8xx_cfgchip_platform_data,
},
.num_resources = ARRAY_SIZE(da8xx_cfgchip_resources),
.resource = da8xx_cfgchip_resources,
};
int __init da8xx_register_cfgchip(void)
/**
* da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
*
* This is for use on non-DT boards only. For DT boards, use
* syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
*
* Returns: Pointer to the CFGCHIP regmap or negative error code.
*/
struct regmap * __init da8xx_get_cfgchip(void)
{
return platform_device_register(&da8xx_cfgchip_device);
if (IS_ERR_OR_NULL(da8xx_cfgchip))
da8xx_cfgchip = regmap_init_mmio(NULL,
DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
&da8xx_cfgchip_config);
return da8xx_cfgchip;
}

7
arch/arm/mach-davinci/devices.c
View File

@ -282,18 +282,13 @@ static struct resource wdt_resources[] = {
},
};
struct platform_device davinci_wdt_device = {
static struct platform_device davinci_wdt_device = {
.name = "davinci-wdt",
.id = -1,
.num_resources = ARRAY_SIZE(wdt_resources),
.resource = wdt_resources,
};
void davinci_restart(enum reboot_mode mode, const char *cmd)
{
davinci_watchdog_reset(&davinci_wdt_device);
}
int davinci_init_wdt(void)
{
return platform_device_register(&davinci_wdt_device);

8
arch/arm/mach-davinci/dm355.c
View File

@ -1012,7 +1012,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
.jtag_id_reg = 0x01c40028,
.ids = dm355_ids,
.ids_num = ARRAY_SIZE(dm355_ids),
.cpu_clks = dm355_clks,
.psc_bases = dm355_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@ -1043,7 +1042,12 @@ void __init dm355_init(void)
{
davinci_common_init(&davinci_soc_info_dm355);
davinci_map_sysmod();
davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
}
void __init dm355_init_time(void)
{
davinci_clk_init(dm355_clks);
davinci_timer_init();
}
int __init dm355_init_video(struct vpfe_config *vpfe_cfg,

8
arch/arm/mach-davinci/dm365.c
View File

@ -1116,7 +1116,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
.jtag_id_reg = 0x01c40028,
.ids = dm365_ids,
.ids_num = ARRAY_SIZE(dm365_ids),
.cpu_clks = dm365_clks,
.psc_bases = dm365_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@ -1168,7 +1167,12 @@ void __init dm365_init(void)
{
davinci_common_init(&davinci_soc_info_dm365);
davinci_map_sysmod();
davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
}
void __init dm365_init_time(void)
{
davinci_clk_init(dm365_clks);
davinci_timer_init();
}
static struct resource dm365_vpss_resources[] = {

8
arch/arm/mach-davinci/dm644x.c
View File

@ -905,7 +905,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
.jtag_id_reg = 0x01c40028,
.ids = dm644x_ids,
.ids_num = ARRAY_SIZE(dm644x_ids),
.cpu_clks = dm644x_clks,
.psc_bases = dm644x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@ -931,7 +930,12 @@ void __init dm644x_init(void)
{
davinci_common_init(&davinci_soc_info_dm644x);
davinci_map_sysmod();
davinci_clk_init(davinci_soc_info_dm644x.cpu_clks);
}
void __init dm644x_init_time(void)
{
davinci_clk_init(dm644x_clks);
davinci_timer_init();
}
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,

22
arch/arm/mach-davinci/dm646x.c
View File

@ -39,12 +39,6 @@
#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
BIT_MASK(8))
/*
* Device specific clocks
*/
#define DM646X_REF_FREQ 27000000
#define DM646X_AUX_FREQ 24000000
#define DM646X_EMAC_BASE 0x01c80000
#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
#define DM646X_EMAC_CNTRL_OFFSET 0x0000
@ -64,13 +58,12 @@ static struct pll_data pll2_data = {
static struct clk ref_clk = {
.name = "ref_clk",
.rate = DM646X_REF_FREQ,
.set_rate = davinci_simple_set_rate,
/* rate is initialized in dm646x_init_time() */
};
static struct clk aux_clkin = {
.name = "aux_clkin",
.rate = DM646X_AUX_FREQ,
/* rate is initialized in dm646x_init_time() */
};
static struct clk pll1_clk = {
@ -888,7 +881,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
.jtag_id_reg = 0x01c40028,
.ids = dm646x_ids,
.ids_num = ARRAY_SIZE(dm646x_ids),
.cpu_clks = dm646x_clks,
.psc_bases = dm646x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@ -956,7 +948,15 @@ void __init dm646x_init(void)
{
davinci_common_init(&davinci_soc_info_dm646x);
davinci_map_sysmod();
davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
}
void __init dm646x_init_time(unsigned long ref_clk_rate,
unsigned long aux_clkin_rate)
{
ref_clk.rate = ref_clk_rate;
aux_clkin.rate = aux_clkin_rate;
davinci_clk_init(dm646x_clks);
davinci_timer_init();
}
static int __init dm646x_init_devices(void)

2
arch/arm/mach-davinci/include/mach/common.h
View File

@ -53,7 +53,6 @@ struct davinci_soc_info {
u32 jtag_id_reg;
struct davinci_id *ids;
unsigned long ids_num;
struct clk_lookup *cpu_clks;
u32 *psc_bases;
unsigned long psc_bases_num;
u32 pinmux_base;
@ -81,7 +80,6 @@ extern struct davinci_soc_info davinci_soc_info;
extern void davinci_common_init(const struct davinci_soc_info *soc_info);
extern void davinci_init_ide(void);
void davinci_restart(enum reboot_mode mode, const char *cmd);
void davinci_init_late(void);
#ifdef CONFIG_DAVINCI_RESET_CLOCKS

7
arch/arm/mach-davinci/include/mach/da8xx.h
View File

@ -18,6 +18,7 @@
#include <linux/spi/spi.h>
#include <linux/platform_data/davinci_asp.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/videodev2.h>
#include <mach/serial.h>
@ -87,7 +88,10 @@ extern unsigned int da850_max_speed;
#define DA8XX_ARM_RAM_BASE 0xffff0000
void da830_init(void);
void da830_init_time(void);
void da850_init(void);
void da850_init_time(void);
int da830_register_edma(struct edma_rsv_info *rsv);
int da850_register_edma(struct edma_rsv_info *rsv[2]);
@ -118,12 +122,11 @@ int da850_register_vpif_display
(struct vpif_display_config *display_config);
int da850_register_vpif_capture
(struct vpif_capture_config *capture_config);
void da8xx_restart(enum reboot_mode mode, const char *cmd);
void da8xx_rproc_reserve_cma(void);
int da8xx_register_rproc(void);
int da850_register_gpio(void);
int da830_register_gpio(void);
int da8xx_register_cfgchip(void);
struct regmap *da8xx_get_cfgchip(void);
extern struct platform_device da8xx_serial_device[];
extern struct emac_platform_data da8xx_emac_pdata;

57
arch/arm/mach-davinci/time.c
View File

@ -80,13 +80,6 @@ enum {
#define TGCR_UNRESET 0x1
#define TGCR_RESET_MASK 0x3
#define WDTCR_WDEN_SHIFT 14
#define WDTCR_WDEN_DISABLE 0x0
#define WDTCR_WDEN_ENABLE 0x1
#define WDTCR_WDKEY_SHIFT 16
#define WDTCR_WDKEY_SEQ0 0xa5c6
#define WDTCR_WDKEY_SEQ1 0xda7e
struct timer_s {
char *name;
unsigned int id;
@ -409,53 +402,3 @@ void __init davinci_timer_init(void)
for (i=0; i< ARRAY_SIZE(timers); i++)
timer32_config(&timers[i]);
}
/* reset board using watchdog timer */
void davinci_watchdog_reset(struct platform_device *pdev)
{
u32 tgcr, wdtcr;
void __iomem *base;
struct clk *wd_clk;
base = ioremap(pdev->resource[0].start, SZ_4K);
if (WARN_ON(!base))
return;
wd_clk = clk_get(&pdev->dev, NULL);
if (WARN_ON(IS_ERR(wd_clk)))
return;
clk_prepare_enable(wd_clk);
/* disable, internal clock source */
__raw_writel(0, base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
tgcr = 0;
__raw_writel(tgcr, base + TGCR);
tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
__raw_writel(tgcr, base + TGCR);
/* clear counter and period regs */
__raw_writel(0, base + TIM12);
__raw_writel(0, base + TIM34);
__raw_writel(0, base + PRD12);
__raw_writel(0, base + PRD34);
/* put watchdog in pre-active state */
wdtcr = __raw_readl(base + WDTCR);
wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
__raw_writel(wdtcr, base + WDTCR);
/* put watchdog in active state */
wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
__raw_writel(wdtcr, base + WDTCR);
/* write an invalid value to the WDKEY field to trigger
* a watchdog reset */
wdtcr = 0x00004000;
__raw_writel(wdtcr, base + WDTCR);
}

18
arch/arm/mach-davinci/usb-da8xx.c
View File

@ -8,6 +8,7 @@
#include <linux/init.h>
#include <linux/mfd/da8xx-cfgchip.h>
#include <linux/phy/phy.h>
#include <linux/platform_data/phy-da8xx-usb.h>
#include <linux/platform_data/usb-davinci.h>
#include <linux/platform_device.h>
#include <linux/usb/musb.h>
@ -25,6 +26,8 @@
static struct clk *usb20_clk;
static struct da8xx_usb_phy_platform_data da8xx_usb_phy_pdata;
static struct platform_device da8xx_usb_phy = {
.name = "da8xx-usb-phy",
.id = -1,
@ -35,11 +38,14 @@ static struct platform_device da8xx_usb_phy = {
* registered yet.
*/
.init_name = "da8xx-usb-phy",
.platform_data = &da8xx_usb_phy_pdata,
},
};
int __init da8xx_register_usb_phy(void)
{
da8xx_usb_phy_pdata.cfgchip = da8xx_get_cfgchip();
return platform_device_register(&da8xx_usb_phy);
}
@ -256,14 +262,14 @@ static int usb20_phy_clk_set_parent(struct clk *clk, struct clk *parent)
}
static struct clk usb20_phy_clk = {
.name = "usb20_phy",
.name = "usb0_clk48",
.clk_enable = usb20_phy_clk_enable,
.clk_disable = usb20_phy_clk_disable,
.set_parent = usb20_phy_clk_set_parent,
};
static struct clk_lookup usb20_phy_clk_lookup =
CLK("da8xx-usb-phy", "usb20_phy", &usb20_phy_clk);
CLK("da8xx-usb-phy", "usb0_clk48", &usb20_phy_clk);
/**
* da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock
@ -320,18 +326,18 @@ static int usb11_phy_clk_set_parent(struct clk *clk, struct clk *parent)
}
static struct clk usb11_phy_clk = {
.name = "usb11_phy",
.name = "usb1_clk48",
.set_parent = usb11_phy_clk_set_parent,
};
static struct clk_lookup usb11_phy_clk_lookup =
CLK("da8xx-usb-phy", "usb11_phy", &usb11_phy_clk);
CLK("da8xx-usb-phy", "usb1_clk48", &usb11_phy_clk);
/**
* da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock
*
* @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
* or "usb20_phy" if false.
* or "usb0_clk48" if false.
*/
int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
{
@ -341,7 +347,7 @@ int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
if (use_usb_refclkin)
parent = clk_get(NULL, "usb_refclkin");
else
parent = clk_get(&da8xx_usb_phy.dev, "usb20_phy");
parent = clk_get(&da8xx_usb_phy.dev, "usb0_clk48");
if (IS_ERR(parent))
return PTR_ERR(parent);

3
arch/arm/mach-exynos/exynos.c
View File

@ -192,7 +192,8 @@ static void __init exynos_dt_machine_init(void)
#endif
if (of_machine_is_compatible("samsung,exynos4210") ||
(of_machine_is_compatible("samsung,exynos4412") &&
of_machine_is_compatible("samsung,trats2")) ||
(of_machine_is_compatible("samsung,trats2") ||
of_machine_is_compatible("samsung,midas"))) ||
of_machine_is_compatible("samsung,exynos3250") ||
of_machine_is_compatible("samsung,exynos5250"))
platform_device_register(&exynos_cpuidle);

8
arch/arm/mach-exynos/pm.c
View File

@ -163,7 +163,7 @@ void exynos_enter_aftr(void)
exynos_pm_central_suspend();
if (of_machine_is_compatible("samsung,exynos4412")) {
if (soc_is_exynos4412()) {
/* Setting SEQ_OPTION register */
pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
S5P_CENTRAL_SEQ_OPTION);
@ -271,11 +271,7 @@ static int exynos_cpu0_enter_aftr(void)
goto fail;
call_firmware_op(cpu_boot, 1);
if (soc_is_exynos3250())
dsb_sev();
else
arch_send_wakeup_ipi_mask(cpumask_of(1));
dsb_sev();
}
}
fail:

22
arch/arm/mach-imx/Kconfig
View File

@ -32,18 +32,6 @@ config MXC_DEBUG_BOARD
data/address de-multiplexing and decode, signal level shift,
interrupt control and various board functions.
config HAVE_EPIT
bool
config MXC_USE_EPIT
bool "Use EPIT instead of GPT"
depends on HAVE_EPIT
help
Use EPIT as the system timer on systems that have it. Normally you
don't have a reason to do so as the EPIT has the same features and
uses the same clocks as the GPT. Anyway, on some systems the GPT
may be in use for other purposes.
config HAVE_IMX_ANATOP
bool
@ -85,7 +73,6 @@ config SOC_IMX31
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
select HAVE_EPIT
select MXC_AVIC
select PINCTRL_IMX35
@ -482,7 +469,7 @@ config SOC_IMX53
config SOC_IMX6
bool
select ARM_CPU_SUSPEND if PM
select ARM_CPU_SUSPEND if (PM || CPU_IDLE)
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select ARM_GIC
@ -512,6 +499,13 @@ config SOC_IMX6SL
help
This enables support for Freescale i.MX6 SoloLite processor.
config SOC_IMX6SLL
bool "i.MX6 SoloLiteLite support"
select SOC_IMX6
help
This enables support for Freescale i.MX6 SoloLiteLite processor.
config SOC_IMX6SX
bool "i.MX6 SoloX support"
select PINCTRL_IMX6SX

3
arch/arm/mach-imx/Makefile
View File

@ -20,13 +20,13 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
obj-$(CONFIG_MXC_TZIC) += tzic.o
obj-$(CONFIG_MXC_AVIC) += avic.o
obj-$(CONFIG_MXC_USE_EPIT) += epit.o
obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o
endif
@ -78,6 +78,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
endif
obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o

58
arch/arm/mach-imx/anatop.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@ -116,6 +117,7 @@ void __init imx_init_revision_from_anatop(void)
unsigned int revision;
u32 digprog;
u16 offset = ANADIG_DIGPROG;
u8 major_part, minor_part;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
anatop_base = of_iomap(np, 0);
@ -127,45 +129,25 @@ void __init imx_init_revision_from_anatop(void)
digprog = readl_relaxed(anatop_base + offset);
iounmap(anatop_base);
switch (digprog & 0xff) {
case 0:
/*
* For i.MX6QP, most of the code for i.MX6Q can be resued,
* so internally, we identify it as i.MX6Q Rev 2.0
*/
if (digprog >> 8 & 0x01)
revision = IMX_CHIP_REVISION_2_0;
else
revision = IMX_CHIP_REVISION_1_0;
break;
case 1:
revision = IMX_CHIP_REVISION_1_1;
break;
case 2:
revision = IMX_CHIP_REVISION_1_2;
break;
case 3:
revision = IMX_CHIP_REVISION_1_3;
break;
case 4:
revision = IMX_CHIP_REVISION_1_4;
break;
case 5:
/*
* i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
* as 'D' in Part Number last character.
*/
revision = IMX_CHIP_REVISION_1_5;
break;
default:
/*
* Fail back to return raw register value instead of 0xff.
* It will be easy to know version information in SOC if it
* can't be recognized by known version. And some chip's (i.MX7D)
* digprog value match linux version format, so it needn't map
* again and we can use register value directly.
*/
/*
* On i.MX7D digprog value match linux version format, so
* it needn't map again and we can use register value directly.
*/
if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {
revision = digprog & 0xff;
} else {
/*
* MAJOR: [15:8], the major silicon revison;
* MINOR: [7: 0], the minor silicon revison;
*
* please refer to the i.MX RM for the detailed
* silicon revison bit define.
* format the major part and minor part to match the
* linux kernel soc version format.
*/
major_part = (digprog >> 8) & 0xf;
minor_part = digprog & 0xf;
revision = ((major_part + 1) << 4) | minor_part;
}
mxc_set_cpu_type(digprog >> 16 & 0xff);

37
arch/arm/mach-imx/avic.c
View File

@ -22,6 +22,7 @@
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
@ -51,7 +52,12 @@
#define AVIC_NUM_IRQS 64
/* low power interrupt mask registers */
#define MX25_CCM_LPIMR0 0x68
#define MX25_CCM_LPIMR1 0x6C
static void __iomem *avic_base;
static void __iomem *mx25_ccm_base;
static struct irq_domain *domain;
#ifdef CONFIG_FIQ
@ -93,6 +99,18 @@ static void avic_irq_suspend(struct irq_data *d)
avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
imx_writel(gc->wake_active, avic_base + ct->regs.mask);
if (mx25_ccm_base) {
u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
/*
* The interrupts which are still enabled will be used as wakeup
* sources. Allow those interrupts in low-power mode.
* The LPIMR registers use 0 to allow an interrupt, the AVIC
* registers use 1.
*/
imx_writel(~gc->wake_active, mx25_ccm_base + offs);
}
}
static void avic_irq_resume(struct irq_data *d)
@ -102,6 +120,13 @@ static void avic_irq_resume(struct irq_data *d)
int idx = d->hwirq >> 5;
imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
if (mx25_ccm_base) {
u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
imx_writel(0xffffffff, mx25_ccm_base + offs);
}
}
#else
@ -158,6 +183,18 @@ void __init mxc_init_irq(void __iomem *irqbase)
avic_base = irqbase;
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
mx25_ccm_base = of_iomap(np, 0);
if (mx25_ccm_base) {
/*
* By default, we mask all interrupts. We set the actual mask
* before we go into low-power mode.
*/
imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);
imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);
}
/* put the AVIC into the reset value with
* all interrupts disabled
*/

3
arch/arm/mach-imx/cpu.c
View File

@ -135,6 +135,9 @@ struct device * __init imx_soc_device_init(void)
case MXC_CPU_IMX6ULL:
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX6SLL:
soc_id = "i.MX6SLL";
break;
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;

7
arch/arm/mach-imx/cpuidle-imx6sl.c
View File

@ -12,6 +12,7 @@
#include "common.h"
#include "cpuidle.h"
#include "hardware.h"
static int imx6sl_enter_wait(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
@ -21,9 +22,11 @@ static int imx6sl_enter_wait(struct cpuidle_device *dev,
* Software workaround for ERR005311, see function
* description for details.
*/
imx6sl_set_wait_clk(true);
if (cpu_is_imx6sl())
imx6sl_set_wait_clk(true);
cpu_do_idle();
imx6sl_set_wait_clk(false);
if (cpu_is_imx6sl())
imx6sl_set_wait_clk(false);
imx6_set_lpm(WAIT_CLOCKED);
return index;

1
arch/arm/mach-imx/cpuidle-imx6sx.c
View File

@ -89,6 +89,7 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = {
*/
.exit_latency = 300,
.target_residency = 500,
.flags = CPUIDLE_FLAG_TIMER_STOP,
.enter = imx6sx_enter_wait,
.name = "LOW-POWER-IDLE",
.desc = "ARM power off",

228
arch/arm/mach-imx/epit.c
View File

@ -1,228 +0,0 @@
/*
* linux/arch/arm/plat-mxc/epit.c
*
* Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#define EPITCR 0x00
#define EPITSR 0x04
#define EPITLR 0x08
#define EPITCMPR 0x0c
#define EPITCNR 0x10
#define EPITCR_EN (1 << 0)
#define EPITCR_ENMOD (1 << 1)
#define EPITCR_OCIEN (1 << 2)
#define EPITCR_RLD (1 << 3)
#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
#define EPITCR_SWR (1 << 16)
#define EPITCR_IOVW (1 << 17)
#define EPITCR_DBGEN (1 << 18)
#define EPITCR_WAITEN (1 << 19)
#define EPITCR_RES (1 << 20)
#define EPITCR_STOPEN (1 << 21)
#define EPITCR_OM_DISCON (0 << 22)
#define EPITCR_OM_TOGGLE (1 << 22)
#define EPITCR_OM_CLEAR (2 << 22)
#define EPITCR_OM_SET (3 << 22)
#define EPITCR_CLKSRC_OFF (0 << 24)
#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
#define EPITCR_CLKSRC_REF_HIGH (1 << 24)
#define EPITCR_CLKSRC_REF_LOW (3 << 24)
#define EPITSR_OCIF (1 << 0)
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <asm/mach/time.h>
#include "common.h"
#include "hardware.h"
static struct clock_event_device clockevent_epit;
static void __iomem *timer_base;
static inline void epit_irq_disable(void)
{
u32 val;
val = imx_readl(timer_base + EPITCR);
val &= ~EPITCR_OCIEN;
imx_writel(val, timer_base + EPITCR);
}
static inline void epit_irq_enable(void)
{
u32 val;
val = imx_readl(timer_base + EPITCR);
val |= EPITCR_OCIEN;
imx_writel(val, timer_base + EPITCR);
}
static void epit_irq_acknowledge(void)
{
imx_writel(EPITSR_OCIF, timer_base + EPITSR);
}
static int __init epit_clocksource_init(struct clk *timer_clk)
{
unsigned int c = clk_get_rate(timer_clk);
return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32,
clocksource_mmio_readl_down);
}
/* clock event */
static int epit_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
unsigned long tcmp;
tcmp = imx_readl(timer_base + EPITCNR);
imx_writel(tcmp - evt, timer_base + EPITCMPR);
return 0;
}
/* Left event sources disabled, no more interrupts appear */
static int epit_shutdown(struct clock_event_device *evt)
{
unsigned long flags;
/*
* The timer interrupt generation is disabled at least
* for enough time to call epit_set_next_event()
*/
local_irq_save(flags);
/* Disable interrupt in GPT module */
epit_irq_disable();
/* Clear pending interrupt */
epit_irq_acknowledge();
local_irq_restore(flags);
return 0;
}
static int epit_set_oneshot(struct clock_event_device *evt)
{
unsigned long flags;
/*
* The timer interrupt generation is disabled at least
* for enough time to call epit_set_next_event()
*/
local_irq_save(flags);
/* Disable interrupt in GPT module */
epit_irq_disable();
/* Clear pending interrupt, only while switching mode */
if (!clockevent_state_oneshot(evt))
epit_irq_acknowledge();
/*
* Do not put overhead of interrupt enable/disable into
* epit_set_next_event(), the core has about 4 minutes
* to call epit_set_next_event() or shutdown clock after
* mode switching
*/
epit_irq_enable();
local_irq_restore(flags);
return 0;
}
/*
* IRQ handler for the timer
*/
static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &clockevent_epit;
epit_irq_acknowledge();
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction epit_timer_irq = {
.name = "i.MX EPIT Timer Tick",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = epit_timer_interrupt,
};
static struct clock_event_device clockevent_epit = {
.name = "epit",
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_state_shutdown = epit_shutdown,
.tick_resume = epit_shutdown,
.set_state_oneshot = epit_set_oneshot,
.set_next_event = epit_set_next_event,
.rating = 200,
};
static int __init epit_clockevent_init(struct clk *timer_clk)
{
clockevent_epit.cpumask = cpumask_of(0);
clockevents_config_and_register(&clockevent_epit,
clk_get_rate(timer_clk),
0x800, 0xfffffffe);
return 0;
}
void __init epit_timer_init(void __iomem *base, int irq)
{
struct clk *timer_clk;
timer_clk = clk_get_sys("imx-epit.0", NULL);
if (IS_ERR(timer_clk)) {
pr_err("i.MX epit: unable to get clk\n");
return;
}
clk_prepare_enable(timer_clk);
timer_base = base;
/*
* Initialise to a known state (all timers off, and timing reset)
*/
imx_writel(0x0, timer_base + EPITCR);
imx_writel(0xffffffff, timer_base + EPITLR);
imx_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
timer_base + EPITCR);
/* init and register the timer to the framework */
epit_clocksource_init(timer_clk);
epit_clockevent_init(timer_clk);
/* Make irqs happen */
setup_irq(irq, &epit_timer_irq);
}

10
arch/arm/mach-imx/mach-imx6sl.c
View File

@ -18,6 +18,7 @@
#include "common.h"
#include "cpuidle.h"
#include "hardware.h"
static void __init imx6sl_fec_init(void)
{
@ -54,7 +55,8 @@ static void __init imx6sl_init_machine(void)
of_platform_default_populate(NULL, NULL, parent);
imx6sl_fec_init();
if (cpu_is_imx6sl())
imx6sl_fec_init();
imx_anatop_init();
imx6sl_pm_init();
}
@ -66,11 +68,15 @@ static void __init imx6sl_init_irq(void)
imx_init_l2cache();
imx_src_init();
irqchip_init();
imx6_pm_ccm_init("fsl,imx6sl-ccm");
if (cpu_is_imx6sl())
imx6_pm_ccm_init("fsl,imx6sl-ccm");
else
imx6_pm_ccm_init("fsl,imx6sll-ccm");
}
static const char * const imx6sl_dt_compat[] __initconst = {
"fsl,imx6sl",
"fsl,imx6sll",
NULL,
};

6
arch/arm/mach-imx/mxc.h
View File

@ -40,6 +40,7 @@
#define MXC_CPU_IMX6Q 0x63
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
#define MXC_CPU_IMX6SLL 0x67
#define MXC_CPU_IMX7D 0x72
#define IMX_DDR_TYPE_LPDDR2 1
@ -79,6 +80,11 @@ static inline bool cpu_is_imx6ull(void)
return __mxc_cpu_type == MXC_CPU_IMX6ULL;
}
static inline bool cpu_is_imx6sll(void)
{
return __mxc_cpu_type == MXC_CPU_IMX6SLL;
}
static inline bool cpu_is_imx6q(void)
{
return __mxc_cpu_type == MXC_CPU_IMX6Q;

7
arch/arm/mach-imx/pm-imx6.c
View File

@ -428,10 +428,8 @@ static int __init imx6_pm_get_base(struct imx6_pm_base *base,
int ret = 0;
node = of_find_compatible_node(NULL, NULL, compat);
if (!node) {
ret = -ENODEV;
goto out;
}
if (!node)
return -ENODEV;
ret = of_address_to_resource(node, 0, &res);
if (ret)
@ -444,7 +442,6 @@ static int __init imx6_pm_get_base(struct imx6_pm_base *base,
put_node:
of_node_put(node);
out:
return ret;
}

6
arch/arm/mach-mmp/aspenite.c
View File

@ -172,10 +172,8 @@ static struct mtd_partition aspenite_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data aspenite_nand_info = {
.enable_arbiter = 1,
.num_cs = 1,
.parts[0] = aspenite_nand_partitions,
.nr_parts[0] = ARRAY_SIZE(aspenite_nand_partitions),
.parts = aspenite_nand_partitions,
.nr_parts = ARRAY_SIZE(aspenite_nand_partitions),
};
static struct i2c_board_info aspenite_i2c_info[] __initdata = {

9
arch/arm/mach-mmp/ttc_dkb.c
View File

@ -178,11 +178,8 @@ static struct mv_usb_platform_data ttc_usb_pdata = {
#endif
#endif
#if IS_ENABLED(CONFIG_MTD_NAND_PXA3xx)
static struct pxa3xx_nand_platform_data dkb_nand_info = {
.enable_arbiter = 1,
.num_cs = 1,
};
#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
static struct pxa3xx_nand_platform_data dkb_nand_info = {};
#endif
#if IS_ENABLED(CONFIG_MMP_DISP)
@ -275,7 +272,7 @@ static void __init ttc_dkb_init(void)
/* on-chip devices */
pxa910_add_uart(1);
#if IS_ENABLED(CONFIG_MTD_NAND_PXA3xx)
#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
pxa910_add_nand(&dkb_nand_info);
#endif

30
arch/arm/mach-npcm/Kconfig Normal file
View File

@ -0,0 +1,30 @@
menuconfig ARCH_NPCM
bool "Nuvoton NPCM Architecture"
depends on ARCH_MULTI_V7
select PINCTRL
if ARCH_NPCM
config ARCH_NPCM7XX
bool "Support for NPCM7xx BMC (Poleg)"
depends on ARCH_MULTI_V7
select PINCTRL_NPCM7XX
select NPCM7XX_TIMER
select ARCH_REQUIRE_GPIOLIB
select CACHE_L2X0
select ARM_GIC
select HAVE_ARM_TWD if SMP
select HAVE_ARM_SCU if SMP
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_720789
select ARM_ERRATA_754322
select ARM_ERRATA_794072
select PL310_ERRATA_588369
select PL310_ERRATA_727915
select MFD_SYSCON
help
General support for NPCM7xx BMC (Poleg).
Nuvoton NPCM7xx BMC based on the Cortex A9.
endif

4
arch/arm/mach-npcm/Makefile Normal file
View File

@ -0,0 +1,4 @@
AFLAGS_headsmp.o += -march=armv7-a
obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o

17
arch/arm/mach-npcm/headsmp.S Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology corporation.
// Copyright 2018 Google, Inc.
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
/*
* The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
* here.
*/
ENTRY(npcm7xx_secondary_startup)
safe_svcmode_maskall r0
b secondary_startup
ENDPROC(npcm7xx_secondary_startup)

20
arch/arm/mach-npcm/npcm7xx.c Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology corporation.
// Copyright 2018 Google, Inc.
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
static const char *const npcm7xx_dt_match[] = {
"nuvoton,npcm750",
NULL
};
DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
.atag_offset = 0x100,
.dt_compat = npcm7xx_dt_match,
MACHINE_END

81
arch/arm/mach-npcm/platsmp.c Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology corporation.
// Copyright 2018 Google, Inc.
#define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <asm/cacheflush.h>
#include <asm/smp.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#define NPCM7XX_SCRPAD_REG 0x13c
extern void npcm7xx_secondary_startup(void);
static int npcm7xx_smp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
struct device_node *gcr_np;
void __iomem *gcr_base;
int ret = 0;
gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
if (!gcr_np) {
pr_err("no gcr device node\n");
ret = -ENODEV;
goto out;
}
gcr_base = of_iomap(gcr_np, 0);
if (!gcr_base) {
pr_err("could not iomap gcr");
ret = -ENOMEM;
goto out;
}
/* give boot ROM kernel start address. */
iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
NPCM7XX_SCRPAD_REG);
/* make sure the previous write is seen by all observers. */
dsb_sev();
iounmap(gcr_base);
out:
return ret;
}
static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *scu_np;
void __iomem *scu_base;
scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (!scu_np) {
pr_err("no scu device node\n");
return;
}
scu_base = of_iomap(scu_np, 0);
if (!scu_base) {
pr_err("could not iomap scu");
return;
}
scu_enable(scu_base);
iounmap(scu_base);
}
static struct smp_operations npcm7xx_smp_ops __initdata = {
.smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
.smp_boot_secondary = npcm7xx_smp_boot_secondary,
};
CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops);

6
arch/arm/mach-nspire/nspire.c
View File

@ -33,11 +33,6 @@ static const char *const nspire_dt_match[] __initconst = {
NULL,
};
static void __init nspire_map_io(void)
{
debug_ll_io_init();
}
static struct clcd_board nspire_clcd_data = {
.name = "LCD",
.caps = CLCD_CAP_5551 | CLCD_CAP_565,
@ -71,7 +66,6 @@ static void nspire_restart(enum reboot_mode mode, const char *cmd)
DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
.dt_compat = nspire_dt_match,
.map_io = nspire_map_io,
.init_machine = nspire_init,
.restart = nspire_restart,
MACHINE_END

1
arch/arm/mach-omap1/Kconfig
View File

@ -30,6 +30,7 @@ config ARCH_OMAP16XX
bool "OMAP16xx Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
select OMAP_DM_TIMER
config OMAP_MUX
bool "OMAP multiplexing support"

3
arch/arm/mach-omap1/common.h
View File

@ -32,11 +32,10 @@
#include <asm/exception.h>
#include <plat/i2c.h>
#include <mach/irqs.h>
#include "soc.h"
#include "i2c.h"
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
void omap7xx_map_io(void);

2
arch/arm/mach-omap1/i2c.c
View File

@ -24,8 +24,6 @@
#include <mach/mux.h>
#include "soc.h"
#include <plat/i2c.h>
#define OMAP_I2C_SIZE 0x3f
#define OMAP1_I2C_BASE 0xfffb3800

9
arch/arm/plat-omap/include/plat/i2c.h → arch/arm/mach-omap1/i2c.h
View File

@ -19,8 +19,8 @@
*
*/
#ifndef __PLAT_OMAP_I2C_H
#define __PLAT_OMAP_I2C_H
#ifndef __ARCH_ARM_MACH_OMAP1_I2C_H
#define __ARCH_ARM_MACH_OMAP1_I2C_H
struct i2c_board_info;
struct omap_i2c_bus_platform_data;
@ -47,7 +47,4 @@ static inline int omap_register_i2c_bus_cmdline(void)
}
#endif
struct omap_hwmod;
int omap_i2c_reset(struct omap_hwmod *oh);
#endif /* __PLAT_OMAP_I2C_H */
#endif /* __ARCH_ARM_MACH_OMAP1_I2C_H */

2
arch/arm/mach-omap1/pm.c
View File

@ -55,7 +55,7 @@
#include <mach/tc.h>
#include <mach/mux.h>
#include <linux/omap-dma.h>
#include <plat/dmtimer.h>
#include <clocksource/timer-ti-dm.h>
#include <mach/irqs.h>

2
arch/arm/mach-omap1/timer.c
View File

@ -27,7 +27,7 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
#include <plat/dmtimer.h>
#include <clocksource/timer-ti-dm.h>
#include "soc.h"

1
arch/arm/mach-omap2/Kconfig
View File

@ -72,6 +72,7 @@ config SOC_AM43XX
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select OMAP_INTERCONNECT
select ARM_CPU_SUSPEND if PM
config SOC_DRA7XX
bool "TI DRA7XX"

16
arch/arm/mach-omap2/Makefile
View File

@ -88,6 +88,8 @@ omap-4-5-pm-common += pm44xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_AM33XX) += pm33xx-core.o sleep33xx.o
obj-$(CONFIG_SOC_AM43XX) += pm33xx-core.o sleep43xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
@ -95,6 +97,8 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec)
AFLAGS_sleep43xx.o :=-Wa,-march=armv7-a$(plus_sec)
endif
@ -232,3 +236,15 @@ obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
obj-y += omap_phy_internal.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
arch/arm/mach-omap2/pm-asm-offsets.s: arch/arm/mach-omap2/pm-asm-offsets.c
$(call if_changed_dep,cc_s_c)
include/generated/ti-pm-asm-offsets.h: arch/arm/mach-omap2/pm-asm-offsets.s FORCE
$(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__)
# For rule to generate ti-emif-asm-offsets.h dependency
include drivers/memory/Makefile.asm-offsets
arch/arm/mach-omap2/sleep33xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h
arch/arm/mach-omap2/sleep43xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h

4
arch/arm/mach-omap2/board-n8x0.c
View File

@ -566,11 +566,11 @@ static int n8x0_menelaus_late_init(struct device *dev)
}
#endif
struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
struct menelaus_platform_data n8x0_menelaus_platform_data = {
.late_init = n8x0_menelaus_late_init,
};
struct aic3x_pdata n810_aic33_data __initdata = {
struct aic3x_pdata n810_aic33_data = {
.gpio_reset = 118,
};

7
arch/arm/mach-omap2/common.h
View File

@ -77,6 +77,13 @@ static inline int omap4_pm_init_early(void)
}
#endif
#if defined(CONFIG_PM) && (defined(CONFIG_SOC_AM33XX) || \
defined(CONFIG_SOC_AM43XX))
void amx3_common_pm_init(void);
#else
static inline void amx3_common_pm_init(void) { }
#endif
extern void omap2_init_common_infrastructure(void);
extern void omap_init_time(void);

20
arch/arm/mach-omap2/control.c
View File

@ -623,6 +623,7 @@ void __init omap3_ctrl_init(void)
struct control_init_data {
int index;
void __iomem *mem;
s16 offset;
};
@ -635,6 +636,10 @@ static const struct control_init_data omap2_ctrl_data = {
.offset = -OMAP2_CONTROL_GENERAL,
};
static const struct control_init_data ctrl_aux_data = {
.index = TI_CLKM_CTRL_AUX,
};
static const struct of_device_id omap_scrm_dt_match_table[] = {
{ .compatible = "ti,am3-scm", .data = &ctrl_data },
{ .compatible = "ti,am4-scm", .data = &ctrl_data },
@ -644,6 +649,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = {
{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
{ .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
{ .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
{ .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data },
{ .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
{ }
};
@ -660,15 +666,21 @@ int __init omap2_control_base_init(void)
struct device_node *np;
const struct of_device_id *match;
struct control_init_data *data;
void __iomem *mem;
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
data = (struct control_init_data *)match->data;
omap2_ctrl_base = of_iomap(np, 0);
if (!omap2_ctrl_base)
mem = of_iomap(np, 0);
if (!mem)
return -ENOMEM;
omap2_ctrl_offset = data->offset;
if (data->index == TI_CLKM_CTRL) {
omap2_ctrl_base = mem;
omap2_ctrl_offset = data->offset;
}
data->mem = mem;
}
return 0;
@ -713,7 +725,7 @@ int __init omap_control_init(void)
} else {
/* No scm_conf found, direct access */
ret = omap2_clk_provider_init(np, data->index, NULL,
omap2_ctrl_base);
data->mem);
if (ret)
return ret;
}

2
arch/arm/mach-omap2/devices.c
View File

@ -8,7 +8,7 @@
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>

2
arch/arm/mach-omap2/hsmmc.c
View File

@ -13,9 +13,7 @@
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/mmc/host.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include "soc.h"

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