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ASoC: rt5677: add i2s asrc clk src selection 

The ASRC source of i2s are also configurable. We add the selection
in the existing rt5677_sel_asrc_clk_src API.

Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Bard Liao 2015-04-28 11:27:40 +08:00 committed by Mark Brown
parent b787f68c36
commit 16ab6e18c6
2 changed files with 44 additions and 0 deletions
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30
sound/soc/codecs/rt5677.c
View File

@ -1057,6 +1057,7 @@ int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
unsigned int asrc5_mask = 0, asrc5_value = 0;
unsigned int asrc6_mask = 0, asrc6_value = 0;
unsigned int asrc7_mask = 0, asrc7_value = 0;
unsigned int asrc8_mask = 0, asrc8_value = 0;
switch (clk_src) {
case RT5677_CLK_SEL_SYS:
@ -1193,6 +1194,35 @@ int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
asrc7_value);
/* ASRC 8 */
if (filter_mask & RT5677_I2S1_SOURCE) {
asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S2_SOURCE) {
asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S3_SOURCE) {
asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S4_SOURCE) {
asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
}
if (asrc8_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
asrc8_value);
return 0;
}
EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);

14
sound/soc/codecs/rt5677.h
View File

@ -1446,6 +1446,16 @@
#define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8)
#define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8
/* ASRC Control 8 (0x8a) */
#define RT5677_I2S1_CLK_SEL_MASK (0xf << 12)
#define RT5677_I2S1_CLK_SEL_SFT 12
#define RT5677_I2S2_CLK_SEL_MASK (0xf << 8)
#define RT5677_I2S2_CLK_SEL_SFT 8
#define RT5677_I2S3_CLK_SEL_MASK (0xf << 4)
#define RT5677_I2S3_CLK_SEL_SFT 4
#define RT5677_I2S4_CLK_SEL_MASK (0xf)
#define RT5677_I2S4_CLK_SEL_SFT 0
/* VAD Function Control 4 (0x9f) */
#define RT5677_VAD_SRC_MASK (0x7 << 8)
#define RT5677_VAD_SRC_SFT 8
@ -1744,6 +1754,10 @@ enum {
RT5677_AD_MONO_R_FILTER = (0x1 << 12),
RT5677_DSP_OB_0_3_FILTER = (0x1 << 13),
RT5677_DSP_OB_4_7_FILTER = (0x1 << 14),
RT5677_I2S1_SOURCE = (0x1 << 15),
RT5677_I2S2_SOURCE = (0x1 << 16),
RT5677_I2S3_SOURCE = (0x1 << 17),
RT5677_I2S4_SOURCE = (0x1 << 18),
};
struct rt5677_priv {