Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (39 commits) omap: delete unused bootloader tag variables omap: Devkit8000: Remove unused pins omap: Devkit8000: Change position of init calls omap: Devkit8000: Remove unnecessary include file omap: Devkit8000: Fix typo in pin name omap: Devkit8000: Add missing package selection omap: Devkit8000: Fix typo in supplies n8x0_defconfig: remove CONFIG_NILFS2_FS override omap: board-sdp-flash.c: Fix typos in debug output omap4: Fix McBSP4 base address omap: rx51_defconfig: Remove CONFIG_SYSFS_DEPRECATED*=y options omap: rx51_defconfig: Remove duplicate phonet omap: fix a gpmc nand problem AM3517: initialize i2c subsystem after mux subsystem omap: remove one of the define of INT_34XX_BENCH_MPU_EMUL omap: fix the compile error if CONFIG_MTD_NAND_OMAP2 is notenabled OMAP4: Clocks: Change SPI Instance Names omap: Devkit8000: Fix wrong usb port on Devkit8000 OMAP4: Fix for CONTROL register Base OMAP4-HSMMC: FIX for MMC5 Controller IRQ Base ...
This commit is contained in:
commit
17282b9855
arch/arm
configs
mach-omap1
mach-omap2
Kconfigboard-3630sdp.cboard-am3517evm.cboard-devkit8000.cboard-igep0020.cboard-n8x0.cboard-sdp-flash.cboard-zoom-debugboard.cboard-zoom-peripherals.cclock3xxx_data.cclock44xx_data.cclockdomain.cdevices.cgpmc-nand.c
include/mach
omap-headsmp.Somap44xx-smc.Somap_hwmod.cpowerdomain.cprcm.cserial.cplat-omap
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@ -1058,7 +1058,6 @@ CONFIG_JFFS2_CMODE_PRIORITY=y
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# CONFIG_ROMFS_FS is not set
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# CONFIG_SYSV_FS is not set
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# CONFIG_UFS_FS is not set
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# CONFIG_NILFS2_FS is not set
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CONFIG_NETWORK_FILESYSTEMS=y
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# CONFIG_NFS_FS is not set
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# CONFIG_NFSD is not set
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@ -661,7 +661,7 @@ CONFIG_DEVKMEM=y
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=32
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CONFIG_SERIAL_8250_RUNTIME_UARTS=4
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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CONFIG_SERIAL_8250_EXTENDED=y
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CONFIG_SERIAL_8250_MANY_PORTS=y
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CONFIG_SERIAL_8250_SHARE_IRQ=y
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@ -680,7 +680,7 @@ CONFIG_DEVKMEM=y
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=32
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CONFIG_SERIAL_8250_RUNTIME_UARTS=4
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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CONFIG_SERIAL_8250_EXTENDED=y
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CONFIG_SERIAL_8250_MANY_PORTS=y
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CONFIG_SERIAL_8250_SHARE_IRQ=y
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@ -59,8 +59,6 @@ CONFIG_FAIR_GROUP_SCHED=y
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CONFIG_USER_SCHED=y
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# CONFIG_CGROUP_SCHED is not set
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# CONFIG_CGROUPS is not set
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CONFIG_SYSFS_DEPRECATED=y
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CONFIG_SYSFS_DEPRECATED_V2=y
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# CONFIG_RELAY is not set
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# CONFIG_NAMESPACES is not set
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CONFIG_BLK_DEV_INITRD=y
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@ -480,7 +478,6 @@ CONFIG_BT_HIDP=m
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# CONFIG_BT_HCIBFUSB is not set
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# CONFIG_BT_HCIVHCI is not set
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# CONFIG_AF_RXRPC is not set
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# CONFIG_PHONET is not set
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CONFIG_WIRELESS=y
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CONFIG_CFG80211=y
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# CONFIG_CFG80211_REG_DEBUG is not set
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@ -68,12 +68,6 @@ struct sys_timer omap_timer;
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* ---------------------------------------------------------------------------
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*/
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#if defined(CONFIG_ARCH_OMAP16XX)
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#define TIMER_32K_SYNCHRONIZED 0xfffbc410
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#else
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#error OMAP 32KHz timer does not currently work on 15XX!
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#endif
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/* 16xx specific defines */
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#define OMAP1_32K_TIMER_BASE 0xfffb9000
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#define OMAP1_32K_TIMER_CR 0x08
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@ -150,15 +144,6 @@ static struct clock_event_device clockevent_32k_timer = {
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.set_mode = omap_32k_timer_set_mode,
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};
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/*
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* The 32KHz synchronized timer is an additional timer on 16xx.
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* It is always running.
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*/
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static inline unsigned long omap_32k_sync_timer_read(void)
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{
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return omap_readl(TIMER_32K_SYNCHRONIZED);
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}
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static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_32k_timer;
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@ -59,8 +59,10 @@ config MACH_OMAP3_BEAGLE
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select OMAP_PACKAGE_CBB
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config MACH_DEVKIT8000
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bool "DEVKIT8000 board"
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depends on ARCH_OMAP3
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bool "DEVKIT8000 board"
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depends on ARCH_OMAP3
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select OMAP_PACKAGE_CUS
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select OMAP_MUX
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config MACH_OMAP_LDP
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bool "OMAP3 LDP board"
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@ -96,6 +96,7 @@ static struct omap_board_mux board_mux[] __initdata = {
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static void __init omap_sdp_init(void)
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{
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omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
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omap_serial_init();
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zoom_peripherals_init();
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board_smc91x_init();
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enable_board_wakeup_source();
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@ -294,9 +294,9 @@ static struct omap_board_mux board_mux[] __initdata = {
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static void __init am3517_evm_init(void)
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{
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am3517_evm_i2c_init();
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omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
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am3517_evm_i2c_init();
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platform_add_devices(am3517_evm_devices,
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ARRAY_SIZE(am3517_evm_devices));
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@ -50,7 +50,6 @@
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#include <linux/input/matrix_keypad.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/ads7846.h>
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#include <linux/usb/otg.h>
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#include <linux/dm9000.h>
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#include <linux/interrupt.h>
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@ -269,20 +268,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
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devkit8000_vmmc1_supply.dev = mmc[0].dev;
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devkit8000_vsim_supply.dev = mmc[0].dev;
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/* REVISIT: need ehci-omap hooks for external VBUS
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* power switch and overcurrent detect
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*/
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gpio_request(gpio + 1, "EHCI_nOC");
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gpio_direction_input(gpio + 1);
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/* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
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gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
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gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1);
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/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
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gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
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return 0;
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}
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@ -303,7 +288,7 @@ static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = {
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.dev = &devkit8000_lcd_device.dev,
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},
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{
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.supply = "vdss_dsi",
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.supply = "vdds_dsi",
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.dev = &devkit8000_dss_device.dev,
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}
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};
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@ -639,17 +624,21 @@ static struct omap_musb_board_data musb_board_data = {
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static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
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.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.phy_reset = true,
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.reset_gpio_port[0] = -EINVAL,
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.reset_gpio_port[1] = 147,
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.reset_gpio_port[1] = -EINVAL,
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.reset_gpio_port[2] = -EINVAL
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};
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static void __init devkit8000_init(void)
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{
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omap_serial_init();
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omap_dm9000_init();
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devkit8000_i2c_init();
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platform_add_devices(devkit8000_devices,
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ARRAY_SIZE(devkit8000_devices));
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@ -659,25 +648,15 @@ static void __init devkit8000_init(void)
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spi_register_board_info(devkit8000_spi_board_info,
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ARRAY_SIZE(devkit8000_spi_board_info));
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omap_serial_init();
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omap_dm9000_init();
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devkit8000_ads7846_init();
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omap_mux_init_gpio(170, OMAP_PIN_INPUT);
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gpio_request(170, "DVI_nPD");
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/* REVISIT leave DVI powered down until it's needed ... */
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gpio_direction_output(170, true);
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usb_musb_init(&musb_board_data);
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usb_ehci_init(&ehci_pdata);
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devkit8000_flash_init();
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/* Ensure SDRC pins are mux'd for self-refresh */
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omap_mux_init_signal("sdr_cke0", OMAP_PIN_OUTPUT);
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omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT);
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omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
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omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
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}
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static void __init devkit8000_map_io(void)
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@ -458,13 +458,13 @@ static struct omap_musb_board_data musb_board_data = {
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};
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static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
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.port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.phy_reset = true,
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.reset_gpio_port[0] = -EINVAL,
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.reset_gpio_port[1] = IGEP2_GPIO_USBH_NRESET,
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.reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
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.reset_gpio_port[1] = -EINVAL,
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.reset_gpio_port[2] = -EINVAL,
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};
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@ -216,7 +216,7 @@ static void __init n8x0_onenand_init(void) {}
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*/
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#define N8X0_SLOT_SWITCH_GPIO 96
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#define N810_EMMC_VSD_GPIO 23
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#define NN810_EMMC_VIO_GPIO 9
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#define N810_EMMC_VIO_GPIO 9
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static int n8x0_mmc_switch_slot(struct device *dev, int slot)
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{
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@ -304,10 +304,10 @@ static void n810_set_power_emmc(struct device *dev,
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if (power_on) {
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gpio_set_value(N810_EMMC_VSD_GPIO, 1);
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msleep(1);
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gpio_set_value(NN810_EMMC_VIO_GPIO, 1);
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gpio_set_value(N810_EMMC_VIO_GPIO, 1);
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msleep(1);
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} else {
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gpio_set_value(NN810_EMMC_VIO_GPIO, 0);
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gpio_set_value(N810_EMMC_VIO_GPIO, 0);
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msleep(50);
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gpio_set_value(N810_EMMC_VSD_GPIO, 0);
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msleep(50);
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@ -468,7 +468,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
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if (machine_is_nokia_n810()) {
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gpio_free(N810_EMMC_VSD_GPIO);
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gpio_free(NN810_EMMC_VIO_GPIO);
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gpio_free(N810_EMMC_VIO_GPIO);
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}
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}
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@ -529,7 +529,7 @@ void __init n8x0_mmc_init(void)
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err = gpio_request(N8X0_SLOT_SWITCH_GPIO, "MMC slot switch");
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if (err)
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return err;
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return;
|
||||
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gpio_direction_output(N8X0_SLOT_SWITCH_GPIO, 0);
|
||||
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@ -537,17 +537,17 @@ void __init n8x0_mmc_init(void)
|
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err = gpio_request(N810_EMMC_VSD_GPIO, "MMC slot 2 Vddf");
|
||||
if (err) {
|
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gpio_free(N8X0_SLOT_SWITCH_GPIO);
|
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return err;
|
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return;
|
||||
}
|
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gpio_direction_output(N810_EMMC_VSD_GPIO, 0);
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|
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err = gpio_request(NN810_EMMC_VIO_GPIO, "MMC slot 2 Vdd");
|
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err = gpio_request(N810_EMMC_VIO_GPIO, "MMC slot 2 Vdd");
|
||||
if (err) {
|
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gpio_free(N8X0_SLOT_SWITCH_GPIO);
|
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gpio_free(N810_EMMC_VSD_GPIO);
|
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return err;
|
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return;
|
||||
}
|
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gpio_direction_output(NN810_EMMC_VIO_GPIO, 0);
|
||||
gpio_direction_output(N810_EMMC_VIO_GPIO, 0);
|
||||
}
|
||||
|
||||
mmc_data[0] = &mmc1_data;
|
||||
|
|
|
@ -253,20 +253,20 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[])
|
|||
}
|
||||
|
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if (norcs > GPMC_CS_NUM)
|
||||
printk(KERN_INFO "OneNAND: Unable to find configuration "
|
||||
" in GPMC\n ");
|
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printk(KERN_INFO "NOR: Unable to find configuration "
|
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"in GPMC\n");
|
||||
else
|
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board_nor_init(sdp_partition_info[0], norcs);
|
||||
|
||||
if (onenandcs > GPMC_CS_NUM)
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printk(KERN_INFO "OneNAND: Unable to find configuration "
|
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" in GPMC\n ");
|
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"in GPMC\n");
|
||||
else
|
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board_onenand_init(sdp_partition_info[1], onenandcs);
|
||||
|
||||
if (nandcs > GPMC_CS_NUM)
|
||||
printk(KERN_INFO "NAND: Unable to find configuration "
|
||||
" in GPMC\n ");
|
||||
"in GPMC\n");
|
||||
else
|
||||
board_nand_init(sdp_partition_info[2], nandcs);
|
||||
}
|
||||
|
|
|
@ -96,7 +96,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
|
||||
static struct platform_device zoom_debugboard_serial_device = {
|
||||
.name = "serial8250",
|
||||
.id = 3,
|
||||
.id = PLAT8250_DEV_PLATFORM,
|
||||
.dev = {
|
||||
.platform_data = serial_platform_data,
|
||||
},
|
||||
|
|
|
@ -280,7 +280,6 @@ static void enable_board_wakeup_source(void)
|
|||
void __init zoom_peripherals_init(void)
|
||||
{
|
||||
omap_i2c_init();
|
||||
omap_serial_init();
|
||||
usb_musb_init(&musb_board_data);
|
||||
enable_board_wakeup_source();
|
||||
}
|
||||
|
|
|
@ -895,7 +895,7 @@ static struct clk dpll4_m4x2_ck = {
|
|||
.ops = &clkops_omap2_dflt_wait,
|
||||
.parent = &dpll4_m4_ck,
|
||||
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
||||
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
|
||||
.enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
|
||||
.flags = INVERT_ENABLE,
|
||||
.clkdm_name = "dpll4_clkdm",
|
||||
.recalc = &omap3_clkoutx2_recalc,
|
||||
|
|
|
@ -2671,10 +2671,10 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap-mcspi.1", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap-mcspi.2", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap-mcspi.3", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap-mcspi.4", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
|
||||
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
|
||||
|
|
|
@ -240,7 +240,7 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
|
|||
bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
|
||||
else
|
||||
bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
|
||||
} else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
|
||||
} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
|
||||
if (enable)
|
||||
bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
|
||||
else
|
||||
|
@ -812,7 +812,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
|
|||
cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
|
||||
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
|
||||
|
||||
} else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
|
||||
} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
|
||||
|
||||
u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
|
||||
__ffs(clkdm->clktrctrl_mask));
|
||||
|
@ -856,7 +856,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
|
|||
cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
|
||||
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
|
||||
|
||||
} else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
|
||||
} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
|
||||
|
||||
u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
|
||||
__ffs(clkdm->clktrctrl_mask));
|
||||
|
|
|
@ -726,7 +726,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
|
|||
if (!cpu_is_omap44xx())
|
||||
return;
|
||||
base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
|
||||
irq = OMAP44XX_IRQ_MMC4;
|
||||
irq = OMAP44XX_IRQ_MMC5;
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
|
|
|
@ -39,6 +39,9 @@ static int omap2_nand_gpmc_retime(void)
|
|||
struct gpmc_timings t;
|
||||
int err;
|
||||
|
||||
if (!gpmc_nand_data->gpmc_t)
|
||||
return 0;
|
||||
|
||||
memset(&t, 0, sizeof(t));
|
||||
t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk);
|
||||
t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
|
||||
|
|
|
@ -52,7 +52,7 @@ omap_irq_base: .word 0
|
|||
|
||||
mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
|
||||
and \tmp, \tmp, #0x000f0000 @ only check architecture
|
||||
cmp \tmp, #0x00060000 @ is v6?
|
||||
cmp \tmp, #0x00070000 @ is v6?
|
||||
beq 2400f @ found v6 so it's omap24xx
|
||||
mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
|
||||
and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
|
||||
|
|
|
@ -33,7 +33,7 @@
|
|||
ENTRY(omap_secondary_startup)
|
||||
hold: ldr r12,=0x103
|
||||
dsb
|
||||
smc @ read from AuxCoreBoot0
|
||||
smc #0 @ read from AuxCoreBoot0
|
||||
mov r0, r0, lsr #9
|
||||
mrc p15, 0, r4, c0, c0, 5
|
||||
and r4, r4, #0x0f
|
||||
|
@ -52,7 +52,7 @@ ENTRY(omap_modify_auxcoreboot0)
|
|||
stmfd sp!, {r1-r12, lr}
|
||||
ldr r12, =0x104
|
||||
dsb
|
||||
smc
|
||||
smc #0
|
||||
ldmfd sp!, {r1-r12, pc}
|
||||
END(omap_modify_auxcoreboot0)
|
||||
|
||||
|
@ -60,6 +60,6 @@ ENTRY(omap_auxcoreboot_addr)
|
|||
stmfd sp!, {r2-r12, lr}
|
||||
ldr r12, =0x105
|
||||
dsb
|
||||
smc
|
||||
smc #0
|
||||
ldmfd sp!, {r2-r12, pc}
|
||||
END(omap_auxcoreboot_addr)
|
||||
|
|
|
@ -27,6 +27,6 @@ ENTRY(omap_smc1)
|
|||
mov r12, r0
|
||||
mov r0, r1
|
||||
dsb
|
||||
smc
|
||||
smc #0
|
||||
ldmfd sp!, {r2-r12, pc}
|
||||
END(omap_smc1)
|
||||
|
|
|
@ -1511,6 +1511,9 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
|
|||
c = oh->slaves[oh->_mpu_port_index]->_clk;
|
||||
}
|
||||
|
||||
if (!c->clkdm)
|
||||
return NULL;
|
||||
|
||||
return c->clkdm->pwrdm.ptr;
|
||||
|
||||
}
|
||||
|
|
|
@ -222,7 +222,7 @@ void pwrdm_init(struct powerdomain **pwrdm_list)
|
|||
{
|
||||
struct powerdomain **p = NULL;
|
||||
|
||||
if (cpu_is_omap24xx() | cpu_is_omap34xx()) {
|
||||
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
||||
pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL;
|
||||
pwrstst_reg_offs = OMAP2_PM_PWSTST;
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
|
|
|
@ -123,7 +123,7 @@ struct omap3_prcm_regs prcm_context;
|
|||
u32 omap_prcm_get_reset_sources(void)
|
||||
{
|
||||
/* XXX This presumably needs modification for 34XX */
|
||||
if (cpu_is_omap24xx() | cpu_is_omap34xx())
|
||||
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
||||
return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
|
||||
if (cpu_is_omap44xx())
|
||||
return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
|
||||
|
@ -157,7 +157,7 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
|
|||
else
|
||||
WARN_ON(1);
|
||||
|
||||
if (cpu_is_omap24xx() | cpu_is_omap34xx())
|
||||
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
||||
prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
|
||||
OMAP2_RM_RSTCTRL);
|
||||
if (cpu_is_omap44xx())
|
||||
|
|
|
@ -115,7 +115,6 @@ static struct plat_serial8250_port serial_platform_data2[] = {
|
|||
}
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
|
||||
static struct plat_serial8250_port serial_platform_data3[] = {
|
||||
{
|
||||
.irq = 70,
|
||||
|
@ -128,23 +127,12 @@ static struct plat_serial8250_port serial_platform_data3[] = {
|
|||
}
|
||||
};
|
||||
|
||||
static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
|
||||
{
|
||||
serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
|
||||
}
|
||||
#else
|
||||
static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
|
||||
{
|
||||
serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
|
||||
serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
|
||||
serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
|
||||
if (cpu_is_omap3630() || cpu_is_omap44xx())
|
||||
omap2_set_globals_uart4(omap2_globals);
|
||||
serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
|
||||
}
|
||||
|
||||
static inline unsigned int __serial_read_reg(struct uart_port *up,
|
||||
|
@ -550,7 +538,7 @@ static ssize_t sleep_timeout_store(struct device *dev,
|
|||
unsigned int value;
|
||||
|
||||
if (sscanf(buf, "%u", &value) != 1) {
|
||||
printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
|
||||
dev_err(dev, "sleep_timeout_store: Invalid value\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -664,27 +652,33 @@ void __init omap_serial_early_init(void)
|
|||
struct device *dev = &pdev->dev;
|
||||
struct plat_serial8250_port *p = dev->platform_data;
|
||||
|
||||
/* Don't map zero-based physical address */
|
||||
if (p->mapbase == 0) {
|
||||
dev_warn(dev, "no physical address for uart#%d,"
|
||||
" so skipping early_init...\n", i);
|
||||
continue;
|
||||
}
|
||||
/*
|
||||
* Module 4KB + L4 interconnect 4KB
|
||||
* Static mapping, never released
|
||||
*/
|
||||
p->membase = ioremap(p->mapbase, SZ_8K);
|
||||
if (!p->membase) {
|
||||
printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
|
||||
dev_err(dev, "ioremap failed for uart%i\n", i + 1);
|
||||
continue;
|
||||
}
|
||||
|
||||
sprintf(name, "uart%d_ick", i + 1);
|
||||
uart->ick = clk_get(NULL, name);
|
||||
if (IS_ERR(uart->ick)) {
|
||||
printk(KERN_ERR "Could not get uart%d_ick\n", i + 1);
|
||||
dev_err(dev, "Could not get uart%d_ick\n", i + 1);
|
||||
uart->ick = NULL;
|
||||
}
|
||||
|
||||
sprintf(name, "uart%d_fck", i+1);
|
||||
uart->fck = clk_get(NULL, name);
|
||||
if (IS_ERR(uart->fck)) {
|
||||
printk(KERN_ERR "Could not get uart%d_fck\n", i + 1);
|
||||
dev_err(dev, "Could not get uart%d_fck\n", i + 1);
|
||||
uart->fck = NULL;
|
||||
}
|
||||
|
||||
|
@ -727,6 +721,13 @@ void __init omap_serial_init_port(int port)
|
|||
pdev = &uart->pdev;
|
||||
dev = &pdev->dev;
|
||||
|
||||
/* Don't proceed if there's no clocks available */
|
||||
if (unlikely(!uart->ick || !uart->fck)) {
|
||||
WARN(1, "%s: can't init uart%d, no clocks available\n",
|
||||
kobject_name(&dev->kobj), port);
|
||||
return;
|
||||
}
|
||||
|
||||
omap_uart_enable_clocks(uart);
|
||||
|
||||
omap_uart_reset(uart);
|
||||
|
|
|
@ -44,9 +44,6 @@
|
|||
|
||||
#define NO_LENGTH_CHECK 0xffffffff
|
||||
|
||||
unsigned char omap_bootloader_tag[512];
|
||||
int omap_bootloader_tag_len;
|
||||
|
||||
struct omap_board_config_kernel *omap_board_config;
|
||||
int omap_board_config_size;
|
||||
|
||||
|
@ -100,10 +97,17 @@ EXPORT_SYMBOL(omap_get_var_config);
|
|||
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
/*
|
||||
* offset_32k holds the init time counter value. It is then subtracted
|
||||
* from every counter read to achieve a counter that counts time from the
|
||||
* kernel boot (needed for sched_clock()).
|
||||
*/
|
||||
static u32 offset_32k __read_mostly;
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP16XX
|
||||
static cycle_t omap16xx_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED);
|
||||
return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap16xx_32k_read NULL
|
||||
|
@ -112,7 +116,7 @@ static cycle_t omap16xx_32k_read(struct clocksource *cs)
|
|||
#ifdef CONFIG_ARCH_OMAP2420
|
||||
static cycle_t omap2420_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10);
|
||||
return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap2420_32k_read NULL
|
||||
|
@ -121,7 +125,7 @@ static cycle_t omap2420_32k_read(struct clocksource *cs)
|
|||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
static cycle_t omap2430_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10);
|
||||
return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap2430_32k_read NULL
|
||||
|
@ -130,7 +134,7 @@ static cycle_t omap2430_32k_read(struct clocksource *cs)
|
|||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static cycle_t omap34xx_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10);
|
||||
return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap34xx_32k_read NULL
|
||||
|
@ -139,7 +143,7 @@ static cycle_t omap34xx_32k_read(struct clocksource *cs)
|
|||
#ifdef CONFIG_ARCH_OMAP4
|
||||
static cycle_t omap44xx_32k_read(struct clocksource *cs)
|
||||
{
|
||||
return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10);
|
||||
return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
|
||||
}
|
||||
#else
|
||||
#define omap44xx_32k_read NULL
|
||||
|
@ -227,6 +231,8 @@ static int __init omap_init_clocksource_32k(void)
|
|||
clocksource_32k.mult = clocksource_hz2mult(32768,
|
||||
clocksource_32k.shift);
|
||||
|
||||
offset_32k = clocksource_32k.read(&clocksource_32k);
|
||||
|
||||
if (clocksource_register(&clocksource_32k))
|
||||
printk(err, clocksource_32k.name);
|
||||
}
|
||||
|
|
|
@ -937,6 +937,15 @@ void omap_start_dma(int lch)
|
|||
{
|
||||
u32 l;
|
||||
|
||||
/*
|
||||
* The CPC/CDAC register needs to be initialized to zero
|
||||
* before starting dma transfer.
|
||||
*/
|
||||
if (cpu_is_omap15xx())
|
||||
dma_write(0, CPC(lch));
|
||||
else
|
||||
dma_write(0, CDAC(lch));
|
||||
|
||||
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
|
||||
int next_lch, cur_lch;
|
||||
char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
|
||||
|
|
|
@ -798,7 +798,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
|
|||
case METHOD_MPUIO:
|
||||
reg += OMAP_MPUIO_GPIO_INT_EDGE;
|
||||
l = __raw_readl(reg);
|
||||
if (trigger & IRQ_TYPE_EDGE_BOTH)
|
||||
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
||||
bank->toggle_mask |= 1 << gpio;
|
||||
if (trigger & IRQ_TYPE_EDGE_RISING)
|
||||
l |= 1 << gpio;
|
||||
|
@ -812,7 +812,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
|
|||
case METHOD_GPIO_1510:
|
||||
reg += OMAP1510_GPIO_INT_CONTROL;
|
||||
l = __raw_readl(reg);
|
||||
if (trigger & IRQ_TYPE_EDGE_BOTH)
|
||||
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
||||
bank->toggle_mask |= 1 << gpio;
|
||||
if (trigger & IRQ_TYPE_EDGE_RISING)
|
||||
l |= 1 << gpio;
|
||||
|
@ -846,7 +846,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
|
|||
case METHOD_GPIO_7XX:
|
||||
reg += OMAP7XX_GPIO_INT_CONTROL;
|
||||
l = __raw_readl(reg);
|
||||
if (trigger & IRQ_TYPE_EDGE_BOTH)
|
||||
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
||||
bank->toggle_mask |= 1 << gpio;
|
||||
if (trigger & IRQ_TYPE_EDGE_RISING)
|
||||
l |= 1 << gpio;
|
||||
|
|
|
@ -345,8 +345,6 @@
|
|||
#define INT_34XX_MMC3_IRQ 94
|
||||
#define INT_34XX_GPT12_IRQ 95
|
||||
|
||||
#define INT_34XX_BENCH_MPU_EMUL 3
|
||||
|
||||
#define INT_35XX_HECC0_IRQ 24
|
||||
#define INT_35XX_HECC1_IRQ 28
|
||||
#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
|
||||
|
|
|
@ -59,7 +59,7 @@
|
|||
#define OMAP44XX_MCBSP1_BASE 0x49022000
|
||||
#define OMAP44XX_MCBSP2_BASE 0x49024000
|
||||
#define OMAP44XX_MCBSP3_BASE 0x49026000
|
||||
#define OMAP44XX_MCBSP4_BASE 0x48074000
|
||||
#define OMAP44XX_MCBSP4_BASE 0x48096000
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
||||
|
||||
|
|
|
@ -29,4 +29,11 @@ struct omap_nand_platform_data {
|
|||
/* size (4 KiB) for IO mapping */
|
||||
#define NAND_IO_SIZE SZ_4K
|
||||
|
||||
#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
|
||||
extern int gpmc_nand_init(struct omap_nand_platform_data *d);
|
||||
#else
|
||||
static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -32,7 +32,7 @@
|
|||
#define OMAP4430_PRM_BASE 0x4a306000
|
||||
#define OMAP44XX_GPMC_BASE 0x50000000
|
||||
#define OMAP443X_SCM_BASE 0x4a002000
|
||||
#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
|
||||
#define OMAP443X_CTRL_BASE 0x4a100000
|
||||
#define OMAP44XX_IC_BASE 0x48200000
|
||||
#define OMAP44XX_IVA_INTC_BASE 0x40000000
|
||||
#define IRQ_SIR_IRQ 0x0040
|
||||
|
|
|
@ -294,8 +294,8 @@ struct omap_hwmod_class_sysconfig {
|
|||
u16 rev_offs;
|
||||
u16 sysc_offs;
|
||||
u16 syss_offs;
|
||||
u16 sysc_flags;
|
||||
u8 idlemodes;
|
||||
u8 sysc_flags;
|
||||
u8 clockact;
|
||||
struct omap_hwmod_sysc_fields *sysc_fields;
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue