From b5e29cf7617cfae70a5d8b850b26cd3cdd7deaa0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 22 Oct 2021 21:15:13 +0800 Subject: [PATCH 1/5] clk: imx: imx8ulp: set suppress_bind_attrs to true The clock driver is registered as platform devices and it is possible to reloading the driver at runtime. But actually the clocks should never be removed to make system work, attempting to bind again would result in a crash, because almost all devices depends on clock to function well. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20211022131513.17381-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8ulp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c index 6699437e17b8..8eb1af2d6429 100644 --- a/drivers/clk/imx/clk-imx8ulp.c +++ b/drivers/clk/imx/clk-imx8ulp.c @@ -559,6 +559,7 @@ static struct platform_driver imx8ulp_clk_driver = { .probe = imx8ulp_clk_probe, .driver = { .name = KBUILD_MODNAME, + .suppress_bind_attrs = true, .of_match_table = imx8ulp_clk_dt_ids, }, }; From c1b6ad9a902539f9c037b6b3c35cb134c5724022 Mon Sep 17 00:00:00 2001 From: Changcheng Deng Date: Thu, 18 Nov 2021 08:06:34 +0000 Subject: [PATCH 2/5] clk: imx: Use div64_ul instead of do_div do_div() does a 64-by-32 division. Here the divisor is an unsigned long which on some platforms is 64 bit wide. So use div64_ul instead of do_div to avoid a possible truncation. Reported-by: Zeal Robot Signed-off-by: Changcheng Deng Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20211118080634.165275-1-deng.changcheng@zte.com.cn Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pllv3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 20ee9611ba6e..eea32f87c60a 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -247,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mfn = temp64; temp64 = (u64)parent_rate; @@ -277,7 +277,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mfn = temp64; val = readl_relaxed(pll->base); @@ -334,7 +334,7 @@ static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( /* rate = parent_rate * (mfi + mfn/mfd) */ temp64 = rate - parent_rate * mf.mfi; temp64 *= mf.mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mf.mfn = temp64; } From 570727e9acfac1c2330a01dd5e1272e9c3acec08 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 17 Nov 2021 07:32:02 -0600 Subject: [PATCH 3/5] clk: imx8mn: Fix imx8mn_clko1_sels When attempting to use sys_pll1_80m as the parent for clko1, the system hangs. This is due to the fact that the source select for sys_pll1_80m was incorrectly pointing to m7_alt_pll_clk, which doesn't yet exist. According to Rev 3 of the TRM, The imx8mn_clko1_sels also incorrectly references an osc_27m which does not exist, nor does an entry for source select bits 010b. Fix both by inserting a dummy clock into the missing space in the table and renaming the incorrectly name clock with dummy. Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Link: https://lore.kernel.org/r/20211117133202.775633-1-aford173@gmail.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mn.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index c55577604e16..021355a24708 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -277,9 +277,9 @@ static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audi static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; -static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", - "sys_pll1_200m", "audio_pll2_out", "vpu_pll", - "sys_pll1_80m", }; +static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", + "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", + "dummy", "sys_pll1_80m", }; static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", }; From 6deb3fb22da19e21ca5372fb34fb868bfceaf74c Mon Sep 17 00:00:00 2001 From: Hui Wang Date: Tue, 9 Nov 2021 20:56:56 +0800 Subject: [PATCH 4/5] clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h Since the commit b24e288d5063 ("clk: imx: Remove the audio ipg clock from imx8mp") removes the non-existing IPG_AUDIO_ROOT from the clk-imx8mp.c, and this definition is not used by anywhere, let us removed it in the imx8mp-clock.h as well. Signed-off-by: Hui Wang Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20211109125657.63485-1-hui.wang@canonical.com Signed-off-by: Abel Vesa --- include/dt-bindings/clock/imx8mp-clock.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 43927a1b9e94..235c7a00d379 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -117,7 +117,6 @@ #define IMX8MP_CLK_AUDIO_AHB 108 #define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 #define IMX8MP_CLK_IPG_ROOT 110 -#define IMX8MP_CLK_IPG_AUDIO_ROOT 111 #define IMX8MP_CLK_DRAM_ALT 112 #define IMX8MP_CLK_DRAM_APB 113 #define IMX8MP_CLK_VPU_G1 114 From 9dd81021084ff22cf88a180d720f4f4b47392059 Mon Sep 17 00:00:00 2001 From: Hui Wang Date: Tue, 9 Nov 2021 20:56:57 +0800 Subject: [PATCH 5/5] clk: imx8mp: Fix the parent clk of the audio_root_clk Having the parent of the audio_root_clk set to ipg_root in the clk-imx8mp.c, there is a hang happening when the audiomix IP regs are accessed. Switch parent to audio_ahb. And we could also refer to the section "5.1.4 System Clocks" of the IMX8MPRM.pdf, the parent clk of CCGR101 (Audiomix) is the AUDIO_AHB_CLK_ROOT. Signed-off-by: Hui Wang Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20211109125657.63485-2-hui.wang@canonical.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 12837304545d..c990ad37882b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -700,7 +700,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0); + hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "audio_ahb", ccm_base + 0x4650, 0); hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk,