Merge tag 'clk-samsung-4.5' of git://linuxtv.org/snawrocki/samsung into clk-next
drivers/clk/samsung updates (mostly bug fixes): - instantiation of the cpu clocks and addition of the GSCL IP parent clocks to the list of available consumer clocks for exynos542x SoCs; - MFC IP parent clock fix for exynos542x; - fix of locking bug in samsung/clk-cpu.c which caused system crashes with cpufreq enabled; - minor cleanup for s3c2410.
This commit is contained in:
Michael Turquette
commit
1807b34f95
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@ -148,6 +148,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
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unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
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unsigned long div0, div1 = 0, mux_reg;
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unsigned long flags;
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/* find out the divider values to use for clock data */
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while ((cfg_data->prate * 1000) != ndata->new_rate) {
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@ -156,7 +157,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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cfg_data++;
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}
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spin_lock(cpuclk->lock);
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spin_lock_irqsave(cpuclk->lock, flags);
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/*
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* For the selected PLL clock frequency, get the pre-defined divider
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@ -212,7 +213,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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DIV_MASK_ALL);
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}
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spin_unlock(cpuclk->lock);
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spin_unlock_irqrestore(cpuclk->lock, flags);
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return 0;
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}
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@ -223,6 +224,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long div = 0, div_mask = DIV_MASK;
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unsigned long mux_reg;
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unsigned long flags;
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/* find out the divider values to use for clock data */
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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@ -233,7 +235,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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}
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}
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spin_lock(cpuclk->lock);
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spin_lock_irqsave(cpuclk->lock, flags);
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/* select mout_apll as the alternate parent */
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mux_reg = readl(base + E4210_SRC_CPU);
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@ -246,7 +248,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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}
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exynos_set_safe_div(base, div, div_mask);
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spin_unlock(cpuclk->lock);
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spin_unlock_irqrestore(cpuclk->lock, flags);
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return 0;
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}
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@ -18,6 +18,7 @@
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#include <linux/syscore_ops.h>
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#include "clk.h"
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#include "clk-cpu.h"
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#define APLL_LOCK 0x0
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#define APLL_CON0 0x100
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@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
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MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
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MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
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MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
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MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
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MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
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MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
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CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
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MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
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MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
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@ -677,8 +680,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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SRC_TOP5, 20, 1),
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MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
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mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
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MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
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SRC_TOP5, 28, 1),
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MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
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mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
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MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
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MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
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@ -729,8 +732,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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SRC_TOP12, 20, 1),
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MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
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mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
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MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
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SRC_TOP12, 28, 1),
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MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
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mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
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/* DISP1 Block */
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MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
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@ -926,7 +929,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
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GATE_BUS_TOP, 13, 0, 0),
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GATE(0, "aclk166", "mout_user_aclk166",
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GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
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GATE(0, "aclk333", "mout_aclk333",
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GATE(0, "aclk333", "mout_user_aclk333",
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GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
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GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
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GATE_BUS_TOP, 16, 0, 0),
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@ -1246,6 +1249,74 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
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KPLL_CON0, NULL),
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};
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#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
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((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
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((cpud) << 4)))
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static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
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{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
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{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
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{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
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{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
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{ 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
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{ 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
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{ 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
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{ 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
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{ 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
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{ 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
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{ 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
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{ 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
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{ 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
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{ 0 },
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};
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static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
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{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
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{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
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{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
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{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
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{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
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{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
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{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
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{ 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
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{ 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
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{ 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
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{ 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
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{ 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
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{ 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
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{ 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
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{ 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
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{ 0 },
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};
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#define E5420_KFC_DIV(kpll, pclk, aclk) \
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((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
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static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
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{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
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{ 1300000, E5420_KFC_DIV(3, 5, 2), },
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{ 1200000, E5420_KFC_DIV(3, 5, 2), },
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{ 1100000, E5420_KFC_DIV(3, 5, 2), },
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{ 1000000, E5420_KFC_DIV(3, 5, 2), },
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{ 900000, E5420_KFC_DIV(3, 5, 2), },
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{ 800000, E5420_KFC_DIV(3, 5, 2), },
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{ 700000, E5420_KFC_DIV(3, 4, 2), },
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{ 600000, E5420_KFC_DIV(3, 4, 2), },
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{ 500000, E5420_KFC_DIV(3, 4, 2), },
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{ 400000, E5420_KFC_DIV(3, 3, 2), },
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{ 300000, E5420_KFC_DIV(3, 3, 2), },
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{ 200000, E5420_KFC_DIV(3, 3, 2), },
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{ 0 },
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};
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static const struct of_device_id ext_clk_match[] __initconst = {
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{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
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{ },
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@ -1310,6 +1381,19 @@ static void __init exynos5x_clk_init(struct device_node *np,
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ARRAY_SIZE(exynos5800_gate_clks));
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}
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if (soc == EXYNOS5420) {
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_cpu_p[0], mout_cpu_p[1], 0x200,
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exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
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} else {
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_cpu_p[0], mout_cpu_p[1], 0x200,
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exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
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}
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exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
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mout_kfc_p[0], mout_kfc_p[1], 0x28200,
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exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
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exynos5420_clk_sleep_init();
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samsung_clk_of_add_provider(np, ctx);
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@ -77,12 +77,11 @@ static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
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static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
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{
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struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
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int ret = 0;
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s3c2410_modify_misccr((clkout->mask << clkout->shift),
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(index << clkout->shift));
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return ret;
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return 0;
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}
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static const struct clk_ops s3c24xx_clkout_ops = {
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@ -25,6 +25,8 @@
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#define CLK_FOUT_MPLL 10
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#define CLK_FOUT_BPLL 11
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#define CLK_FOUT_KPLL 12
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#define CLK_ARM_CLK 13
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#define CLK_KFC_CLK 14
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/* gate for special clocks (sclk) */
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#define CLK_SCLK_UART0 128
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@ -210,6 +212,8 @@
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#define CLK_MOUT_SW_ACLK300 649
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#define CLK_MOUT_USER_ACLK400_DISP1 650
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#define CLK_MOUT_SW_ACLK400 651
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#define CLK_MOUT_USER_ACLK300_GSCL 652
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#define CLK_MOUT_SW_ACLK300_GSCL 653
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/* divider clocks */
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#define CLK_DOUT_PIXEL 768
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