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spi: atmel-quadspi: drop wrappers for iomem accesses 

The wrappers hid that the accesses are relaxed. Drop them.

Suggested-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Tudor Ambarus 2019-02-05 17:33:11 +00:00 committed by Mark Brown
parent 3ae012e9df
commit 18b6f6e176
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 17 additions and 28 deletions
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45
drivers/spi/atmel-quadspi.c
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@ -175,17 +175,6 @@ static const struct qspi_mode sama5d2_qspi_modes[] = {
{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
}; };
/* Register access functions */
static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg)
{
return readl_relaxed(aq->regs + reg);
}
static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value)
{
writel_relaxed(value, aq->regs + reg);
}
static inline bool is_compatible(const struct spi_mem_op *op, static inline bool is_compatible(const struct spi_mem_op *op,
const struct qspi_mode *mode) const struct qspi_mode *mode)
{ {
@ -243,7 +232,7 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
* Serial Memory Mode (SMM). * Serial Memory Mode (SMM).
*/ */
if (aq->mr != QSPI_MR_SMM) { if (aq->mr != QSPI_MR_SMM) {
qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
aq->mr = QSPI_MR_SMM; aq->mr = QSPI_MR_SMM;
} }
@ -303,17 +292,17 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE; ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE;
/* Clear pending interrupts */ /* Clear pending interrupts */
(void)qspi_readl(aq, QSPI_SR); (void)readl_relaxed(aq->regs + QSPI_SR);
/* Set QSPI Instruction Frame registers */ /* Set QSPI Instruction Frame registers */
qspi_writel(aq, QSPI_IAR, iar); writel_relaxed(iar, aq->regs + QSPI_IAR);
qspi_writel(aq, QSPI_ICR, icr); writel_relaxed(icr, aq->regs + QSPI_ICR);
qspi_writel(aq, QSPI_IFR, ifr); writel_relaxed(ifr, aq->regs + QSPI_IFR);
/* Skip to the final steps if there is no data */ /* Skip to the final steps if there is no data */
if (op->data.nbytes) { if (op->data.nbytes) {
/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
(void)qspi_readl(aq, QSPI_IFR); (void)readl_relaxed(aq->regs + QSPI_IFR);
/* Send/Receive data */ /* Send/Receive data */
if (op->data.dir == SPI_MEM_DATA_IN) if (op->data.dir == SPI_MEM_DATA_IN)
@ -324,22 +313,22 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
op->data.buf.out, op->data.nbytes); op->data.buf.out, op->data.nbytes);
/* Release the chip-select */ /* Release the chip-select */
qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER); writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
} }
/* Poll INSTRuction End status */ /* Poll INSTRuction End status */
sr = qspi_readl(aq, QSPI_SR); sr = readl_relaxed(aq->regs + QSPI_SR);
if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
return err; return err;
/* Wait for INSTRuction End interrupt */ /* Wait for INSTRuction End interrupt */
reinit_completion(&aq->cmd_completion); reinit_completion(&aq->cmd_completion);
aq->pending = sr & QSPI_SR_CMD_COMPLETED; aq->pending = sr & QSPI_SR_CMD_COMPLETED;
qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED); writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
if (!wait_for_completion_timeout(&aq->cmd_completion, if (!wait_for_completion_timeout(&aq->cmd_completion,
msecs_to_jiffies(1000))) msecs_to_jiffies(1000)))
err = -ETIMEDOUT; err = -ETIMEDOUT;
qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED); writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
return err; return err;
} }
@ -378,7 +367,7 @@ static int atmel_qspi_setup(struct spi_device *spi)
scbr--; scbr--;
scr = QSPI_SCR_SCBR(scbr); scr = QSPI_SCR_SCBR(scbr);
qspi_writel(aq, QSPI_SCR, scr); writel_relaxed(scr, aq->regs + QSPI_SCR);
return 0; return 0;
} }
@ -386,14 +375,14 @@ static int atmel_qspi_setup(struct spi_device *spi)
static int atmel_qspi_init(struct atmel_qspi *aq) static int atmel_qspi_init(struct atmel_qspi *aq)
{ {
/* Reset the QSPI controller */ /* Reset the QSPI controller */
qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST); writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
/* Set the QSPI controller by default in Serial Memory Mode */ /* Set the QSPI controller by default in Serial Memory Mode */
qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
aq->mr = QSPI_MR_SMM; aq->mr = QSPI_MR_SMM;
/* Enable the QSPI controller */ /* Enable the QSPI controller */
qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN); writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
return 0; return 0;
} }
@ -403,8 +392,8 @@ static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
struct atmel_qspi *aq = (struct atmel_qspi *)dev_id; struct atmel_qspi *aq = (struct atmel_qspi *)dev_id;
u32 status, mask, pending; u32 status, mask, pending;
status = qspi_readl(aq, QSPI_SR); status = readl_relaxed(aq->regs + QSPI_SR);
mask = qspi_readl(aq, QSPI_IMR); mask = readl_relaxed(aq->regs + QSPI_IMR);
pending = status & mask; pending = status & mask;
if (!pending) if (!pending)
@ -510,7 +499,7 @@ static int atmel_qspi_remove(struct platform_device *pdev)
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
spi_unregister_controller(ctrl); spi_unregister_controller(ctrl);
qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS); writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
clk_disable_unprepare(aq->clk); clk_disable_unprepare(aq->clk);
return 0; return 0;
} }