drm/i915: Pass new_config down do crtc_compute_clock
This reduces the number of direct users of crtc->new_config, opening up the possibilty of removing it altogether. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ander Conselvan de Oliveira
Daniel Vetter
parent
2d112de7db
commit
190f68c5e9
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@ -541,7 +541,8 @@ struct drm_i915_display_funcs {
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struct intel_crtc_state *);
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void (*get_plane_config)(struct intel_crtc *,
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struct intel_plane_config *);
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int (*crtc_compute_clock)(struct intel_crtc *crtc);
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int (*crtc_compute_clock)(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state);
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void (*crtc_enable)(struct drm_crtc *crtc);
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void (*crtc_disable)(struct drm_crtc *crtc);
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void (*off)(struct drm_crtc *crtc);
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@ -909,6 +909,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
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static bool
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hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state,
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struct intel_encoder *intel_encoder,
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int clock)
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{
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@ -923,16 +924,16 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
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WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
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WRPLL_DIVIDER_POST(p);
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intel_crtc->new_config->dpll_hw_state.wrpll = val;
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crtc_state->dpll_hw_state.wrpll = val;
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pll = intel_get_shared_dpll(intel_crtc);
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pll = intel_get_shared_dpll(intel_crtc, crtc_state);
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if (pll == NULL) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
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pipe_name(intel_crtc->pipe));
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return false;
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}
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intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
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crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
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}
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return true;
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@ -1095,6 +1096,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
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static bool
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skl_ddi_pll_select(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state,
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struct intel_encoder *intel_encoder,
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int clock)
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{
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@ -1144,11 +1146,11 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
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} else /* eDP */
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return true;
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intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
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intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
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intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
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crtc_state->dpll_hw_state.ctrl1 = ctrl1;
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crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
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crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
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pll = intel_get_shared_dpll(intel_crtc);
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pll = intel_get_shared_dpll(intel_crtc, crtc_state);
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if (pll == NULL) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
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pipe_name(intel_crtc->pipe));
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@ -1156,7 +1158,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
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}
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/* shared DPLL id 0 is DPLL 1 */
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intel_crtc->new_config->ddi_pll_sel = pll->id + 1;
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crtc_state->ddi_pll_sel = pll->id + 1;
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return true;
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}
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@ -1168,17 +1170,20 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
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* For private DPLLs, compute_config() should do the selection for us. This
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* function should be folded into compute_config() eventually.
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*/
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bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
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bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct intel_encoder *intel_encoder =
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intel_ddi_get_crtc_new_encoder(intel_crtc);
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int clock = intel_crtc->new_config->port_clock;
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int clock = crtc_state->port_clock;
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if (IS_SKYLAKE(dev))
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return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
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return skl_ddi_pll_select(intel_crtc, crtc_state,
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intel_encoder, clock);
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else
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return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
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return hsw_ddi_pll_select(intel_crtc, crtc_state,
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intel_encoder, clock);
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}
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void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
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@ -3861,7 +3861,8 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
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crtc->config.shared_dpll = DPLL_ID_PRIVATE;
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}
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struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
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struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct intel_shared_dpll *pll;
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@ -3887,7 +3888,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
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if (pll->new_config->crtc_mask == 0)
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continue;
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if (memcmp(&crtc->new_config->dpll_hw_state,
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if (memcmp(&crtc_state->dpll_hw_state,
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&pll->new_config->hw_state,
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sizeof(pll->new_config->hw_state)) == 0) {
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DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
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@ -3912,9 +3913,9 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
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found:
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if (pll->new_config->crtc_mask == 0)
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pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
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pll->new_config->hw_state = crtc_state->dpll_hw_state;
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crtc->new_config->shared_dpll = i;
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crtc_state->shared_dpll = i;
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DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
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pipe_name(crtc->pipe));
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@ -5729,30 +5730,31 @@ static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
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}
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static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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intel_clock_t *reduced_clock)
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{
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struct drm_device *dev = crtc->base.dev;
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u32 fp, fp2 = 0;
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if (IS_PINEVIEW(dev)) {
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fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
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fp = pnv_dpll_compute_fp(&crtc_state->dpll);
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if (reduced_clock)
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fp2 = pnv_dpll_compute_fp(reduced_clock);
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} else {
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fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
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fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
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if (reduced_clock)
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fp2 = i9xx_dpll_compute_fp(reduced_clock);
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}
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crtc->new_config->dpll_hw_state.fp0 = fp;
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crtc_state->dpll_hw_state.fp0 = fp;
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crtc->lowfreq_avail = false;
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if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
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reduced_clock && i915.powersave) {
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crtc->new_config->dpll_hw_state.fp1 = fp2;
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crtc_state->dpll_hw_state.fp1 = fp2;
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crtc->lowfreq_avail = true;
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} else {
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crtc->new_config->dpll_hw_state.fp1 = fp;
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crtc_state->dpll_hw_state.fp1 = fp;
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}
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}
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@ -6087,6 +6089,7 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
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}
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static void i9xx_update_pll(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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intel_clock_t *reduced_clock,
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int num_connectors)
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{
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@ -6094,9 +6097,9 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dpll;
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bool is_sdvo;
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struct dpll *clock = &crtc->new_config->dpll;
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struct dpll *clock = &crtc_state->dpll;
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i9xx_update_pll_dividers(crtc, reduced_clock);
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i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
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is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
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intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
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@ -6109,14 +6112,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
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dpll |= (crtc->new_config->pixel_multiplier - 1)
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dpll |= (crtc_state->pixel_multiplier - 1)
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<< SDVO_MULTIPLIER_SHIFT_HIRES;
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}
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if (is_sdvo)
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dpll |= DPLL_SDVO_HIGH_SPEED;
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if (crtc->new_config->has_dp_encoder)
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if (crtc_state->has_dp_encoder)
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dpll |= DPLL_SDVO_HIGH_SPEED;
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/* compute bitmask from p1 value */
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@ -6144,7 +6147,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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if (INTEL_INFO(dev)->gen >= 4)
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dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
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if (crtc->new_config->sdvo_tv_clock)
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if (crtc_state->sdvo_tv_clock)
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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@ -6153,25 +6156,26 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll |= DPLL_VCO_ENABLE;
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crtc->new_config->dpll_hw_state.dpll = dpll;
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crtc_state->dpll_hw_state.dpll = dpll;
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if (INTEL_INFO(dev)->gen >= 4) {
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u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
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u32 dpll_md = (crtc_state->pixel_multiplier - 1)
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
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crtc_state->dpll_hw_state.dpll_md = dpll_md;
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}
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}
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static void i8xx_update_pll(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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intel_clock_t *reduced_clock,
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int num_connectors)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dpll;
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struct dpll *clock = &crtc->new_config->dpll;
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struct dpll *clock = &crtc_state->dpll;
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i9xx_update_pll_dividers(crtc, reduced_clock);
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i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
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dpll = DPLL_VGA_MODE_DIS;
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@ -6196,7 +6200,7 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll |= DPLL_VCO_ENABLE;
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crtc->new_config->dpll_hw_state.dpll = dpll;
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crtc_state->dpll_hw_state.dpll = dpll;
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}
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static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
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@ -6392,7 +6396,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
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POSTING_READ(PIPECONF(intel_crtc->pipe));
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}
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static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
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static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -6424,7 +6429,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
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if (is_dsi)
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return 0;
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if (!crtc->new_config->clock_set) {
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if (!crtc_state->clock_set) {
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refclk = i9xx_get_refclk(crtc, num_connectors);
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/*
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@ -6435,7 +6440,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
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*/
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limit = intel_limit(crtc, refclk);
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ok = dev_priv->display.find_dpll(limit, crtc,
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crtc->new_config->port_clock,
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crtc_state->port_clock,
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refclk, NULL, &clock);
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if (!ok) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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@ -6456,23 +6461,23 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
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&reduced_clock);
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}
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/* Compat-code for transition, will disappear. */
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crtc->new_config->dpll.n = clock.n;
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crtc->new_config->dpll.m1 = clock.m1;
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crtc->new_config->dpll.m2 = clock.m2;
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crtc->new_config->dpll.p1 = clock.p1;
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crtc->new_config->dpll.p2 = clock.p2;
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crtc_state->dpll.n = clock.n;
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crtc_state->dpll.m1 = clock.m1;
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crtc_state->dpll.m2 = clock.m2;
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crtc_state->dpll.p1 = clock.p1;
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crtc_state->dpll.p2 = clock.p2;
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}
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if (IS_GEN2(dev)) {
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i8xx_update_pll(crtc,
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i8xx_update_pll(crtc, crtc_state,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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} else if (IS_CHERRYVIEW(dev)) {
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chv_update_pll(crtc, crtc->new_config);
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chv_update_pll(crtc, crtc_state);
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} else if (IS_VALLEYVIEW(dev)) {
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vlv_update_pll(crtc, crtc->new_config);
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vlv_update_pll(crtc, crtc_state);
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} else {
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i9xx_update_pll(crtc,
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i9xx_update_pll(crtc, crtc_state,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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}
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@ -7263,6 +7268,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
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}
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static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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intel_clock_t *clock,
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bool *has_reduced_clock,
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intel_clock_t *reduced_clock)
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@ -7285,7 +7291,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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*/
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limit = intel_limit(intel_crtc, refclk);
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ret = dev_priv->display.find_dpll(limit, intel_crtc,
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intel_crtc->new_config->port_clock,
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crtc_state->port_clock,
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refclk, NULL, clock);
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if (!ret)
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return false;
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@ -7324,6 +7330,7 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
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}
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static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state,
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u32 *fp,
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intel_clock_t *reduced_clock, u32 *fp2)
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{
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@ -7361,10 +7368,10 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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dev_priv->vbt.lvds_ssc_freq == 100000) ||
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(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
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factor = 25;
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} else if (intel_crtc->new_config->sdvo_tv_clock)
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} else if (crtc_state->sdvo_tv_clock)
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factor = 20;
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if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
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if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
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*fp |= FP_CB_TUNE;
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if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
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@ -7377,20 +7384,20 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
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dpll |= (crtc_state->pixel_multiplier - 1)
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<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
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if (is_sdvo)
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dpll |= DPLL_SDVO_HIGH_SPEED;
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if (intel_crtc->new_config->has_dp_encoder)
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if (crtc_state->has_dp_encoder)
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dpll |= DPLL_SDVO_HIGH_SPEED;
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||||
/* compute bitmask from p1 value */
|
||||
dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
|
||||
dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
|
||||
/* also FPA1 */
|
||||
dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
|
||||
dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
|
||||
|
||||
switch (intel_crtc->new_config->dpll.p2) {
|
||||
switch (crtc_state->dpll.p2) {
|
||||
case 5:
|
||||
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
|
||||
break;
|
||||
|
|
@ -7413,7 +7420,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
|
|||
return dpll | DPLL_VCO_ENABLE;
|
||||
}
|
||||
|
||||
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
|
||||
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_device *dev = crtc->base.dev;
|
||||
intel_clock_t clock, reduced_clock;
|
||||
|
|
@ -7427,39 +7435,39 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
|
|||
WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
|
||||
"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
|
||||
|
||||
ok = ironlake_compute_clocks(&crtc->base, &clock,
|
||||
ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
|
||||
&has_reduced_clock, &reduced_clock);
|
||||
if (!ok && !crtc->new_config->clock_set) {
|
||||
if (!ok && !crtc_state->clock_set) {
|
||||
DRM_ERROR("Couldn't find PLL settings for mode!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
/* Compat-code for transition, will disappear. */
|
||||
if (!crtc->new_config->clock_set) {
|
||||
crtc->new_config->dpll.n = clock.n;
|
||||
crtc->new_config->dpll.m1 = clock.m1;
|
||||
crtc->new_config->dpll.m2 = clock.m2;
|
||||
crtc->new_config->dpll.p1 = clock.p1;
|
||||
crtc->new_config->dpll.p2 = clock.p2;
|
||||
if (!crtc_state->clock_set) {
|
||||
crtc_state->dpll.n = clock.n;
|
||||
crtc_state->dpll.m1 = clock.m1;
|
||||
crtc_state->dpll.m2 = clock.m2;
|
||||
crtc_state->dpll.p1 = clock.p1;
|
||||
crtc_state->dpll.p2 = clock.p2;
|
||||
}
|
||||
|
||||
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
|
||||
if (crtc->new_config->has_pch_encoder) {
|
||||
fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
|
||||
if (crtc_state->has_pch_encoder) {
|
||||
fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
|
||||
if (has_reduced_clock)
|
||||
fp2 = i9xx_dpll_compute_fp(&reduced_clock);
|
||||
|
||||
dpll = ironlake_compute_dpll(crtc,
|
||||
dpll = ironlake_compute_dpll(crtc, crtc_state,
|
||||
&fp, &reduced_clock,
|
||||
has_reduced_clock ? &fp2 : NULL);
|
||||
|
||||
crtc->new_config->dpll_hw_state.dpll = dpll;
|
||||
crtc->new_config->dpll_hw_state.fp0 = fp;
|
||||
crtc_state->dpll_hw_state.dpll = dpll;
|
||||
crtc_state->dpll_hw_state.fp0 = fp;
|
||||
if (has_reduced_clock)
|
||||
crtc->new_config->dpll_hw_state.fp1 = fp2;
|
||||
crtc_state->dpll_hw_state.fp1 = fp2;
|
||||
else
|
||||
crtc->new_config->dpll_hw_state.fp1 = fp;
|
||||
crtc_state->dpll_hw_state.fp1 = fp;
|
||||
|
||||
pll = intel_get_shared_dpll(crtc);
|
||||
pll = intel_get_shared_dpll(crtc, crtc_state);
|
||||
if (pll == NULL) {
|
||||
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
|
||||
pipe_name(crtc->pipe));
|
||||
|
|
@ -7970,9 +7978,10 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
|
|||
intel_prepare_ddi(dev);
|
||||
}
|
||||
|
||||
static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
|
||||
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
if (!intel_ddi_pll_select(crtc))
|
||||
if (!intel_ddi_pll_select(crtc, crtc_state))
|
||||
return -EINVAL;
|
||||
|
||||
crtc->lowfreq_avail = false;
|
||||
|
|
@ -10957,7 +10966,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
|
|||
goto done;
|
||||
|
||||
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
|
||||
ret = dev_priv->display.crtc_compute_clock(intel_crtc);
|
||||
struct intel_crtc_state *state = intel_crtc->new_config;
|
||||
ret = dev_priv->display.crtc_compute_clock(intel_crtc,
|
||||
state);
|
||||
if (ret) {
|
||||
intel_shared_dpll_abort_config(dev_priv);
|
||||
goto done;
|
||||
|
|
|
|||
|
|
@ -831,7 +831,8 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
|
|||
enum transcoder cpu_transcoder);
|
||||
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
|
||||
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
|
||||
bool intel_ddi_pll_select(struct intel_crtc *crtc);
|
||||
bool intel_ddi_pll_select(struct intel_crtc *crtc,
|
||||
struct intel_crtc_state *crtc_state);
|
||||
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
|
||||
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
|
||||
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
|
||||
|
|
@ -944,7 +945,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
|
|||
bool state);
|
||||
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
|
||||
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
|
||||
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
|
||||
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
|
||||
struct intel_crtc_state *state);
|
||||
void intel_put_shared_dpll(struct intel_crtc *crtc);
|
||||
|
||||
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
|
||||
|
|
|
|||
Loading…
Reference in New Issue