i2c: qup: Add V2 tags support
QUP from version 2.1.1 onwards, supports a new format of i2c command tags. Tag codes instructs the controller to perform a operation like read/write. This new tagging version supports bam dma and transfers of more than 256 bytes without 'stop' in between. Adding the support for the same. For each block a data_write/read tag and data_len tag is added to the output fifo. For the final block of data write_stop/read_stop tag is used. Signed-off-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Sricharan R
Wolfram Sang
parent
c4f0c5fb38
commit
191424bb61
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@ -42,6 +42,7 @@
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#define QUP_IN_FIFO_BASE 0x218
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#define QUP_I2C_CLK_CTL 0x400
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#define QUP_I2C_STATUS 0x404
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#define QUP_I2C_MASTER_GEN 0x408
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/* QUP States and reset values */
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#define QUP_RESET_STATE 0
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@ -69,6 +70,8 @@
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#define QUP_CLOCK_AUTO_GATE BIT(13)
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#define I2C_MINI_CORE (2 << 8)
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#define I2C_N_VAL 15
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#define I2C_N_VAL_V2 7
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/* Most significant word offset in FIFO port */
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#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
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@ -79,6 +82,7 @@
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#define QUP_PACK_EN BIT(15)
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#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
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#define QUP_V2_TAGS_EN 1
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#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
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#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
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@ -91,6 +95,13 @@
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#define QUP_TAG_STOP (3 << 8)
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#define QUP_TAG_REC (4 << 8)
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/* QUP v2 tags */
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#define QUP_TAG_V2_START 0x81
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#define QUP_TAG_V2_DATAWR 0x82
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#define QUP_TAG_V2_DATAWR_STOP 0x83
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#define QUP_TAG_V2_DATARD 0x85
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#define QUP_TAG_V2_DATARD_STOP 0x87
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/* Status, Error flags */
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#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
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#define I2C_STATUS_BUS_ACTIVE BIT(8)
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@ -102,6 +113,15 @@
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#define RESET_BIT 0x0
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#define ONE_BYTE 0x1
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struct qup_i2c_block {
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int count;
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int pos;
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int tx_tag_len;
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int rx_tag_len;
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int data_len;
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u8 tags[6];
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};
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struct qup_i2c_dev {
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struct device *dev;
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void __iomem *base;
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@ -117,6 +137,7 @@ struct qup_i2c_dev {
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int in_blk_sz;
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unsigned long one_byte_t;
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struct qup_i2c_block blk;
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struct i2c_msg *msg;
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/* Current posion in user message buffer */
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@ -263,6 +284,24 @@ static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
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}
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}
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static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup,
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struct i2c_msg *msg)
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{
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/* Number of entries to shift out, including the tags */
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int total = msg->len + qup->blk.tx_tag_len;
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if (total < qup->out_fifo_sz) {
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/* FIFO mode */
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writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
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writel(total, qup->base + QUP_MX_WRITE_CNT);
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} else {
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/* BLOCK mode (transfer data on chunks) */
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writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
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qup->base + QUP_IO_MODE);
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writel(total, qup->base + QUP_MX_OUTPUT_CNT);
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}
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}
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static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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/* Number of entries to shift out, including the start */
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@ -324,9 +363,189 @@ static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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return ret;
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}
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static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
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struct i2c_msg *msg)
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{
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memset(&qup->blk, 0, sizeof(qup->blk));
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qup->blk.data_len = msg->len;
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qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
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/* 4 bytes for first block and 2 writes for rest */
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qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2;
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/* There are 2 tag bytes that are read in to fifo for every block */
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if (msg->flags & I2C_M_RD)
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qup->blk.rx_tag_len = qup->blk.count * 2;
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}
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static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
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int dlen, u8 *dbuf)
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{
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u32 val = 0, idx = 0, pos = 0, i = 0, t;
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int len = tlen + dlen;
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u8 *buf = tbuf;
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int ret = 0;
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while (len > 0) {
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ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL,
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RESET_BIT, 4 * ONE_BYTE);
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if (ret) {
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dev_err(qup->dev, "timeout for fifo out full");
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return ret;
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}
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t = (len >= 4) ? 4 : len;
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while (idx < t) {
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if (!i && (pos >= tlen)) {
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buf = dbuf;
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pos = 0;
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i = 1;
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}
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val |= buf[pos++] << (idx++ * 8);
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}
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writel(val, qup->base + QUP_OUT_FIFO_BASE);
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idx = 0;
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val = 0;
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len -= 4;
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}
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return ret;
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}
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static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
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{
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int data_len;
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if (qup->blk.data_len > QUP_READ_LIMIT)
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data_len = QUP_READ_LIMIT;
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else
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data_len = qup->blk.data_len;
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return data_len;
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}
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static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
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struct i2c_msg *msg)
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{
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u16 addr = (msg->addr << 1) | ((msg->flags & I2C_M_RD) == I2C_M_RD);
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int len = 0;
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int data_len;
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if (qup->blk.pos == 0) {
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tags[len++] = QUP_TAG_V2_START;
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tags[len++] = addr & 0xff;
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if (msg->flags & I2C_M_TEN)
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tags[len++] = addr >> 8;
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}
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/* Send _STOP commands for the last block */
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if (qup->blk.pos == (qup->blk.count - 1)) {
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if (msg->flags & I2C_M_RD)
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tags[len++] = QUP_TAG_V2_DATARD_STOP;
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else
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tags[len++] = QUP_TAG_V2_DATAWR_STOP;
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} else {
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if (msg->flags & I2C_M_RD)
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tags[len++] = QUP_TAG_V2_DATARD;
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else
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tags[len++] = QUP_TAG_V2_DATAWR;
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}
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data_len = qup_i2c_get_data_len(qup);
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/* 0 implies 256 bytes */
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if (data_len == QUP_READ_LIMIT)
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tags[len++] = 0;
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else
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tags[len++] = data_len;
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return len;
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}
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static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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int data_len = 0, tag_len, index;
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int ret;
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tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg);
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index = msg->len - qup->blk.data_len;
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/* only tags are written for read */
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if (!(msg->flags & I2C_M_RD))
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data_len = qup_i2c_get_data_len(qup);
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ret = qup_i2c_send_data(qup, tag_len, qup->blk.tags,
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data_len, &msg->buf[index]);
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qup->blk.data_len -= data_len;
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return ret;
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}
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static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
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struct i2c_msg *msg)
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{
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unsigned long left;
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int ret = 0;
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left = wait_for_completion_timeout(&qup->xfer, HZ);
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if (!left) {
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writel(1, qup->base + QUP_SW_RESET);
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ret = -ETIMEDOUT;
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}
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if (qup->bus_err || qup->qup_err) {
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if (qup->bus_err & QUP_I2C_NACK_FLAG) {
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dev_err(qup->dev, "NACK from %x\n", msg->addr);
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ret = -EIO;
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}
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}
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return ret;
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}
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static int qup_i2c_write_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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int ret = 0;
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qup->msg = msg;
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qup->pos = 0;
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enable_irq(qup->irq);
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qup_i2c_set_blk_data(qup, msg);
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qup_i2c_set_write_mode_v2(qup, msg);
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ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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if (ret)
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goto err;
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writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
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do {
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ret = qup_i2c_issue_xfer_v2(qup, msg);
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if (ret)
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goto err;
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ret = qup_i2c_wait_for_complete(qup, msg);
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if (ret)
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goto err;
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qup->blk.pos++;
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} while (qup->blk.pos < qup->blk.count);
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ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
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err:
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disable_irq(qup->irq);
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qup->msg = NULL;
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return ret;
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}
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static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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int ret;
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qup->msg = msg;
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@ -355,19 +574,9 @@ static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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if (ret)
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goto err;
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left = wait_for_completion_timeout(&qup->xfer, HZ);
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if (!left) {
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writel(1, qup->base + QUP_SW_RESET);
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ret = -ETIMEDOUT;
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ret = qup_i2c_wait_for_complete(qup, msg);
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if (ret)
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goto err;
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}
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if (qup->bus_err || qup->qup_err) {
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if (qup->bus_err & QUP_I2C_NACK_FLAG)
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dev_err(qup->dev, "NACK from %x\n", msg->addr);
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ret = -EIO;
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goto err;
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}
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} while (qup->pos < msg->len);
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/* Wait for the outstanding data in the fifo to drain */
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@ -394,6 +603,26 @@ static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
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}
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}
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static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
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{
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int tx_len = qup->blk.tx_tag_len;
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len += qup->blk.rx_tag_len;
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if (len < qup->in_fifo_sz) {
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/* FIFO mode */
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writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
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writel(len, qup->base + QUP_MX_READ_CNT);
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writel(tx_len, qup->base + QUP_MX_WRITE_CNT);
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} else {
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/* BLOCK mode (transfer data on chunks) */
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writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
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qup->base + QUP_IO_MODE);
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writel(len, qup->base + QUP_MX_INPUT_CNT);
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writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT);
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}
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}
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static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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u32 addr, len, val;
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@ -434,16 +663,90 @@ static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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return ret;
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}
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static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
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struct i2c_msg *msg)
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{
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u32 val;
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int idx, pos = 0, ret = 0, total;
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total = qup_i2c_get_data_len(qup);
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/* 2 extra bytes for read tags */
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while (pos < (total + 2)) {
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/* Check that FIFO have data */
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ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
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SET_BIT, 4 * ONE_BYTE);
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if (ret) {
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dev_err(qup->dev, "timeout for fifo not empty");
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return ret;
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}
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val = readl(qup->base + QUP_IN_FIFO_BASE);
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for (idx = 0; idx < 4; idx++, val >>= 8, pos++) {
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/* first 2 bytes are tag bytes */
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if (pos < 2)
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continue;
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if (pos >= (total + 2))
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goto out;
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msg->buf[qup->pos++] = val & 0xff;
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}
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}
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out:
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qup->blk.data_len -= total;
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return ret;
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}
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static int qup_i2c_read_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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int ret = 0;
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qup->msg = msg;
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qup->pos = 0;
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enable_irq(qup->irq);
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qup_i2c_set_blk_data(qup, msg);
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qup_i2c_set_read_mode_v2(qup, msg->len);
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ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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if (ret)
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goto err;
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writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
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do {
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ret = qup_i2c_issue_xfer_v2(qup, msg);
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if (ret)
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goto err;
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ret = qup_i2c_wait_for_complete(qup, msg);
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if (ret)
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goto err;
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ret = qup_i2c_read_fifo_v2(qup, msg);
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if (ret)
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goto err;
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qup->blk.pos++;
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} while (qup->blk.pos < qup->blk.count);
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err:
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disable_irq(qup->irq);
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qup->msg = NULL;
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return ret;
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}
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static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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unsigned long left;
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int ret;
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qup->msg = msg;
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qup->pos = 0;
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enable_irq(qup->irq);
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qup_i2c_set_read_mode(qup, msg->len);
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ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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@ -463,19 +766,9 @@ static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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goto err;
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do {
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left = wait_for_completion_timeout(&qup->xfer, HZ);
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if (!left) {
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writel(1, qup->base + QUP_SW_RESET);
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ret = -ETIMEDOUT;
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ret = qup_i2c_wait_for_complete(qup, msg);
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if (ret)
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goto err;
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}
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if (qup->bus_err || qup->qup_err) {
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if (qup->bus_err & QUP_I2C_NACK_FLAG)
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dev_err(qup->dev, "NACK from %x\n", msg->addr);
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ret = -EIO;
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goto err;
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}
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ret = qup_i2c_read_fifo(qup, msg);
|
||||
if (ret)
|
||||
|
|
@ -542,6 +835,60 @@ static int qup_i2c_xfer(struct i2c_adapter *adap,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
|
||||
struct i2c_msg msgs[],
|
||||
int num)
|
||||
{
|
||||
struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
|
||||
int ret, idx;
|
||||
|
||||
ret = pm_runtime_get_sync(qup->dev);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
writel(1, qup->base + QUP_SW_RESET);
|
||||
ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* Configure QUP as I2C mini core */
|
||||
writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
|
||||
writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
|
||||
|
||||
for (idx = 0; idx < num; idx++) {
|
||||
if (msgs[idx].len == 0) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (qup_i2c_poll_state_i2c_master(qup)) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
reinit_completion(&qup->xfer);
|
||||
|
||||
if (msgs[idx].flags & I2C_M_RD)
|
||||
ret = qup_i2c_read_one_v2(qup, &msgs[idx]);
|
||||
else
|
||||
ret = qup_i2c_write_one_v2(qup, &msgs[idx]);
|
||||
|
||||
if (!ret)
|
||||
ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret == 0)
|
||||
ret = num;
|
||||
out:
|
||||
pm_runtime_mark_last_busy(qup->dev);
|
||||
pm_runtime_put_autosuspend(qup->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 qup_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
||||
|
|
@ -552,6 +899,11 @@ static const struct i2c_algorithm qup_i2c_algo = {
|
|||
.functionality = qup_i2c_func,
|
||||
};
|
||||
|
||||
static const struct i2c_algorithm qup_i2c_algo_v2 = {
|
||||
.master_xfer = qup_i2c_xfer_v2,
|
||||
.functionality = qup_i2c_func,
|
||||
};
|
||||
|
||||
/*
|
||||
* The QUP block will issue a NACK and STOP on the bus when reaching
|
||||
* the end of the read, the length of the read is specified as one byte
|
||||
|
|
@ -601,6 +953,13 @@ static int qup_i2c_probe(struct platform_device *pdev)
|
|||
|
||||
of_property_read_u32(node, "clock-frequency", &clk_freq);
|
||||
|
||||
if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
|
||||
qup->adap.algo = &qup_i2c_algo;
|
||||
qup->adap.quirks = &qup_i2c_quirks;
|
||||
} else {
|
||||
qup->adap.algo = &qup_i2c_algo_v2;
|
||||
}
|
||||
|
||||
/* We support frequencies up to FAST Mode (400KHz) */
|
||||
if (!clk_freq || clk_freq > 400000) {
|
||||
dev_err(qup->dev, "clock frequency not supported %d\n",
|
||||
|
|
@ -696,8 +1055,6 @@ static int qup_i2c_probe(struct platform_device *pdev)
|
|||
qup->out_blk_sz, qup->out_fifo_sz);
|
||||
|
||||
i2c_set_adapdata(&qup->adap, qup);
|
||||
qup->adap.algo = &qup_i2c_algo;
|
||||
qup->adap.quirks = &qup_i2c_quirks;
|
||||
qup->adap.dev.parent = qup->dev;
|
||||
qup->adap.dev.of_node = pdev->dev.of_node;
|
||||
strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
|
||||
|
|
|
|||
Loading…
Reference in New Issue