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ARM: socfpga: dts: add "altr,modrst-offset" property 

The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Dinh Nguyen 2015-07-24 14:05:06 -05:00 committed by Dinh Nguyen
parent 007bb689b3
commit 1a94acf858
3 changed files with 4 additions and 0 deletions
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2
Documentation/devicetree/bindings/reset/socfpga-reset.txt
View File

@ -3,6 +3,7 @@ Altera SOCFPGA Reset Manager
Required properties: Required properties:
- compatible : "altr,rst-mgr" - compatible : "altr,rst-mgr"
- reg : Should contain 1 register ranges(address and length) - reg : Should contain 1 register ranges(address and length)
- altr,modrst-offset : Should contain the offset of the first modrst register.
- #reset-cells: 1 - #reset-cells: 1
Example: Example:
@ -10,4 +11,5 @@ Example:
#reset-cells = <1>; #reset-cells = <1>;
compatible = "altr,rst-mgr"; compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>; reg = <0xffd05000 0x1000>;
altr,modrst-offset = <0x10>;
}; };

1
arch/arm/boot/dts/socfpga.dtsi
View File

@ -752,6 +752,7 @@ rst: rstmgr@ffd05000 {
#reset-cells = <1>; #reset-cells = <1>;
compatible = "altr,rst-mgr"; compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>; reg = <0xffd05000 0x1000>;
altr,modrst-offset = <0x10>;
}; };
usbphy0: usbphy@0 { usbphy0: usbphy@0 {

1
arch/arm/boot/dts/socfpga_arria10.dtsi
View File

@ -588,6 +588,7 @@ rst: rstmgr@ffd05000 {
#reset-cells = <1>; #reset-cells = <1>;
compatible = "altr,rst-mgr"; compatible = "altr,rst-mgr";
reg = <0xffd05000 0x100>; reg = <0xffd05000 0x100>;
altr,modrst-offset = <0x20>;
}; };
scu: snoop-control-unit@ffffc000 { scu: snoop-control-unit@ffffc000 {