soc: mediatek: add a fixed wait for SRAM stable
MT7622_POWER_DOMAIN_WB doesn't send an ACK when its managed SRAM becomes stable, which is not like the behavior the other power domains should have. Therefore, it's necessary for such a power domain to have a fixed and well-predefined duration to wait until its managed SRAM can be allowed to access by all functions running on the top. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -32,6 +32,7 @@
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#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
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#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
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#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
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#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
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#define MTK_SCPD_FWAIT_SRAM BIT(1)
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#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
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#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
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#define SPM_VDE_PWR_CON 0x0210
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#define SPM_VDE_PWR_CON 0x0210
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@ -237,11 +238,21 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
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val &= ~scpd->data->sram_pdn_bits;
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val &= ~scpd->data->sram_pdn_bits;
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writel(val, ctl_addr);
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writel(val, ctl_addr);
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/* wait until SRAM_PDN_ACK all 0 */
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/* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
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ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == 0,
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if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
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/*
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if (ret < 0)
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* Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
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goto err_pwr_ack;
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* MT7622_POWER_DOMAIN_WB and thus just a trivial setup is
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* applied here.
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*/
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usleep_range(12000, 12100);
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} else {
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ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == 0,
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
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if (ret < 0)
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goto err_pwr_ack;
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};
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if (scpd->data->bus_prot_mask) {
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if (scpd->data->bus_prot_mask) {
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ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
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ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
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@ -785,7 +796,7 @@ static const struct scp_domain_data scp_domain_data_mt7622[] = {
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.sram_pdn_ack_bits = 0,
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.sram_pdn_ack_bits = 0,
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.clk_id = {CLK_NONE},
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.clk_id = {CLK_NONE},
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.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
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.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
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},
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},
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};
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};
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