mtd: nand: denali: handle timing parameters by setup_data_interface()
Handling timing parameters in a driver's own way should be avoided
because it duplicates efforts of drivers/mtd/nand/nand_timings.c
Besides, this driver hard-codes Intel specific parameters such as
CLK_X=5, CLK_MULTI=4. Taking a certain device (Samsung K9WAG08U1A)
into account by get_samsung_nand_para() is weird as well.
Now, the core framework provides .setup_data_interface() hook, which
handles timing parameters in a generic manner.
While I am working on this, I found even more issues in the current
code, so fixed the following as well:
- In recent IP versions, WE_2_RE and TWHR2 share the same register.
Likewise for ADDR_2_DATA and TCWAW, CS_SETUP_CNT and TWB. When
updating one, the other must be masked. Otherwise, the other will
be set to 0, then timing settings will be broken.
- The recent IP release expanded the ADDR_2_DATA to 7-bit wide.
This register is related to tADL. As commit 74a332e78e ("mtd:
nand: timings: Fix tADL_min for ONFI 4.0 chips") addressed, the
ONFi 4.0 increased the minimum of tADL to 400 nsec. This may not
fit in the 6-bit ADDR_2_DATA in older versions. Check the IP
revision and handle this correctly, otherwise the register value
would wrap around.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Masahiro Yamada
Boris Brezillon
parent
959e9f2ae9
commit
1bb8866677
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@ -28,17 +28,6 @@
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MODULE_LICENSE("GPL");
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/*
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* We define a module parameter that allows the user to override
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* the hardware and decide what timing mode should be used.
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*/
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#define NAND_DEFAULT_TIMINGS -1
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static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
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module_param(onfi_timing_mode, int, S_IRUGO);
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MODULE_PARM_DESC(onfi_timing_mode,
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"Overrides default ONFI setting. -1 indicates use default timings");
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#define DENALI_NAND_NAME "denali-nand"
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/*
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@ -63,10 +52,12 @@ MODULE_PARM_DESC(onfi_timing_mode,
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#define CHIP_SELECT_INVALID -1
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/*
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* This macro divides two integers and rounds fractional values up
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* to the nearest integer value.
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* The bus interface clock, clk_x, is phase aligned with the core clock. The
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* clk_x is an integral multiple N of the core clk. The value N is configured
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* at IP delivery time, and its available value is 4, 5, or 6. We need to align
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* to the largest value to make it work with any possible configuration.
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*/
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#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
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#define DENALI_CLK_X_MULT 6
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/*
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* this macro allows us to convert from an MTD structure to our own
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@ -195,148 +186,6 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
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return PASS;
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}
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/*
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* this routine calculates the ONFI timing values for a given mode and
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* programs the clocking register accordingly. The mode is determined by
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* the get_onfi_nand_para routine.
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*/
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static void nand_onfi_timing_set(struct denali_nand_info *denali,
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uint16_t mode)
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{
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uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
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uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
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uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
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uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
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uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
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uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
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uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
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uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
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uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
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uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
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uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
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uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
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uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
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uint16_t dv_window = 0;
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uint16_t en_lo, en_hi;
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uint16_t acc_clks;
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uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
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en_lo = CEIL_DIV(Trp[mode], CLK_X);
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en_hi = CEIL_DIV(Treh[mode], CLK_X);
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#if ONFI_BLOOM_TIME
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if ((en_hi * CLK_X) < (Treh[mode] + 2))
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en_hi++;
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#endif
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if ((en_lo + en_hi) * CLK_X < Trc[mode])
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en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
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if ((en_lo + en_hi) < CLK_MULTI)
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en_lo += CLK_MULTI - en_lo - en_hi;
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while (dv_window < 8) {
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data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
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data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
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data_invalid = data_invalid_rhoh < data_invalid_rloh ?
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data_invalid_rhoh : data_invalid_rloh;
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dv_window = data_invalid - Trea[mode];
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if (dv_window < 8)
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en_lo++;
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}
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acc_clks = CEIL_DIV(Trea[mode], CLK_X);
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while (acc_clks * CLK_X - Trea[mode] < 3)
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acc_clks++;
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if (data_invalid - acc_clks * CLK_X < 2)
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dev_warn(denali->dev, "%s, Line %d: Warning!\n",
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__FILE__, __LINE__);
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addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
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re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
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re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
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we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
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cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
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if (cs_cnt == 0)
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cs_cnt = 1;
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if (Tcea[mode]) {
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while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
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cs_cnt++;
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}
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#if MODE5_WORKAROUND
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if (mode == 5)
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acc_clks = 5;
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#endif
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/* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
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if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
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ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
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acc_clks = 6;
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iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
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iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
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iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
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iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
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iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
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iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
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iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
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iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
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}
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/* queries the NAND device to see what ONFI modes it supports. */
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static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
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{
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int i;
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/*
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* we needn't to do a reset here because driver has already
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* reset all the banks before
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*/
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if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
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ONFI_TIMING_MODE__VALUE))
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return FAIL;
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for (i = 5; i > 0; i--) {
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if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
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(0x01 << i))
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break;
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}
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nand_onfi_timing_set(denali, i);
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/*
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* By now, all the ONFI devices we know support the page cache
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* rw feature. So here we enable the pipeline_rw_ahead feature
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*/
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/* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
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/* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
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return PASS;
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}
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static void get_samsung_nand_para(struct denali_nand_info *denali,
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uint8_t device_id)
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{
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if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
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/* Set timing register values according to datasheet */
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iowrite32(5, denali->flash_reg + ACC_CLKS);
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iowrite32(20, denali->flash_reg + RE_2_WE);
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iowrite32(12, denali->flash_reg + WE_2_RE);
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iowrite32(14, denali->flash_reg + ADDR_2_DATA);
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iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
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iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
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iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
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}
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}
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/*
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* Use the configuration feature register to determine the maximum number of
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* banks that the hardware supports.
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@ -352,58 +201,6 @@ static void detect_max_banks(struct denali_nand_info *denali)
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denali->max_banks <<= 1;
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}
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static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
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{
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uint16_t status = PASS;
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uint32_t id_bytes[8], addr;
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uint8_t maf_id, device_id;
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int i;
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/*
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* Use read id method to get device ID and other params.
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* For some NAND chips, controller can't report the correct
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* device ID by reading from DEVICE_ID register
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*/
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addr = MODE_11 | BANK(denali->flash_bank);
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index_addr(denali, addr | 0, 0x90);
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index_addr(denali, addr | 1, 0);
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for (i = 0; i < 8; i++)
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index_addr_read_data(denali, addr | 2, &id_bytes[i]);
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maf_id = id_bytes[0];
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device_id = id_bytes[1];
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if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
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ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
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if (FAIL == get_onfi_nand_para(denali))
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return FAIL;
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} else if (maf_id == 0xEC) { /* Samsung NAND */
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get_samsung_nand_para(denali, device_id);
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}
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dev_info(denali->dev,
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"Dump timing register values:\n"
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"acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
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"we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
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"rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
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ioread32(denali->flash_reg + ACC_CLKS),
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ioread32(denali->flash_reg + RE_2_WE),
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ioread32(denali->flash_reg + RE_2_RE),
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ioread32(denali->flash_reg + WE_2_RE),
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ioread32(denali->flash_reg + ADDR_2_DATA),
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ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
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ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
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ioread32(denali->flash_reg + CS_SETUP_CNT));
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/*
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* If the user specified to override the default timings
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* with a specific ONFI mode, we apply those changes here.
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*/
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if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
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nand_onfi_timing_set(denali, onfi_timing_mode);
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return status;
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}
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static void denali_set_intr_modes(struct denali_nand_info *denali,
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uint16_t INT_ENABLE)
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{
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@ -1209,7 +1006,121 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
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break;
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}
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}
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/* end NAND core entry points */
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#define DIV_ROUND_DOWN_ULL(ll, d) \
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({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
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static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
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const struct nand_data_interface *conf)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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const struct nand_sdr_timings *timings;
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unsigned long t_clk;
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int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
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int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
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int addr_2_data_mask;
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uint32_t tmp;
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timings = nand_get_sdr_timings(conf);
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if (IS_ERR(timings))
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return PTR_ERR(timings);
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/* clk_x period in picoseconds */
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t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
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if (!t_clk)
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return -EINVAL;
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if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
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return 0;
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/* tREA -> ACC_CLKS */
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acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk);
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acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
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tmp = ioread32(denali->flash_reg + ACC_CLKS);
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tmp &= ~ACC_CLKS__VALUE;
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tmp |= acc_clks;
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iowrite32(tmp, denali->flash_reg + ACC_CLKS);
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/* tRWH -> RE_2_WE */
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re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk);
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re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
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tmp = ioread32(denali->flash_reg + RE_2_WE);
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tmp &= ~RE_2_WE__VALUE;
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tmp |= re_2_we;
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iowrite32(tmp, denali->flash_reg + RE_2_WE);
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/* tRHZ -> RE_2_RE */
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re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk);
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re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
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tmp = ioread32(denali->flash_reg + RE_2_RE);
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tmp &= ~RE_2_RE__VALUE;
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tmp |= re_2_re;
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iowrite32(tmp, denali->flash_reg + RE_2_RE);
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/* tWHR -> WE_2_RE */
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we_2_re = DIV_ROUND_UP(timings->tWHR_min, t_clk);
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we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
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tmp = ioread32(denali->flash_reg + TWHR2_AND_WE_2_RE);
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tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
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tmp |= we_2_re;
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iowrite32(tmp, denali->flash_reg + TWHR2_AND_WE_2_RE);
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/* tADL -> ADDR_2_DATA */
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/* for older versions, ADDR_2_DATA is only 6 bit wide */
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addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
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if (denali->revision < 0x0501)
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addr_2_data_mask >>= 1;
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addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk);
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addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
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tmp = ioread32(denali->flash_reg + TCWAW_AND_ADDR_2_DATA);
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tmp &= ~addr_2_data_mask;
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tmp |= addr_2_data;
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iowrite32(tmp, denali->flash_reg + TCWAW_AND_ADDR_2_DATA);
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/* tREH, tWH -> RDWR_EN_HI_CNT */
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rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
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t_clk);
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rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
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tmp = ioread32(denali->flash_reg + RDWR_EN_HI_CNT);
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tmp &= ~RDWR_EN_HI_CNT__VALUE;
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tmp |= rdwr_en_hi;
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iowrite32(tmp, denali->flash_reg + RDWR_EN_HI_CNT);
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/* tRP, tWP -> RDWR_EN_LO_CNT */
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rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min),
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t_clk);
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rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
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t_clk);
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rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT);
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rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
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rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
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tmp = ioread32(denali->flash_reg + RDWR_EN_LO_CNT);
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tmp &= ~RDWR_EN_LO_CNT__VALUE;
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tmp |= rdwr_en_lo;
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iowrite32(tmp, denali->flash_reg + RDWR_EN_LO_CNT);
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/* tCS, tCEA -> CS_SETUP_CNT */
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cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo,
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(int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks,
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0);
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cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
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tmp = ioread32(denali->flash_reg + CS_SETUP_CNT);
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tmp &= ~CS_SETUP_CNT__VALUE;
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tmp |= cs_setup;
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iowrite32(tmp, denali->flash_reg + CS_SETUP_CNT);
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return 0;
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}
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/* Initialization code to bring the device up to a known good state */
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static void denali_hw_init(struct denali_nand_info *denali)
|
||||
|
|
@ -1241,7 +1152,6 @@ static void denali_hw_init(struct denali_nand_info *denali)
|
|||
/* Should set value for these registers when init */
|
||||
iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
|
||||
iowrite32(1, denali->flash_reg + ECC_ENABLE);
|
||||
denali_nand_timing_set(denali);
|
||||
denali_irq_init(denali);
|
||||
}
|
||||
|
||||
|
|
@ -1416,17 +1326,6 @@ int denali_init(struct denali_nand_info *denali)
|
|||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
int ret;
|
||||
|
||||
if (denali->platform == INTEL_CE4100) {
|
||||
/*
|
||||
* Due to a silicon limitation, we can only support
|
||||
* ONFI timing mode 1 and below.
|
||||
*/
|
||||
if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
|
||||
pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* allocate a temporary buffer for nand_scan_ident() */
|
||||
denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
|
||||
GFP_DMA | GFP_KERNEL);
|
||||
|
|
@ -1460,6 +1359,10 @@ int denali_init(struct denali_nand_info *denali)
|
|||
chip->onfi_set_features = nand_onfi_get_set_features_notsupp;
|
||||
chip->onfi_get_features = nand_onfi_get_set_features_notsupp;
|
||||
|
||||
/* clk rate info is needed for setup_data_interface */
|
||||
if (denali->clk_x_rate)
|
||||
chip->setup_data_interface = denali_setup_data_interface;
|
||||
|
||||
/*
|
||||
* scan for NAND devices attached to the controller
|
||||
* this is the first stage in a two step process to register
|
||||
|
|
|
|||
|
|
@ -72,11 +72,14 @@
|
|||
#define GLOBAL_INT_ENABLE 0xf0
|
||||
#define GLOBAL_INT_EN_FLAG BIT(0)
|
||||
|
||||
#define WE_2_RE 0x100
|
||||
#define WE_2_RE__VALUE GENMASK(5, 0)
|
||||
#define TWHR2_AND_WE_2_RE 0x100
|
||||
#define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
|
||||
#define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
|
||||
|
||||
#define ADDR_2_DATA 0x110
|
||||
#define ADDR_2_DATA__VALUE GENMASK(5, 0)
|
||||
#define TCWAW_AND_ADDR_2_DATA 0x110
|
||||
/* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
|
||||
#define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
|
||||
#define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
|
||||
|
||||
#define RE_2_WE 0x120
|
||||
#define RE_2_WE__VALUE GENMASK(5, 0)
|
||||
|
|
@ -128,6 +131,7 @@
|
|||
|
||||
#define CS_SETUP_CNT 0x220
|
||||
#define CS_SETUP_CNT__VALUE GENMASK(4, 0)
|
||||
#define CS_SETUP_CNT__TWB GENMASK(17, 12)
|
||||
|
||||
#define SPARE_AREA_SKIP_BYTES 0x230
|
||||
#define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
|
||||
|
|
@ -294,16 +298,8 @@
|
|||
#define CHNL_ACTIVE__CHANNEL2 BIT(2)
|
||||
#define CHNL_ACTIVE__CHANNEL3 BIT(3)
|
||||
|
||||
#define FAIL 1 /*failed flag*/
|
||||
#define PASS 0 /*success flag*/
|
||||
|
||||
#define CLK_X 5
|
||||
#define CLK_MULTI 4
|
||||
|
||||
#define ONFI_BLOOM_TIME 1
|
||||
#define MODE5_WORKAROUND 0
|
||||
|
||||
|
||||
#define MODE_00 0x00000000
|
||||
#define MODE_01 0x04000000
|
||||
#define MODE_10 0x08000000
|
||||
|
|
@ -316,14 +312,10 @@ struct nand_buf {
|
|||
dma_addr_t dma_buf;
|
||||
};
|
||||
|
||||
#define INTEL_CE4100 1
|
||||
#define INTEL_MRST 2
|
||||
#define DT 3
|
||||
|
||||
struct denali_nand_info {
|
||||
struct nand_chip nand;
|
||||
unsigned long clk_x_rate; /* bus interface clock rate */
|
||||
int flash_bank; /* currently selected chip */
|
||||
int platform;
|
||||
struct nand_buf buf;
|
||||
struct device *dev;
|
||||
int page;
|
||||
|
|
|
|||
|
|
@ -96,7 +96,6 @@ static int denali_dt_probe(struct platform_device *pdev)
|
|||
denali->ecc_caps = data->ecc_caps;
|
||||
}
|
||||
|
||||
denali->platform = DT;
|
||||
denali->dev = &pdev->dev;
|
||||
denali->irq = platform_get_irq(pdev, 0);
|
||||
if (denali->irq < 0) {
|
||||
|
|
@ -121,6 +120,8 @@ static int denali_dt_probe(struct platform_device *pdev)
|
|||
}
|
||||
clk_prepare_enable(dt->clk);
|
||||
|
||||
denali->clk_x_rate = clk_get_rate(dt->clk);
|
||||
|
||||
ret = denali_init(denali);
|
||||
if (ret)
|
||||
goto out_disable_clk;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,9 @@
|
|||
|
||||
#define DENALI_NAND_NAME "denali-nand-pci"
|
||||
|
||||
#define INTEL_CE4100 1
|
||||
#define INTEL_MRST 2
|
||||
|
||||
/* List of platforms this NAND controller has be integrated into */
|
||||
static const struct pci_device_id denali_pci_ids[] = {
|
||||
{ PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
|
||||
|
|
@ -47,13 +50,11 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
}
|
||||
|
||||
if (id->driver_data == INTEL_CE4100) {
|
||||
denali->platform = INTEL_CE4100;
|
||||
mem_base = pci_resource_start(dev, 0);
|
||||
mem_len = pci_resource_len(dev, 1);
|
||||
csr_base = pci_resource_start(dev, 1);
|
||||
csr_len = pci_resource_len(dev, 1);
|
||||
} else {
|
||||
denali->platform = INTEL_MRST;
|
||||
csr_base = pci_resource_start(dev, 0);
|
||||
csr_len = pci_resource_len(dev, 0);
|
||||
mem_base = pci_resource_start(dev, 1);
|
||||
|
|
@ -69,6 +70,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
denali->irq = dev->irq;
|
||||
denali->ecc_caps = &denali_pci_ecc_caps;
|
||||
denali->nand.ecc.options |= NAND_ECC_MAXIMIZE;
|
||||
denali->clk_x_rate = 200000000; /* 200 MHz */
|
||||
|
||||
ret = pci_request_regions(dev, DENALI_NAND_NAME);
|
||||
if (ret) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue