mvebu dt64 for 5.1 (part 1)
- Interrupt support to Armada 7K/8K thermal nodes - Armada 37xx related patches allowing to enable suspend to RAM (USB2, USB3, PCIe, SATA, DSA) - uDPU board support (Armada-3720 based):single-port FTTdp distribution point unit - Fixes for EspressoBin Ethernet support when using U-Boot mainline - cleanup for partitions under flashes nodes -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXF3x1wAKCRALBhiOFHI7 1ZtFAJ4pn8nIeHqWgYEUmWmCpQXnUoc4eQCgninj7JcAFV8KNLKhRCkKdlkeO38= =Wt6S -----END PGP SIGNATURE----- Merge tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu into arm/dt mvebu dt64 for 5.1 (part 1) - Interrupt support to Armada 7K/8K thermal nodes - Armada 37xx related patches allowing to enable suspend to RAM (USB2, USB3, PCIe, SATA, DSA) - uDPU board support (Armada-3720 based):single-port FTTdp distribution point unit - Fixes for EspressoBin Ethernet support when using U-Boot mainline - cleanup for partitions under flashes nodes * tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY property arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHY arm64: dts: marvell: armada-37xx: declare the COMPHY node arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashes arm64: dts: armada-3720-espressobin: Set mv88e6341 cpu port as RGMII-ID arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pins arm64: dts: marvell: Add device tree for uDPU board arm64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pin arm64: dts: marvell: armada-37xx: declare PCIe reset pin arm64: dts: marvell: armada-37xx: declare USB2 UTMI PHYs arm64: dts: marvell: armada-37xx: fix USB2 memory region arm64: dts: marvell: armada-37xx: declare SATA clock arm64: dts: marvell: armada-37xx: fix SATA node scope arm64: dts: marvell: add interrupt support to cp110 thermal node arm64: dts: marvell: add interrupt support to ap806 thermal node Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
1c2950563a
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@ -2,6 +2,7 @@
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# Mvebu SoC Family
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dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
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@ -46,11 +46,16 @@ vcc_sd_reg1: regulator {
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/* J9 */
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&pcie0 {
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status = "okay";
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phys = <&comphy1 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
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};
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/* J6 */
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&sata {
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status = "okay";
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phys = <&comphy2 0>;
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phy-names = "sata-phy";
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};
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/* J1 */
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@ -156,6 +161,11 @@ port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <ð0>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@1 {
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@ -196,6 +206,8 @@ switch0phy2: switch0phy2@13 {
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};
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ð0 {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
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phy-mode = "rgmii-id";
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status = "okay";
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@ -0,0 +1,162 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device tree for the uDPU board.
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* Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
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* Copyright (C) 2016 Marvell
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* Copyright (C) 2019 Methode Electronics
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* Copyright (C) 2019 Telus
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*
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* Vladimir Vid <vladimir.vid@sartura.hr>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-372x.dtsi"
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/ {
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model = "Methode uDPU Board";
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compatible = "methode,udpu", "marvell,armada3720";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
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};
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leds {
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pinctrl-names = "default";
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compatible = "gpio-leds";
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power1 {
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label = "udpu:green:power";
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gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
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};
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power2 {
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label = "udpu:red:power";
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gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
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};
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network1 {
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label = "udpu:green:network";
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gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
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};
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network2 {
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label = "udpu:red:network";
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gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
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};
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alarm1 {
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label = "udpu:green:alarm";
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gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
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};
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alarm2 {
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label = "udpu:red:alarm";
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gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
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};
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};
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sfp_eth0: sfp-eth0 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
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};
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sfp_eth1: sfp-eth1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
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};
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};
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&sdhci0 {
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status = "okay";
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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marvell,pad-type = "fixed-1-8v";
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non-removable;
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no-sd;
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no-sdio;
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};
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&spi0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi_quad_pins>;
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m25p80@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <54000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* only bootloader is located on the SPI */
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partition@0 {
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label = "uboot";
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reg = <0 0x400000>;
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};
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};
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};
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};
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&i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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lm75@48 {
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status = "okay";
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compatible = "lm75";
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reg = <0x48>;
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};
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lm75@49 {
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status = "okay";
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compatible = "lm75";
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reg = <0x49>;
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};
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};
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ð0 {
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phy-mode = "sgmii";
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status = "okay";
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managed = "in-band-status";
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sfp = <&sfp_eth0>;
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};
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ð1 {
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phy-mode = "sgmii";
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status = "okay";
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managed = "in-band-status";
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sfp = <&sfp_eth1>;
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};
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&usb3 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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@ -247,6 +247,35 @@ nb_pm: syscon@14000 {
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reg = <0x14000 0x60>;
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};
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comphy: phy@18300 {
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compatible = "marvell,comphy-a3700";
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reg = <0x18300 0x300>,
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<0x1F000 0x400>,
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<0x5C000 0x400>,
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<0xe0178 0x8>;
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reg-names = "comphy",
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"lane1_pcie_gbe",
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"lane0_usb3_gbe",
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"lane2_sata_usb3";
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#address-cells = <1>;
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#size-cells = <0>;
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comphy0: phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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comphy1: phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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comphy2: phy@2 {
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reg = <2>;
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#phy-cells = <1>;
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};
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};
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pinctrl_sb: pinctrl@18800 {
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compatible = "marvell,armada3710-sb-pinctrl",
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"syscon", "simple-mfd";
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@ -271,11 +300,25 @@ rgmii_pins: mii-pins {
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function = "mii";
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};
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smi_pins: smi-pins {
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groups = "smi";
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function = "smi";
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};
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sdio_pins: sdio-pins {
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groups = "sdio_sb";
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function = "sdio";
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};
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pcie_reset_pins: pcie-reset-pins {
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groups = "pcie1";
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function = "pcie";
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};
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pcie_clkreq_pins: pcie-clkreq-pins {
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groups = "pcie1_clkreq";
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function = "pcie";
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};
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};
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eth0: ethernet@30000 {
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@ -305,18 +348,50 @@ usb3: usb@58000 {
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compatible = "marvell,armada3700-xhci",
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"generic-xhci";
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reg = <0x58000 0x4000>;
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marvell,usb-misc-reg = <&usb32_syscon>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sb_periph_clk 12>;
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phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
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phy-names = "usb3-phy", "usb2-utmi-otg-phy";
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status = "disabled";
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};
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usb2_utmi_otg_phy: phy@5d000 {
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compatible = "marvell,a3700-utmi-otg-phy";
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reg = <0x5d000 0x800>;
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marvell,usb-misc-reg = <&usb32_syscon>;
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#phy-cells = <0>;
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};
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usb32_syscon: system-controller@5d800 {
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compatible = "marvell,armada-3700-usb2-host-device-misc",
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"syscon";
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reg = <0x5d800 0x800>;
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};
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usb2: usb@5e000 {
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compatible = "marvell,armada-3700-ehci";
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reg = <0x5e000 0x2000>;
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reg = <0x5e000 0x1000>;
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marvell,usb-misc-reg = <&usb2_syscon>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb2_utmi_host_phy>;
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phy-names = "usb2-utmi-host-phy";
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status = "disabled";
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};
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usb2_utmi_host_phy: phy@5f000 {
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compatible = "marvell,a3700-utmi-host-phy";
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reg = <0x5f000 0x800>;
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marvell,usb-misc-reg = <&usb2_syscon>;
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#phy-cells = <0>;
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};
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usb2_syscon: system-controller@5f800 {
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compatible = "marvell,armada-3700-usb2-host-misc",
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"syscon";
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reg = <0x5f800 0x800>;
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};
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xor@60900 {
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compatible = "marvell,armada-3700-xor";
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reg = <0x60900 0x100>,
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@ -368,8 +443,9 @@ sdhci0: sdhci@d8000 {
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sata: sata@e0000 {
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compatible = "marvell,armada-3700-ahci";
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reg = <0xe0000 0x2000>;
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reg = <0xe0000 0x178>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&nb_periph_clk 1>;
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status = "disabled";
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};
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@ -66,8 +66,6 @@ &spi0 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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@ -169,8 +167,6 @@ &cp0_spi1 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <20000000>;
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@ -81,8 +81,6 @@ &spi0 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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@ -214,8 +212,6 @@ &cp1_spi1 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <20000000>;
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@ -283,6 +283,8 @@ ap_syscon1: system-controller@6f8000 {
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ap_thermal: thermal-sensor@80 {
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compatible = "marvell,armada-ap806-thermal";
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reg = <0x80 0x10>;
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interrupt-parent = <&sei>;
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interrupts = <18>;
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#thermal-sensor-cells = <1>;
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};
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};
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|
@ -293,16 +295,26 @@ ap_thermal: thermal-sensor@80 {
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|||
* The thermal IP features one internal sensor plus, if applicable, one
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* remote channel wired to one sensor per CPU.
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||||
*
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||||
* Only one thermal zone per AP/CP may trigger interrupts at a time, the
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* first one that will have a critical trip point will be chosen.
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*
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* The cooling maps are always empty as there are no cooling devices.
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||||
*/
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thermal-zones {
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ap_thermal_ic: ap-thermal-ic {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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polling-delay-passive = <0>; /* Interrupt driven */
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polling-delay = <0>; /* Interrupt driven */
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thermal-sensors = <&ap_thermal 0>;
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||||
trips { };
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trips {
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||||
ap_crit: ap-crit {
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||||
temperature = <100000>; /* mC degrees */
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||||
hysteresis = <2000>; /* mC degrees */
|
||||
type = "critical";
|
||||
};
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||||
};
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||||
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||||
cooling-maps { };
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||||
};
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|
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|
@ -28,12 +28,19 @@ / {
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|||
*/
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||||
thermal-zones {
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||||
CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
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||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <0>; /* Interrupt driven */
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||||
polling-delay = <0>; /* Interrupt driven */
|
||||
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||||
thermal-sensors = <&CP110_LABEL(thermal) 0>;
|
||||
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||||
trips { };
|
||||
trips {
|
||||
CP110_LABEL(crit): crit {
|
||||
temperature = <100000>; /* mC degrees */
|
||||
hysteresis = <2000>; /* mC degrees */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
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||||
cooling-maps { };
|
||||
};
|
||||
};
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||||
|
@ -259,6 +266,8 @@ CP110_LABEL(syscon1): system-controller@400000 {
|
|||
CP110_LABEL(thermal): thermal-sensor@70 {
|
||||
compatible = "marvell,armada-cp110-thermal";
|
||||
reg = <0x70 0x10>;
|
||||
interrupts-extended =
|
||||
<&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue