mvebu dt64 for 5.1 (part 1)

- Interrupt support to Armada 7K/8K thermal nodes
  - Armada 37xx related patches allowing to enable suspend to RAM
    (USB2, USB3, PCIe, SATA, DSA)
  - uDPU board support (Armada-3720 based):single-port FTTdp
     distribution point unit
  - Fixes for EspressoBin Ethernet support when using U-Boot mainline
  - cleanup for partitions under flashes nodes
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Merge tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt64 for 5.1 (part 1)

 - Interrupt support to Armada 7K/8K thermal nodes
 - Armada 37xx related patches allowing to enable suspend to RAM
   (USB2, USB3, PCIe, SATA, DSA)
 - uDPU board support (Armada-3720 based):single-port FTTdp
    distribution point unit
 - Fixes for EspressoBin Ethernet support when using U-Boot mainline
 - cleanup for partitions under flashes nodes

* tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs
  arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY property
  arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHY
  arm64: dts: marvell: armada-37xx: declare the COMPHY node
  arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashes
  arm64: dts: armada-3720-espressobin: Set mv88e6341 cpu port as RGMII-ID
  arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pins
  arm64: dts: marvell: Add device tree for uDPU board
  arm64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pin
  arm64: dts: marvell: armada-37xx: declare PCIe reset pin
  arm64: dts: marvell: armada-37xx: declare USB2 UTMI PHYs
  arm64: dts: marvell: armada-37xx: fix USB2 memory region
  arm64: dts: marvell: armada-37xx: declare SATA clock
  arm64: dts: marvell: armada-37xx: fix SATA node scope
  arm64: dts: marvell: add interrupt support to cp110 thermal node
  arm64: dts: marvell: add interrupt support to ap806 thermal node

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-02-15 16:00:18 +01:00
commit 1c2950563a
8 changed files with 280 additions and 16 deletions

View File

@ -2,6 +2,7 @@
# Mvebu SoC Family
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb

View File

@ -46,11 +46,16 @@ vcc_sd_reg1: regulator {
/* J9 */
&pcie0 {
status = "okay";
phys = <&comphy1 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
};
/* J6 */
&sata {
status = "okay";
phys = <&comphy2 0>;
phy-names = "sata-phy";
};
/* J1 */
@ -156,6 +161,11 @@ port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
@ -196,6 +206,8 @@ switch0phy2: switch0phy2@13 {
};
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii-id";
status = "okay";

View File

@ -0,0 +1,162 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device tree for the uDPU board.
* Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
* Copyright (C) 2016 Marvell
* Copyright (C) 2019 Methode Electronics
* Copyright (C) 2019 Telus
*
* Vladimir Vid <vladimir.vid@sartura.hr>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
model = "Methode uDPU Board";
compatible = "methode,udpu", "marvell,armada3720";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
leds {
pinctrl-names = "default";
compatible = "gpio-leds";
power1 {
label = "udpu:green:power";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
power2 {
label = "udpu:red:power";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
network1 {
label = "udpu:green:network";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
};
network2 {
label = "udpu:red:network";
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
alarm1 {
label = "udpu:green:alarm";
gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
};
alarm2 {
label = "udpu:red:alarm";
gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
};
};
sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
};
sfp_eth1: sfp-eth1 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
};
};
&sdhci0 {
status = "okay";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
non-removable;
no-sd;
no-sdio;
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <54000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* only bootloader is located on the SPI */
partition@0 {
label = "uboot";
reg = <0 0x400000>;
};
};
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
lm75@48 {
status = "okay";
compatible = "lm75";
reg = <0x48>;
};
lm75@49 {
status = "okay";
compatible = "lm75";
reg = <0x49>;
};
};
&eth0 {
phy-mode = "sgmii";
status = "okay";
managed = "in-band-status";
sfp = <&sfp_eth0>;
};
&eth1 {
phy-mode = "sgmii";
status = "okay";
managed = "in-band-status";
sfp = <&sfp_eth1>;
};
&usb3 {
status = "okay";
};
&uart0 {
status = "okay";
};

View File

@ -247,6 +247,35 @@ nb_pm: syscon@14000 {
reg = <0x14000 0x60>;
};
comphy: phy@18300 {
compatible = "marvell,comphy-a3700";
reg = <0x18300 0x300>,
<0x1F000 0x400>,
<0x5C000 0x400>,
<0xe0178 0x8>;
reg-names = "comphy",
"lane1_pcie_gbe",
"lane0_usb3_gbe",
"lane2_sata_usb3";
#address-cells = <1>;
#size-cells = <0>;
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
};
pinctrl_sb: pinctrl@18800 {
compatible = "marvell,armada3710-sb-pinctrl",
"syscon", "simple-mfd";
@ -271,11 +300,25 @@ rgmii_pins: mii-pins {
function = "mii";
};
smi_pins: smi-pins {
groups = "smi";
function = "smi";
};
sdio_pins: sdio-pins {
groups = "sdio_sb";
function = "sdio";
};
pcie_reset_pins: pcie-reset-pins {
groups = "pcie1";
function = "pcie";
};
pcie_clkreq_pins: pcie-clkreq-pins {
groups = "pcie1_clkreq";
function = "pcie";
};
};
eth0: ethernet@30000 {
@ -305,18 +348,50 @@ usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
reg = <0x58000 0x4000>;
marvell,usb-misc-reg = <&usb32_syscon>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sb_periph_clk 12>;
phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
phy-names = "usb3-phy", "usb2-utmi-otg-phy";
status = "disabled";
};
usb2_utmi_otg_phy: phy@5d000 {
compatible = "marvell,a3700-utmi-otg-phy";
reg = <0x5d000 0x800>;
marvell,usb-misc-reg = <&usb32_syscon>;
#phy-cells = <0>;
};
usb32_syscon: system-controller@5d800 {
compatible = "marvell,armada-3700-usb2-host-device-misc",
"syscon";
reg = <0x5d800 0x800>;
};
usb2: usb@5e000 {
compatible = "marvell,armada-3700-ehci";
reg = <0x5e000 0x2000>;
reg = <0x5e000 0x1000>;
marvell,usb-misc-reg = <&usb2_syscon>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_utmi_host_phy>;
phy-names = "usb2-utmi-host-phy";
status = "disabled";
};
usb2_utmi_host_phy: phy@5f000 {
compatible = "marvell,a3700-utmi-host-phy";
reg = <0x5f000 0x800>;
marvell,usb-misc-reg = <&usb2_syscon>;
#phy-cells = <0>;
};
usb2_syscon: system-controller@5f800 {
compatible = "marvell,armada-3700-usb2-host-misc",
"syscon";
reg = <0x5f800 0x800>;
};
xor@60900 {
compatible = "marvell,armada-3700-xor";
reg = <0x60900 0x100>,
@ -368,8 +443,9 @@ sdhci0: sdhci@d8000 {
sata: sata@e0000 {
compatible = "marvell,armada-3700-ahci";
reg = <0xe0000 0x2000>;
reg = <0xe0000 0x178>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&nb_periph_clk 1>;
status = "disabled";
};

View File

@ -66,8 +66,6 @@ &spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
@ -169,8 +167,6 @@ &cp0_spi1 {
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <20000000>;

View File

@ -81,8 +81,6 @@ &spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
@ -214,8 +212,6 @@ &cp1_spi1 {
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <20000000>;

View File

@ -283,6 +283,8 @@ ap_syscon1: system-controller@6f8000 {
ap_thermal: thermal-sensor@80 {
compatible = "marvell,armada-ap806-thermal";
reg = <0x80 0x10>;
interrupt-parent = <&sei>;
interrupts = <18>;
#thermal-sensor-cells = <1>;
};
};
@ -293,16 +295,26 @@ ap_thermal: thermal-sensor@80 {
* The thermal IP features one internal sensor plus, if applicable, one
* remote channel wired to one sensor per CPU.
*
* Only one thermal zone per AP/CP may trigger interrupts at a time, the
* first one that will have a critical trip point will be chosen.
*
* The cooling maps are always empty as there are no cooling devices.
*/
thermal-zones {
ap_thermal_ic: ap-thermal-ic {
polling-delay-passive = <1000>;
polling-delay = <1000>;
polling-delay-passive = <0>; /* Interrupt driven */
polling-delay = <0>; /* Interrupt driven */
thermal-sensors = <&ap_thermal 0>;
trips { };
trips {
ap_crit: ap-crit {
temperature = <100000>; /* mC degrees */
hysteresis = <2000>; /* mC degrees */
type = "critical";
};
};
cooling-maps { };
};

View File

@ -28,12 +28,19 @@ / {
*/
thermal-zones {
CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
polling-delay-passive = <1000>;
polling-delay = <1000>;
polling-delay-passive = <0>; /* Interrupt driven */
polling-delay = <0>; /* Interrupt driven */
thermal-sensors = <&CP110_LABEL(thermal) 0>;
trips { };
trips {
CP110_LABEL(crit): crit {
temperature = <100000>; /* mC degrees */
hysteresis = <2000>; /* mC degrees */
type = "critical";
};
};
cooling-maps { };
};
};
@ -259,6 +266,8 @@ CP110_LABEL(syscon1): system-controller@400000 {
CP110_LABEL(thermal): thermal-sensor@70 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x70 0x10>;
interrupts-extended =
<&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <1>;
};
};