clk: qcom: support for 2 bit PLL post divider
Current PLL driver only supports 4 bit PLL post divider so modified the PLL divider operations to support 2 bit PLL post divider. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -45,7 +45,7 @@
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#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
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# define PLL_POST_DIV_SHIFT 8
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# define PLL_POST_DIV_MASK 0xf
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# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
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# define PLL_ALPHA_EN BIT(24)
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# define PLL_ALPHA_MODE BIT(25)
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# define PLL_VCO_SHIFT 20
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@ -750,7 +750,7 @@ clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
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ctl >>= PLL_POST_DIV_SHIFT;
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ctl &= PLL_POST_DIV_MASK;
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ctl &= PLL_POST_DIV_MASK(pll);
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return parent_rate >> fls(ctl);
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}
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@ -764,13 +764,26 @@ static const struct clk_div_table clk_alpha_div_table[] = {
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{ }
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};
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static const struct clk_div_table clk_alpha_2bit_div_table[] = {
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{ 0x0, 1 },
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{ 0x1, 2 },
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{ 0x3, 4 },
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{ }
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};
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static long
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clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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const struct clk_div_table *table;
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return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
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if (pll->width == 2)
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table = clk_alpha_2bit_div_table;
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else
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table = clk_alpha_div_table;
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return divider_round_rate(hw, rate, prate, table,
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pll->width, CLK_DIVIDER_POWER_OF_TWO);
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}
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@ -784,7 +797,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
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return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
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PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
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PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
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div << PLL_POST_DIV_SHIFT);
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}
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