powerpc/mm: Move PTE bits from generic functions to hash64 functions.
functions which operate on pte bits are moved to hash*.h and other generic functions are moved to pgtable.h Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
371352ca0e
commit
1ca7212932
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@ -294,6 +294,189 @@ void pgtable_cache_init(void);
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extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
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pmd_t **pmdp);
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/* Generic accessors to PTE bits */
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static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);}
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static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
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static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
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static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
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static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
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static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
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static inline int pte_present(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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/* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*
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* Even if PTEs can be unsigned long long, a PFN is always an unsigned
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* long for now.
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*/
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
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{
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return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
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pgprot_val(pgprot));
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}
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static inline unsigned long pte_pfn(pte_t pte)
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{
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return pte_val(pte) >> PTE_RPN_SHIFT;
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}
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/* Generic modifiers for PTE bits */
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_RW);
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_DIRTY);
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_RW);
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_DIRTY);
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_ACCESSED);
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}
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static inline pte_t pte_mkspecial(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_SPECIAL);
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}
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static inline pte_t pte_mkhuge(pte_t pte)
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{
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return pte;
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}
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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/* This low level function performs the actual PTE insertion
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* Setting the PTE depends on the MMU type and other factors. It's
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* an horrible mess that I'm not going to try to clean up now but
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* I'm keeping it in one place rather than spread around
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*/
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static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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#if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
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/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
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* helper pte_update() which does an atomic update. We need to do that
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* because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
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* per-CPU PTE such as a kmap_atomic, we do a simple update preserving
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* the hash bits instead (ie, same as the non-SMP case)
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*/
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if (percpu)
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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else
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pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
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#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
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/* Second case is 32-bit with 64-bit PTE. In this case, we
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* can just store as long as we do the two halves in the right order
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* with a barrier in between. This is possible because we take care,
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* in the hash code, to pre-invalidate if the PTE was already hashed,
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* which synchronizes us with any concurrent invalidation.
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* In the percpu case, we also fallback to the simple update preserving
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* the hash bits
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*/
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if (percpu) {
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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return;
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}
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if (pte_val(*ptep) & _PAGE_HASHPTE)
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flush_hash_entry(mm, ptep, addr);
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__asm__ __volatile__("\
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stw%U0%X0 %2,%0\n\
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eieio\n\
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stw%U0%X0 %L2,%1"
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: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
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: "r" (pte) : "memory");
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#elif defined(CONFIG_PPC_STD_MMU_32)
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/* Third case is 32-bit hash table in UP mode, we need to preserve
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* the _PAGE_HASHPTE bit since we may not have invalidated the previous
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* translation in the hash yet (done in a subsequent flush_tlb_xxx())
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* and see we need to keep track that this PTE needs invalidating
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*/
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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#else
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#error "Not supported "
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#endif
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}
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
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_PAGE_WRITETHRU)
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#define pgprot_noncached pgprot_noncached
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static inline pgprot_t pgprot_noncached(pgprot_t prot)
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{
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return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
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_PAGE_NO_CACHE | _PAGE_GUARDED);
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}
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#define pgprot_noncached_wc pgprot_noncached_wc
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static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
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{
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return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
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_PAGE_NO_CACHE);
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}
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#define pgprot_cached pgprot_cached
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static inline pgprot_t pgprot_cached(pgprot_t prot)
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{
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return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
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_PAGE_COHERENT);
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}
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#define pgprot_cached_wthru pgprot_cached_wthru
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static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
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{
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return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
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_PAGE_COHERENT | _PAGE_WRITETHRU);
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}
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#define pgprot_cached_noncoherent pgprot_cached_noncoherent
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static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
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{
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return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
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}
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#define pgprot_writecombine pgprot_writecombine
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static inline pgprot_t pgprot_writecombine(pgprot_t prot)
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{
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return pgprot_noncached_wc(prot);
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_32_PGTABLE_H */
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@ -481,6 +481,157 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
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pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW, 0);
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}
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/* Generic accessors to PTE bits */
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static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);}
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static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
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static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
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static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
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static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
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static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
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#ifdef CONFIG_NUMA_BALANCING
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/*
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* These work without NUMA balancing but the kernel does not care. See the
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* comment in include/asm-generic/pgtable.h . On powerpc, this will only
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* work for user pages and always return true for kernel pages.
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*/
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static inline int pte_protnone(pte_t pte)
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{
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return (pte_val(pte) &
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(_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
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}
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#endif /* CONFIG_NUMA_BALANCING */
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static inline int pte_present(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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/* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*
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* Even if PTEs can be unsigned long long, a PFN is always an unsigned
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* long for now.
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*/
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
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{
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return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
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pgprot_val(pgprot));
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}
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static inline unsigned long pte_pfn(pte_t pte)
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{
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return pte_val(pte) >> PTE_RPN_SHIFT;
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}
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/* Generic modifiers for PTE bits */
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_RW);
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_DIRTY);
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_RW);
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_DIRTY);
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_ACCESSED);
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}
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static inline pte_t pte_mkspecial(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_SPECIAL);
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}
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static inline pte_t pte_mkhuge(pte_t pte)
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{
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return pte;
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}
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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/* This low level function performs the actual PTE insertion
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* Setting the PTE depends on the MMU type and other factors. It's
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* an horrible mess that I'm not going to try to clean up now but
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* I'm keeping it in one place rather than spread around
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*/
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static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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/*
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* Anything else just stores the PTE normally. That covers all 64-bit
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* cases, and 32-bit non-hash with 32-bit PTEs.
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*/
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*ptep = pte;
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}
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
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_PAGE_WRITETHRU)
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#define pgprot_noncached pgprot_noncached
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static inline pgprot_t pgprot_noncached(pgprot_t prot)
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{
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return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
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_PAGE_NO_CACHE | _PAGE_GUARDED);
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}
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#define pgprot_noncached_wc pgprot_noncached_wc
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static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
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{
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return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
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_PAGE_NO_CACHE);
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}
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#define pgprot_cached pgprot_cached
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static inline pgprot_t pgprot_cached(pgprot_t prot)
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{
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return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
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_PAGE_COHERENT);
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}
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#define pgprot_cached_wthru pgprot_cached_wthru
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static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
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{
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return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
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_PAGE_COHERENT | _PAGE_WRITETHRU);
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}
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#define pgprot_cached_noncoherent pgprot_cached_noncoherent
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static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
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{
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return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
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}
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#define pgprot_writecombine pgprot_writecombine
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static inline pgprot_t pgprot_writecombine(pgprot_t prot)
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{
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return pgprot_noncached_wc(prot);
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
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pmd_t *pmdp, unsigned long old_pmd);
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@ -201,6 +201,12 @@ static inline pte_t *pmdp_ptep(pmd_t *pmd)
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#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
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#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
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#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
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#ifdef CONFIG_NUMA_BALANCING
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static inline int pmd_protnone(pmd_t pmd)
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{
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return pte_protnone(pmd_pte(pmd));
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}
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#endif /* CONFIG_NUMA_BALANCING */
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#define __HAVE_ARCH_PMD_WRITE
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#define pmd_write(pmd) pte_write(pmd_pte(pmd))
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@ -9,221 +9,17 @@
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#define FIRST_USER_ADDRESS 0UL
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#ifndef __ASSEMBLY__
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/* Generic accessors to PTE bits */
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static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);}
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static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
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static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
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static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
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static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
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static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
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#ifdef CONFIG_NUMA_BALANCING
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/*
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* These work without NUMA balancing but the kernel does not care. See the
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* comment in include/asm-generic/pgtable.h . On powerpc, this will only
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* work for user pages and always return true for kernel pages.
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*/
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static inline int pte_protnone(pte_t pte)
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{
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return (pte_val(pte) &
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(_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
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}
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static inline int pmd_protnone(pmd_t pmd)
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{
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return pte_protnone(pmd_pte(pmd));
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}
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#endif /* CONFIG_NUMA_BALANCING */
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static inline int pte_present(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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/* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*
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* Even if PTEs can be unsigned long long, a PFN is always an unsigned
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* long for now.
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*/
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
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{
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return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
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pgprot_val(pgprot));
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}
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static inline unsigned long pte_pfn(pte_t pte)
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{
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return pte_val(pte) >> PTE_RPN_SHIFT;
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}
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/* Generic modifiers for PTE bits */
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static inline pte_t pte_wrprotect(pte_t pte)
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{
|
||||
return __pte(pte_val(pte) & ~_PAGE_RW);
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkclean(pte_t pte)
|
||||
{
|
||||
return __pte(pte_val(pte) & ~_PAGE_DIRTY);
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkold(pte_t pte)
|
||||
{
|
||||
return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkwrite(pte_t pte)
|
||||
{
|
||||
return __pte(pte_val(pte) | _PAGE_RW);
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkdirty(pte_t pte)
|
||||
{
|
||||
return __pte(pte_val(pte) | _PAGE_DIRTY);
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkyoung(pte_t pte)
|
||||
{
|
||||
return __pte(pte_val(pte) | _PAGE_ACCESSED);
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkspecial(pte_t pte)
|
||||
{
|
||||
return __pte(pte_val(pte) | _PAGE_SPECIAL);
|
||||
}
|
||||
|
||||
static inline pte_t pte_mkhuge(pte_t pte)
|
||||
{
|
||||
return pte;
|
||||
}
|
||||
|
||||
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
{
|
||||
return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
|
||||
}
|
||||
|
||||
|
||||
/* Insert a PTE, top-level function is out of line. It uses an inline
|
||||
* low level function in the respective pgtable-* files
|
||||
*/
|
||||
extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
|
||||
pte_t pte);
|
||||
|
||||
/* This low level function performs the actual PTE insertion
|
||||
* Setting the PTE depends on the MMU type and other factors. It's
|
||||
* an horrible mess that I'm not going to try to clean up now but
|
||||
* I'm keeping it in one place rather than spread around
|
||||
*/
|
||||
static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
||||
pte_t *ptep, pte_t pte, int percpu)
|
||||
{
|
||||
#if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
|
||||
/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
|
||||
* helper pte_update() which does an atomic update. We need to do that
|
||||
* because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
|
||||
* per-CPU PTE such as a kmap_atomic, we do a simple update preserving
|
||||
* the hash bits instead (ie, same as the non-SMP case)
|
||||
*/
|
||||
if (percpu)
|
||||
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
||||
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
||||
else
|
||||
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
|
||||
|
||||
#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
|
||||
/* Second case is 32-bit with 64-bit PTE. In this case, we
|
||||
* can just store as long as we do the two halves in the right order
|
||||
* with a barrier in between. This is possible because we take care,
|
||||
* in the hash code, to pre-invalidate if the PTE was already hashed,
|
||||
* which synchronizes us with any concurrent invalidation.
|
||||
* In the percpu case, we also fallback to the simple update preserving
|
||||
* the hash bits
|
||||
*/
|
||||
if (percpu) {
|
||||
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
||||
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
||||
return;
|
||||
}
|
||||
if (pte_val(*ptep) & _PAGE_HASHPTE)
|
||||
flush_hash_entry(mm, ptep, addr);
|
||||
__asm__ __volatile__("\
|
||||
stw%U0%X0 %2,%0\n\
|
||||
eieio\n\
|
||||
stw%U0%X0 %L2,%1"
|
||||
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
||||
: "r" (pte) : "memory");
|
||||
|
||||
#elif defined(CONFIG_PPC_STD_MMU_32)
|
||||
/* Third case is 32-bit hash table in UP mode, we need to preserve
|
||||
* the _PAGE_HASHPTE bit since we may not have invalidated the previous
|
||||
* translation in the hash yet (done in a subsequent flush_tlb_xxx())
|
||||
* and see we need to keep track that this PTE needs invalidating
|
||||
*/
|
||||
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
||||
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
||||
|
||||
#else
|
||||
/* Anything else just stores the PTE normally. That covers all 64-bit
|
||||
* cases, and 32-bit non-hash with 32-bit PTEs.
|
||||
*/
|
||||
*ptep = pte;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
||||
extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
|
||||
pte_t *ptep, pte_t entry, int dirty);
|
||||
|
||||
/*
|
||||
* Macro to mark a page protection value as "uncacheable".
|
||||
*/
|
||||
|
||||
#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
|
||||
_PAGE_WRITETHRU)
|
||||
|
||||
#define pgprot_noncached pgprot_noncached
|
||||
static inline pgprot_t pgprot_noncached(pgprot_t prot)
|
||||
{
|
||||
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
||||
_PAGE_NO_CACHE | _PAGE_GUARDED);
|
||||
}
|
||||
|
||||
#define pgprot_noncached_wc pgprot_noncached_wc
|
||||
static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
|
||||
{
|
||||
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
||||
_PAGE_NO_CACHE);
|
||||
}
|
||||
|
||||
#define pgprot_cached pgprot_cached
|
||||
static inline pgprot_t pgprot_cached(pgprot_t prot)
|
||||
{
|
||||
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
||||
_PAGE_COHERENT);
|
||||
}
|
||||
|
||||
#define pgprot_cached_wthru pgprot_cached_wthru
|
||||
static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
|
||||
{
|
||||
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
||||
_PAGE_COHERENT | _PAGE_WRITETHRU);
|
||||
}
|
||||
|
||||
#define pgprot_cached_noncoherent pgprot_cached_noncoherent
|
||||
static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
|
||||
{
|
||||
return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
|
||||
}
|
||||
|
||||
#define pgprot_writecombine pgprot_writecombine
|
||||
static inline pgprot_t pgprot_writecombine(pgprot_t prot)
|
||||
{
|
||||
return pgprot_noncached_wc(prot);
|
||||
}
|
||||
|
||||
struct file;
|
||||
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
||||
unsigned long size, pgprot_t vma_prot);
|
||||
|
|
|
|||
Loading…
Reference in New Issue