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arm64: dts: rockchip: add mipi_dsi1 support for rk3399 

This patch adds the information for the secondary MIPI DSI controller,
e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing
definition for dsi0.

Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Nickey Yang 2017-11-29 17:11:27 -08:00 committed by Heiko Stuebner
parent 3813a10a5a
commit 1df5d2ab16
1 changed files with 45 additions and 0 deletions
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45
arch/arm64/boot/dts/rockchip/rk3399.dtsi
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@ -1526,6 +1526,11 @@ vopl_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopl>;
};
vopl_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopl>;
};
};
};
@ -1573,6 +1578,11 @@ vopb_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_mipi1: endpoint@3 {
reg = <3>;
remote-endpoint = <&mipi1_in_vopb>;
};
};
};
@ -1670,6 +1680,41 @@ mipi_in_vopl: endpoint@1 {
};
};
mipi_dsi1: mipi@ff968000 {
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff968000 0x0 0x8000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
clock-names = "ref", "pclk", "phy_cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
resets = <&cru SRST_P_MIPI_DSI1>;
reset-names = "apb";
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
mipi1_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi1>;
};
mipi1_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi1>;
};
};
};
};
edp: edp@ff970000 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff970000 0x0 0x8000>;