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Merge branch 'lpc32xx/soc' of https://github.com/vzapolskiy/linux into next/cleanup 

From Vladimir Zapolskiy:

"The main change is a switchover to a common clock framework driver for
LPC32xx, this also allows to reuse a shared LPC32xx clockevent driver, and
hence remove legacy clock and timer drivers from arch/arm/mach-lpc32xx.

I'm adding an official LPC32xx maintainer Roland to Cc, however he seems
to be unresponsive for a quite long time (since 2014)."

* 'lpc32xx/soc' of https://github.com/vzapolskiy/linux:
  arm: lpc32xx: remove direct control of GPIOs from shared mach file
  arm: lpc32xx: remove selected HAVE_IDE
  arm: lpc32xx: switch to common clock framework

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-02-24 12:21:24 -08:00
parent 915c7ce8ad 0ac1a101f5
commit 1e4ee8791f
6 changed files with 3 additions and 1488 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/Kconfig
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@ -527,10 +527,10 @@ config ARCH_LPC32XX
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_LPC32XX
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_IDE
select USE_OF
help
Support for the NXP LPC32XX family of processors

3
arch/arm/mach-lpc32xx/Makefile
View File

@ -2,7 +2,6 @@
# Makefile for the linux kernel.
#
obj-y := timer.o irq.o common.o serial.o clock.o
obj-y := irq.o common.o serial.o
obj-y += pm.o suspend.o
obj-y += phy3250.o

1284
arch/arm/mach-lpc32xx/clock.c
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File diff suppressed because it is too large Load Diff

53
arch/arm/mach-lpc32xx/phy3250.c
View File

@ -36,7 +36,6 @@
#include <linux/clk.h>
#include <linux/mtd/lpc32xx_slc.h>
#include <linux/mtd/lpc32xx_mlc.h>
#include <linux/platform_data/gpio-lpc32xx.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
@ -47,13 +46,6 @@
#include <mach/board.h>
#include "common.h"
/*
* Mapped GPIOLIB GPIOs
*/
#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
/*
* AMBA LCD controller
*/
@ -97,20 +89,6 @@ static int lpc32xx_clcd_setup(struct clcd_fb *fb)
fb->fb.fix.smem_len = PANEL_SIZE;
fb->panel = &conn_lcd_panel;
if (gpio_request(LCD_POWER_GPIO, "LCD power"))
printk(KERN_ERR "Error requesting gpio %u",
LCD_POWER_GPIO);
else if (gpio_direction_output(LCD_POWER_GPIO, 1))
printk(KERN_ERR "Error setting gpio %u to output",
LCD_POWER_GPIO);
if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
printk(KERN_ERR "Error requesting gpio %u",
BKL_POWER_GPIO);
else if (gpio_direction_output(BKL_POWER_GPIO, 1))
printk(KERN_ERR "Error setting gpio %u to output",
BKL_POWER_GPIO);
return 0;
}
@ -127,29 +105,10 @@ static void lpc32xx_clcd_remove(struct clcd_fb *fb)
fb->fb.screen_base, fb->fb.fix.smem_start);
}
/*
* On some early LCD modules (1307.0), the backlight logic is inverted.
* For those board variants, swap the disable and enable states for
* BKL_POWER_GPIO.
*/
static void clcd_disable(struct clcd_fb *fb)
{
gpio_set_value(BKL_POWER_GPIO, 0);
gpio_set_value(LCD_POWER_GPIO, 0);
}
static void clcd_enable(struct clcd_fb *fb)
{
gpio_set_value(BKL_POWER_GPIO, 1);
gpio_set_value(LCD_POWER_GPIO, 1);
}
static struct clcd_board lpc32xx_clcd_data = {
.name = "Phytec LCD",
.check = clcdfb_check,
.decode = clcdfb_decode,
.disable = clcd_disable,
.enable = clcd_enable,
.setup = lpc32xx_clcd_setup,
.mmap = lpc32xx_clcd_mmap,
.remove = lpc32xx_clcd_remove,
@ -188,20 +147,9 @@ static struct pl08x_platform_data pl08x_pd = {
.mem_buses = PL08X_AHB1,
};
static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
{
/* Only on and off are supported */
if (ios->power_mode == MMC_POWER_OFF)
gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
else
gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
return 0;
}
static struct mmci_platform_data lpc32xx_mmci_data = {
.ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
MMC_VDD_32_33 | MMC_VDD_33_34,
.ios_handler = mmc_handle_ios,
};
static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
@ -260,7 +208,6 @@ DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
.atag_offset = 0x100,
.map_io = lpc32xx_map_io,
.init_irq = lpc32xx_init_irq,
.init_time = lpc32xx_timer_init,
.init_machine = lpc3250_machine_init,
.dt_compat = lpc32xx_dt_compat,
.restart = lpc23xx_restart,

3
arch/arm/mach-lpc32xx/serial.c
View File

@ -76,9 +76,6 @@ void __init lpc32xx_serial_init(void)
unsigned int puart;
int i, j;
/* UART clocks are off, let clock driver manage them */
__raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
if (!IS_ERR(clk)) {

144
arch/arm/mach-lpc32xx/timer.c
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@ -1,144 +0,0 @@
/*
* arch/arm/mach-lpc32xx/timer.c
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2009 - 2010 NXP Semiconductors
* Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
* Ed Schouten <e.schouten@fontys.nl>
* Laurens Timmermans <l.timmermans@fontys.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/err.h>
#include <linux/clockchips.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include "common.h"
static int lpc32xx_clkevt_next_event(unsigned long delta,
struct clock_event_device *dev)
{
__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
return 0;
}
static int lpc32xx_shutdown(struct clock_event_device *evt)
{
/*
* Disable the timer. When using oneshot, we must also
* disable the timer to wait for the first call to
* set_next_event().
*/
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
return 0;
}
static struct clock_event_device lpc32xx_clkevt = {
.name = "lpc32xx_clkevt",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_next_event = lpc32xx_clkevt_next_event,
.set_state_shutdown = lpc32xx_shutdown,
.set_state_oneshot = lpc32xx_shutdown,
};
static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &lpc32xx_clkevt;
/* Clear match */
__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction lpc32xx_timer_irq = {
.name = "LPC32XX Timer Tick",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = lpc32xx_timer_interrupt,
};
/*
* The clock management driver isn't initialized at this point, so the
* clocks need to be enabled here manually and then tagged as used in
* the clock driver initialization
*/
void __init lpc32xx_timer_init(void)
{
u32 clkrate, pllreg;
/* Enable timer clock */
__raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
/*
* The clock driver isn't initialized at this point. So determine if
* the SYSCLK is driven from the PLL397 or main oscillator and then use
* it to compute the PLL frequency and the PCLK divider to get the base
* timer rates. This rate is needed to compute the tick rate.
*/
if (clk_is_sysclk_mainosc() != 0)
clkrate = LPC32XX_MAIN_OSC_FREQ;
else
clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
/* Get ARM HCLKPLL register and convert it into a frequency */
pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
/* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
clkrate = clkrate / clk_get_pclk_div();
/* Initial timer setup */
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
LPC32XX_TIMER_CNTR_MCR_STOP(0) |
LPC32XX_TIMER_CNTR_MCR_RESET(0),
LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
/* Setup tick interrupt */
setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
/* Setup the clockevent structure. */
lpc32xx_clkevt.cpumask = cpumask_of(0);
clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
/* Use timer1 as clock source. */
__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
}