clk: davinci: New driver for TI DA8XX CFGCHIP clocks
This adds a new driver for the gate and multiplexer clocks in the CFGCHIPn syscon registers on TI DA8XX-type SoCs. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
David Lechner
Stephen Boyd
parent
0c92c71770
commit
1e88a8d64f
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@ -1,6 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0
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ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o
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obj-y += pll.o
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obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
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obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
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@ -0,0 +1,439 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/mfd/da8xx-cfgchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/platform_data/clk-da8xx-cfgchip.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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/* --- Gate clocks --- */
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#define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1)
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struct da8xx_cfgchip_gate_clk_info {
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const char *name;
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u32 cfgchip;
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u32 bit;
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u32 flags;
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};
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struct da8xx_cfgchip_gate_clk {
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struct clk_hw hw;
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struct regmap *regmap;
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u32 reg;
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u32 mask;
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};
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#define to_da8xx_cfgchip_gate_clk(_hw) \
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container_of((_hw), struct da8xx_cfgchip_gate_clk, hw)
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static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw)
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{
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struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
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return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask);
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}
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static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw)
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{
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struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
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regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0);
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}
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static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw)
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{
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struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
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unsigned int val;
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regmap_read(clk->regmap, clk->reg, &val);
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return !!(val & clk->mask);
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}
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static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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/* this clock divides by 4.5 */
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return parent_rate * 2 / 9;
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}
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static const struct clk_ops da8xx_cfgchip_gate_clk_ops = {
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.enable = da8xx_cfgchip_gate_clk_enable,
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.disable = da8xx_cfgchip_gate_clk_disable,
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.is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
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};
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static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = {
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.enable = da8xx_cfgchip_gate_clk_enable,
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.disable = da8xx_cfgchip_gate_clk_disable,
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.is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
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.recalc_rate = da8xx_cfgchip_div4p5_recalc_rate,
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};
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static struct da8xx_cfgchip_gate_clk * __init
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da8xx_cfgchip_gate_clk_register(struct device *dev,
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const struct da8xx_cfgchip_gate_clk_info *info,
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struct regmap *regmap)
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{
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struct clk *parent;
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const char *parent_name;
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struct da8xx_cfgchip_gate_clk *gate;
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struct clk_init_data init;
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int ret;
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parent = devm_clk_get(dev, NULL);
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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parent_name = __clk_get_name(parent);
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gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = info->name;
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if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5)
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init.ops = &da8xx_cfgchip_div4p5_clk_ops;
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else
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init.ops = &da8xx_cfgchip_gate_clk_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = 0;
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gate->hw.init = &init;
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gate->regmap = regmap;
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gate->reg = info->cfgchip;
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gate->mask = info->bit;
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ret = devm_clk_hw_register(dev, &gate->hw);
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if (ret < 0)
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return ERR_PTR(ret);
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return gate;
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}
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static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = {
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.name = "ehrpwm_tbclk",
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.cfgchip = CFGCHIP(1),
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.bit = CFGCHIP1_TBCLKSYNC,
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};
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static int __init da8xx_cfgchip_register_tbclk(struct device *dev,
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struct regmap *regmap)
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{
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struct da8xx_cfgchip_gate_clk *gate;
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gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info,
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regmap);
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if (IS_ERR(gate))
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return PTR_ERR(gate);
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clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0");
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clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1");
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return 0;
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}
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static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = {
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.name = "div4.5",
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.cfgchip = CFGCHIP(3),
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.bit = CFGCHIP3_DIV45PENA,
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.flags = DA8XX_GATE_CLOCK_IS_DIV4P5,
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};
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static int __init da8xx_cfgchip_register_div4p5(struct device *dev,
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struct regmap *regmap)
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{
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struct da8xx_cfgchip_gate_clk *gate;
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gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap);
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if (IS_ERR(gate))
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return PTR_ERR(gate);
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return 0;
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}
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static int __init
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of_da8xx_cfgchip_gate_clk_init(struct device *dev,
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const struct da8xx_cfgchip_gate_clk_info *info,
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struct regmap *regmap)
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{
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struct da8xx_cfgchip_gate_clk *gate;
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gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap);
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if (IS_ERR(gate))
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return PTR_ERR(gate);
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate);
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}
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static int __init of_da8xx_tbclksync_init(struct device *dev,
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struct regmap *regmap)
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{
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return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap);
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}
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static int __init of_da8xx_div4p5ena_init(struct device *dev,
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struct regmap *regmap)
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{
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return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap);
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}
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/* --- MUX clocks --- */
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struct da8xx_cfgchip_mux_clk_info {
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const char *name;
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const char *parent0;
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const char *parent1;
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u32 cfgchip;
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u32 bit;
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};
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struct da8xx_cfgchip_mux_clk {
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struct clk_hw hw;
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struct regmap *regmap;
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u32 reg;
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u32 mask;
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};
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#define to_da8xx_cfgchip_mux_clk(_hw) \
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container_of((_hw), struct da8xx_cfgchip_mux_clk, hw)
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static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
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unsigned int val = index ? clk->mask : 0;
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return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val);
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}
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static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw)
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{
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struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
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unsigned int val;
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regmap_read(clk->regmap, clk->reg, &val);
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return (val & clk->mask) ? 1 : 0;
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}
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static const struct clk_ops da8xx_cfgchip_mux_clk_ops = {
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.set_parent = da8xx_cfgchip_mux_clk_set_parent,
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.get_parent = da8xx_cfgchip_mux_clk_get_parent,
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};
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static struct da8xx_cfgchip_mux_clk * __init
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da8xx_cfgchip_mux_clk_register(struct device *dev,
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const struct da8xx_cfgchip_mux_clk_info *info,
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struct regmap *regmap)
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{
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const char * const parent_names[] = { info->parent0, info->parent1 };
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struct da8xx_cfgchip_mux_clk *mux;
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struct clk_init_data init;
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int ret;
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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init.name = info->name;
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init.ops = &da8xx_cfgchip_mux_clk_ops;
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init.parent_names = parent_names;
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init.num_parents = 2;
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init.flags = 0;
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mux->hw.init = &init;
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mux->regmap = regmap;
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mux->reg = info->cfgchip;
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mux->mask = info->bit;
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ret = devm_clk_hw_register(dev, &mux->hw);
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if (ret < 0)
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return ERR_PTR(ret);
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return mux;
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}
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static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = {
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.name = "async1",
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.parent0 = "pll0_sysclk3",
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.parent1 = "div4.5",
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.cfgchip = CFGCHIP(3),
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.bit = CFGCHIP3_EMA_CLKSRC,
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};
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static int __init da8xx_cfgchip_register_async1(struct device *dev,
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struct regmap *regmap)
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{
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struct da8xx_cfgchip_mux_clk *mux;
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mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap);
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if (IS_ERR(mux))
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return PTR_ERR(mux);
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clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0");
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return 0;
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}
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static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = {
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.name = "async3",
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.parent0 = "pll0_sysclk2",
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.parent1 = "pll1_sysclk2",
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.cfgchip = CFGCHIP(3),
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.bit = CFGCHIP3_ASYNC3_CLKSRC,
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};
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static int __init da850_cfgchip_register_async3(struct device *dev,
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struct regmap *regmap)
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{
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struct da8xx_cfgchip_mux_clk *mux;
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struct clk_hw *parent;
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mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap);
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if (IS_ERR(mux))
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return PTR_ERR(mux);
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clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1");
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/* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */
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parent = clk_hw_get_parent_by_index(&mux->hw, 1);
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if (parent)
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clk_set_parent(mux->hw.clk, parent->clk);
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else
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dev_warn(dev, "Failed to find async3 parent clock\n");
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return 0;
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}
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static int __init
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of_da8xx_cfgchip_init_mux_clock(struct device *dev,
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const struct da8xx_cfgchip_mux_clk_info *info,
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struct regmap *regmap)
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{
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struct da8xx_cfgchip_mux_clk *mux;
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mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap);
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if (IS_ERR(mux))
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return PTR_ERR(mux);
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw);
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}
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static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap)
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{
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return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap);
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}
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static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap)
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{
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return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap);
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}
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/* --- platform device --- */
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static const struct of_device_id da8xx_cfgchip_of_match[] = {
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{
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.compatible = "ti,da830-tbclksync",
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.data = of_da8xx_tbclksync_init,
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},
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{
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.compatible = "ti,da830-div4p5ena",
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.data = of_da8xx_div4p5ena_init,
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},
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{
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.compatible = "ti,da850-async1-clksrc",
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.data = of_da850_async1_init,
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},
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{
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.compatible = "ti,da850-async3-clksrc",
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.data = of_da850_async3_init,
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},
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{ }
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};
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static const struct platform_device_id da8xx_cfgchip_id_table[] = {
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{
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.name = "da830-tbclksync",
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.driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk,
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},
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{
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.name = "da830-div4p5ena",
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.driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5,
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},
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{
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.name = "da850-async1-clksrc",
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.driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1,
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},
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{
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.name = "da850-async3-clksrc",
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.driver_data = (kernel_ulong_t)da850_cfgchip_register_async3,
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},
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{ }
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};
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typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap);
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static int da8xx_cfgchip_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data;
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const struct of_device_id *of_id;
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da8xx_cfgchip_init clk_init = NULL;
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struct regmap *regmap = NULL;
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of_id = of_match_device(da8xx_cfgchip_of_match, dev);
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if (of_id) {
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struct device_node *parent;
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clk_init = of_id->data;
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parent = of_get_parent(dev->of_node);
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regmap = syscon_node_to_regmap(parent);
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of_node_put(parent);
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} else if (pdev->id_entry && pdata) {
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clk_init = (void *)pdev->id_entry->driver_data;
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regmap = pdata->cfgchip;
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}
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if (!clk_init) {
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dev_err(dev, "unable to find driver data\n");
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return -EINVAL;
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}
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if (IS_ERR_OR_NULL(regmap)) {
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dev_err(dev, "no regmap for CFGCHIP syscon\n");
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return regmap ? PTR_ERR(regmap) : -ENOENT;
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}
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return clk_init(dev, regmap);
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}
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static struct platform_driver da8xx_cfgchip_driver = {
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.probe = da8xx_cfgchip_probe,
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.driver = {
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.name = "da8xx-cfgchip-clk",
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.of_match_table = da8xx_cfgchip_of_match,
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},
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.id_table = da8xx_cfgchip_id_table,
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};
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static int __init da8xx_cfgchip_driver_init(void)
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{
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return platform_driver_register(&da8xx_cfgchip_driver);
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}
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/* has to be postcore_initcall because PSC devices depend on the async3 clock */
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postcore_initcall(da8xx_cfgchip_driver_init);
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@ -0,0 +1,21 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* clk-da8xx-cfgchip - TI DaVinci DA8xx CFGCHIP clock driver
|
||||
*
|
||||
* Copyright (C) 2018 David Lechner <david@lechnology.com>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__
|
||||
#define __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__
|
||||
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/**
|
||||
* da8xx_cfgchip_clk_platform_data
|
||||
* @cfgchip: CFGCHIP syscon regmap
|
||||
*/
|
||||
struct da8xx_cfgchip_clk_platform_data {
|
||||
struct regmap *cfgchip;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ */
|
||||
Loading…
Reference in New Issue