net/mlx5: Add FPGA QP error event
The FPGA queue pair (QP) event fires whenever a QP on the FPGA transitions to the error state. At this stage, this event is unrecoverable, it may become recoverable in the future. Signed-off-by: Ilan Tayari <ilant@mellanox.com> Signed-off-by: Adi Nissim <adin@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -164,6 +164,8 @@ static const char *eqe_type_str(u8 type)
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return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
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case MLX5_EVENT_TYPE_FPGA_ERROR:
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return "MLX5_EVENT_TYPE_FPGA_ERROR";
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case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
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return "MLX5_EVENT_TYPE_FPGA_QP_ERROR";
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case MLX5_EVENT_TYPE_GENERAL_EVENT:
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return "MLX5_EVENT_TYPE_GENERAL_EVENT";
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default:
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@ -563,6 +565,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
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break;
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case MLX5_EVENT_TYPE_FPGA_ERROR:
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case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
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mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
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break;
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@ -842,11 +845,11 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
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async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
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if (MLX5_CAP_GEN(dev, fpga))
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async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);
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async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |
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(1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);
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if (MLX5_CAP_GEN_MAX(dev, dct))
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async_event_mask |= (1ull << MLX5_EVENT_TYPE_DCT_DRAINED);
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if (MLX5_CAP_GEN(dev, temp_warn_event))
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async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
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@ -331,6 +331,7 @@ enum mlx5_event {
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MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
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MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
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MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
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};
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enum {
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@ -60,6 +60,7 @@ enum {
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MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
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MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
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MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
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MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
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};
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enum {
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@ -470,6 +470,22 @@ struct mlx5_ifc_ipsec_counters_bits {
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u8 dropped_cmd[0x40];
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};
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enum {
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MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1,
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MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2,
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};
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struct mlx5_ifc_fpga_qp_error_event_bits {
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u8 reserved_at_0[0x40];
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u8 reserved_at_40[0x18];
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u8 syndrome[0x8];
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u8 reserved_at_60[0x60];
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u8 reserved_at_c0[0x8];
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u8 fpga_qpn[0x18];
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};
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enum mlx5_ifc_fpga_ipsec_response_syndrome {
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MLX5_FPGA_IPSEC_RESPONSE_SUCCESS = 0,
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MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1,
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