drm/i915/gen8: Flip the 48b switch
Use 48b addresses if hw supports it (i915.enable_ppgtt=3). Update the sanitize_enable_ppgtt for 48 bit PPGTT mode. Note, aliasing PPGTT remains 32b only. v2: s/full_64b/full_48b/. (Akash) v3: Add sanitize_enable_ppgtt changes until here. (Akash) v4: Update param description (Chris) Cc: Akash Goel <akash.goel@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -104,9 +104,11 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
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{
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bool has_aliasing_ppgtt;
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bool has_full_ppgtt;
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bool has_full_48bit_ppgtt;
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has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
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has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
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has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
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if (intel_vgpu_active(dev))
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has_full_ppgtt = false; /* emulation is too hard */
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@ -125,6 +127,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
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if (enable_ppgtt == 2 && has_full_ppgtt)
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return 2;
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if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
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return 3;
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#ifdef CONFIG_INTEL_IOMMU
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/* Disable ppgtt on SNB if VT-d is on. */
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if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
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@ -141,7 +146,7 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
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}
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if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
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return 2;
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return has_full_48bit_ppgtt ? 3 : 2;
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else
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return has_aliasing_ppgtt ? 1 : 0;
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}
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@ -111,7 +111,7 @@ MODULE_PARM_DESC(enable_hangcheck,
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module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);
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MODULE_PARM_DESC(enable_ppgtt,
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"Override PPGTT usage. "
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"(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");
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"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
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module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);
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MODULE_PARM_DESC(enable_execlists,
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