drm/meson: Convert existing documentation to actual kerneldoc
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Neil Armstrong
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2021d5b7d9
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@ -24,7 +24,9 @@
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#include "meson_canvas.h"
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#include "meson_registers.h"
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/*
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/**
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* DOC: Canvas
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*
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* CANVAS is a memory zone where physical memory frames information
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* are stored for the VIU to scanout.
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*/
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@ -52,13 +52,14 @@
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#define DRIVER_NAME "meson"
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#define DRIVER_DESC "Amlogic Meson DRM driver"
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/*
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* Video Processing Unit
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/**
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* DOC: Video Processing Unit
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*
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* VPU Handles the Global Video Processing, it includes management of the
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* clocks gates, blocks reset lines and power domains.
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*
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* What is missing :
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*
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* - Full reset of entire video processing HW blocks
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* - Scaling and setup of the VPU clock
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* - Bus clock gates
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@ -42,11 +42,17 @@
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#define DRIVER_NAME "meson-dw-hdmi"
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#define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
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/*
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/**
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* DOC: HDMI Output
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*
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* HDMI Output is composed of :
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*
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* - A Synopsys DesignWare HDMI Controller IP
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* - A TOP control block controlling the Clocks and PHY
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* - A custom HDMI PHY in order convert video to TMDS signal
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*
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* .. code::
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*
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* ___________________________________
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* | HDMI TOP |<= HPD
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* |___________________________________|
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@ -55,6 +61,7 @@
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* | Controller |________________|
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* |___________________________________|<=> DDC
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*
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*
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* The HDMI TOP block only supports HPD sensing.
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* The Synopsys HDMI Controller interrupt is routed
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* through the TOP Block interrupt.
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@ -78,6 +85,7 @@
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* audio source interfaces.
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*
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* We handle the following features :
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*
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* - HPD Rise & Fall interrupt
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* - HDMI Controller Interrupt
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* - HDMI PHY Init for 480i to 1080p60
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@ -85,6 +93,7 @@
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* - VENC Mode setup for 480i to 1080p60
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*
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* What is missing :
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*
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* - PHY, Clock and Mode setup for 2k && 4k modes
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* - SDDC Scrambling mode for HDMI 2.0a
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* - HDCP Setup
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@ -23,15 +23,23 @@
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#include "meson_drv.h"
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#include "meson_vclk.h"
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/*
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/**
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* DOC: Video Clocks
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*
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* VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
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* We handle the following encodings :
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*
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* - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
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* - HDMI Pixel Clocks generation
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*
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* What is missing :
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*
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* - Genenate Pixel clocks for 2K/4K 10bit formats
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*
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* Clock generator scheme :
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*
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* .. code::
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*
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* __________ _________ _____
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* | | | | | |--ENCI
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* | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
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@ -26,23 +26,30 @@
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#include "meson_vclk.h"
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#include "meson_registers.h"
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/*
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/**
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* DOC: Video Encoder
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*
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* VENC Handle the pixels encoding to the output formats.
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* We handle the following encodings :
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*
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* - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
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* - TMDS/HDMI Encoding via ENCI_DIV and ENCP
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* - Setup of more clock rates for HDMI modes
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*
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* What is missing :
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*
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* - LCD Panel encoding via ENCL
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* - TV Panel encoding via ENCT
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*
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* VENC paths :
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*
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* .. code::
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*
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* _____ _____ ____________________
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* vd1---| |-| | | VENC /---------|----VDAC
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* vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|\
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* vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
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* osd1--| |-| | | \ | X--HDMI-TX
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* osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|/
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* osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
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* | | |
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* | \--ENCL-----------|----LVDS
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* |____________________|
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@ -28,9 +28,12 @@
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#include "meson_canvas.h"
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#include "meson_registers.h"
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/*
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/**
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* DOC: Video Input Unit
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*
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* VIU Handles the Pixel scanout and the basic Colorspace conversions
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* We handle the following features :
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*
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* - OSD1 RGB565/RGB888/xRGB8888 scanout
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* - RGB conversion to x/cb/cr
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* - Progressive or Interlace buffer scanout
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@ -38,6 +41,7 @@
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* - HDR OSD matrix for GXL/GXM
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*
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* What is missing :
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*
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* - BGR888/xBGR8888/BGRx8888/BGRx8888 modes
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* - YUV4:2:2 Y0CbY1Cr scanout
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* - Conversion to YUV 4:4:4 from 4:2:2 input
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@ -25,16 +25,20 @@
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#include "meson_vpp.h"
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#include "meson_registers.h"
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/*
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/**
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* DOC: Video Post Processing
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*
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* VPP Handles all the Post Processing after the Scanout from the VIU
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* We handle the following post processings :
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* - Postblend : Blends the OSD1 only
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*
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* - Postblend, Blends the OSD1 only
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* We exclude OSD2, VS1, VS1 and Preblend output
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* - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
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* use it only for interlace scanout
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* - Intermediate FIFO with default Amlogic values
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*
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* What is missing :
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*
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* - Preblend for video overlay pre-scaling
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* - OSD2 support for cursor framebuffer
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* - Video pre-scaling before postblend
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