ARM: STi: DT: STiH415: 415 DT Entry for clockgen A9
Patch adds DT entries for clockgen A9 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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@ -23,15 +23,6 @@ clk_sysin: clk-sysin {
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clock-frequency = <30000000>;
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: arm_periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <500000000>;
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};
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/*
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* ClockGenAs on SASG1
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*/
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@ -499,5 +490,44 @@ clk_m_a2_div3: clk-m-a2-div3 {
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/* Remaining outputs unused */
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};
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};
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/*
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* A9 PLL
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*/
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clockgen-a9@fdde00d8 {
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reg = <0xfdde00d8 0x70>;
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clockgen_a9_pll: clockgen-a9-pll {
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#clock-cells = <1>;
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compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clockgen-a9-pll-odf";
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};
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};
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/*
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* ARM CPU related clocks
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*/
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clk_m_a9: clk-m-a9@fdde00d8 {
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#clock-cells = <0>;
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compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux";
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reg = <0xfdde00d8 0x4>;
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clocks = <&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_m_a0_div1 2>,
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<&clk_m_a9_ext2f_div2>;
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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