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drm/amdgpu/si: fix ring size for compute 

We switched the other asics, but missed this.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2016-09-15 12:04:45 -04:00
parent 72f417a2e0
commit 2255e8c109
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
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@ -2779,7 +2779,7 @@ static int gfx_v6_0_sw_init(void *handle)
ring->queue = i;
sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
r = amdgpu_ring_init(adev, ring, 1024 * 1024,
r = amdgpu_ring_init(adev, ring, 1024,
0x80000000, 0xf,
&adev->gfx.eop_irq, irq_type,
AMDGPU_RING_TYPE_COMPUTE);