arm64: dts: ls2080a: Add TMU device tree support for LS2080A
Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Hongtao Jia
Shawn Guo
parent
18486552b7
commit
236f794e44
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@ -46,7 +46,7 @@
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/dts-v1/;
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/include/ "fsl-ls2080a.dtsi"
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#include "fsl-ls2080a.dtsi"
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/ {
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model = "Freescale Layerscape 2080a QDS Board";
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@ -46,7 +46,7 @@
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/dts-v1/;
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/include/ "fsl-ls2080a.dtsi"
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#include "fsl-ls2080a.dtsi"
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/ {
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model = "Freescale Layerscape 2080a RDB Board";
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@ -46,7 +46,7 @@
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/dts-v1/;
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/include/ "fsl-ls2080a.dtsi"
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#include "fsl-ls2080a.dtsi"
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/ {
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model = "Freescale Layerscape 2080a software Simulator model";
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@ -44,6 +44,8 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "fsl,ls2080a";
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interrupt-parent = <&gic>;
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@ -62,15 +64,16 @@ cpus {
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*/
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/* We have 4 clusters having 2 Cortex-A57 cores each */
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cpu@0 {
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&cluster0_l2>;
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#cooling-cells = <2>;
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};
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cpu@1 {
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1>;
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@ -78,15 +81,16 @@ cpu@1 {
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next-level-cache = <&cluster0_l2>;
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};
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cpu@100 {
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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clocks = <&clockgen 1 1>;
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next-level-cache = <&cluster1_l2>;
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#cooling-cells = <2>;
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};
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cpu@101 {
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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@ -94,15 +98,16 @@ cpu@101 {
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next-level-cache = <&cluster1_l2>;
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};
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cpu@200 {
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cpu4: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x200>;
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clocks = <&clockgen 1 2>;
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next-level-cache = <&cluster2_l2>;
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#cooling-cells = <2>;
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};
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cpu@201 {
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cpu5: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x201>;
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@ -110,15 +115,16 @@ cpu@201 {
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next-level-cache = <&cluster2_l2>;
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};
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cpu@300 {
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cpu6: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x300>;
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clocks = <&clockgen 1 3>;
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next-level-cache = <&cluster3_l2>;
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#cooling-cells = <2>;
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};
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cpu@301 {
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cpu7: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x301>;
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@ -215,6 +221,100 @@ clockgen: clocking@1300000 {
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clocks = <&sysclk>;
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};
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tmu: tmu@1f80000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f80000 0x0 0x10000>;
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interrupts = <0 23 0x4>;
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fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
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fsl,tmu-calibration = <0x00000000 0x00000026
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0x00000001 0x0000002d
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0x00000002 0x00000032
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0x00000003 0x00000039
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0x00000004 0x0000003f
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0x00000005 0x00000046
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0x00000006 0x0000004d
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0x00000007 0x00000054
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0x00000008 0x0000005a
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0x00000009 0x00000061
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0x0000000a 0x0000006a
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0x0000000b 0x00000071
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0x00010000 0x00000025
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0x00010001 0x0000002c
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0x00010002 0x00000035
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0x00010003 0x0000003d
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0x00010004 0x00000045
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0x00010005 0x0000004e
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0x00010006 0x00000057
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0x00010007 0x00000061
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0x00010008 0x0000006b
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0x00010009 0x00000076
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0x00020000 0x00000029
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0x00020001 0x00000033
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0x00020002 0x0000003d
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0x00020003 0x00000049
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0x00020004 0x00000056
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0x00020005 0x00000061
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0x00020006 0x0000006d
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0x00030000 0x00000021
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0x00030001 0x0000002a
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0x00030002 0x0000003c
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0x00030003 0x0000004e>;
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little-endian;
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#thermal-sensor-cells = <1>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 4>;
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trips {
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cpu_alert: cpu-alert {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&cpu_alert>;
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cooling-device =
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<&cpu2 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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map2 {
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trip = <&cpu_alert>;
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cooling-device =
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<&cpu4 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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map3 {
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trip = <&cpu_alert>;
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cooling-device =
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<&cpu6 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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serial0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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