MIPS: Loongson-3: Adjust irq dispatch to speedup processing
This patch adjust the logic in mach_irq_dispatch(), allow multiple IPs handled in the same dispatching. This can speedup interrupt processing. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -24,19 +24,21 @@ static void ht_irqdispatch(void)
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}
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}
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#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
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void mach_irq_dispatch(unsigned int pending)
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{
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if (pending & CAUSEF_IP7)
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do_IRQ(LOONGSON_TIMER_IRQ);
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#if defined(CONFIG_SMP)
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else if (pending & CAUSEF_IP6)
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if (pending & CAUSEF_IP6)
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loongson3_ipi_interrupt(NULL);
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#endif
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else if (pending & CAUSEF_IP3)
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if (pending & CAUSEF_IP3)
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ht_irqdispatch();
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else if (pending & CAUSEF_IP2)
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if (pending & CAUSEF_IP2)
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do_IRQ(LOONGSON_UART_IRQ);
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else {
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if (pending & UNUSED_IPS) {
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pr_err("%s : spurious interrupt\n", __func__);
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spurious_interrupt();
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}
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