ARM: OMAP5: hwmod: add missing ocp2scp hwmod data
Add this hwmod data to allow USB3 to work in OMAP5 boards. Signed-off-by: Benoit Cousson <bcousson@baylibre.com> Signed-off-by: Felipe Balbi <balbi@ti.com> [tony@atomide.com: updated to apply against Paul's changes] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -1180,6 +1180,42 @@ static struct omap_hwmod omap54xx_spinlock_hwmod = {
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},
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};
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/*
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* 'ocp2scp' class
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* bridge to transform ocp interface protocol to scp (serial control port)
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* protocol
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*/
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static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
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.name = "ocp2scp",
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.sysc = &omap54xx_ocp2scp_sysc,
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};
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/* ocp2scp1 */
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static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
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.name = "ocp2scp1",
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.class = &omap54xx_ocp2scp_hwmod_class,
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.clkdm_name = "l3init_clkdm",
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.main_clk = "l4_root_clk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'timer' class
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* general purpose timer module with accurate 1ms tick
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@ -2120,6 +2156,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_cfg -> ocp2scp1 */
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static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
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.master = &omap54xx_l4_cfg_hwmod,
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.slave = &omap54xx_ocp2scp1_hwmod,
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.clk = "l4_root_clk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> timer1 */
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static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
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.master = &omap54xx_l4_wkup_hwmod,
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@ -2340,6 +2384,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
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&omap54xx_l4_per__mmc5,
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&omap54xx_l4_cfg__mpu,
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&omap54xx_l4_cfg__spinlock,
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&omap54xx_l4_cfg__ocp2scp1,
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&omap54xx_l4_wkup__timer1,
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&omap54xx_l4_per__timer2,
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&omap54xx_l4_per__timer3,
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