[media] cx2341x.rst: add contents of fw-memory.txt
Convert the content to ReST and add it at the cx231xx.rst file. Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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Mauro Carvalho Chehab
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The cx2341x driver
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==================
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Memory at cx2341x chips
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-----------------------
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This section describes the cx2341x memory map and documents some of the
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register space.
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.. note:: the memory long words are little-endian ('intel format').
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.. warning::
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This information was figured out from searching through the memory
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and registers, this information may not be correct and is certainly
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not complete, and was not derived from anything more than searching
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through the memory space with commands like:
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.. code-block:: none
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ivtvctl -O min=0x02000000,max=0x020000ff
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So take this as is, I'm always searching for more stuff, it's a large
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register space :-).
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Memory Map
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~~~~~~~~~~
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The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
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(Base Address Register 0). The addresses here are offsets relative to the
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address held in BAR0.
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.. code-block:: none
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0x00000000-0x00ffffff Encoder memory space
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0x00000000-0x0003ffff Encode.rom
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???-??? MPEG buffer(s)
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???-??? Raw video capture buffer(s)
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???-??? Raw audio capture buffer(s)
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???-??? Display buffers (6 or 9)
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0x01000000-0x01ffffff Decoder memory space
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0x01000000-0x0103ffff Decode.rom
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???-??? MPEG buffers(s)
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0x0114b000-0x0115afff Audio.rom (deprecated?)
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0x02000000-0x0200ffff Register Space
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Registers
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~~~~~~~~~
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The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
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All of these registers are 32 bits wide.
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.. code-block:: none
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DMA Registers 0x000-0xff:
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0x00 - Control:
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0=reset/cancel, 1=read, 2=write, 4=stop
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0x04 - DMA status:
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1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error
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0x08 - pci DMA pointer for read link list
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0x0c - pci DMA pointer for write link list
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0x10 - read/write DMA enable:
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1=read enable, 2=write enable
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0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
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0x18 - ??
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0x1c - always 0x20 or 32, smaller values slow down DMA transactions
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0x20 - always value of 0x780a010a
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0x24-0x3c - usually just random values???
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0x40 - Interrupt status
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0x44 - Write a bit here and shows up in Interrupt status 0x40
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0x48 - Interrupt Mask
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0x4C - always value of 0xfffdffff,
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if changed to 0xffffffff DMA write interrupts break.
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0x50 - always 0xffffffff
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0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
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3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the
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interrupt masks???).
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0x60-0x7C - random values
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0x80 - first write linked list reg, for Encoder Memory addr
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0x84 - first write linked list reg, for pci memory addr
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0x88 - first write linked list reg, for length of buffer in memory addr
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(|0x80000000 or this for last link)
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0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
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from linked list addr in reg 0x0c, firmware must push through or
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something.
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0xe0 - first (and only) read linked list reg, for pci memory addr
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0xe4 - first (and only) read linked list reg, for Decoder memory addr
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0xe8 - first (and only) read linked list reg, for length of buffer
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0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
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Memory locations for Encoder Buffers 0x700-0x7ff:
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These registers show offsets of memory locations pertaining to each
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buffer area used for encoding, have to shift them by <<1 first.
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- 0x07F8: Encoder SDRAM refresh
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- 0x07FC: Encoder SDRAM pre-charge
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Memory locations for Decoder Buffers 0x800-0x8ff:
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These registers show offsets of memory locations pertaining to each
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buffer area used for decoding, have to shift them by <<1 first.
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- 0x08F8: Decoder SDRAM refresh
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- 0x08FC: Decoder SDRAM pre-charge
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Other memory locations:
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- 0x2800: Video Display Module control
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- 0x2D00: AO (audio output?) control
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- 0x2D24: Bytes Flushed
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- 0x7000: LSB I2C write clock bit (inverted)
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- 0x7004: LSB I2C write data bit (inverted)
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- 0x7008: LSB I2C read clock bit
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- 0x700c: LSB I2C read data bit
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- 0x9008: GPIO get input state
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- 0x900c: GPIO set output state
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- 0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
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- 0x9050: SPU control
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- 0x9054: Reset HW blocks
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- 0x9058: VPU control
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- 0xA018: Bit6: interrupt pending?
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- 0xA064: APU command
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Interrupt Status Register
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~~~~~~~~~~~~~~~~~~~~~~~~~
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The definition of the bits in the interrupt status register 0x0040, and the
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interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to
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execute.
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- bit 31 Encoder Start Capture
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- bit 30 Encoder EOS
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- bit 29 Encoder VBI capture
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- bit 28 Encoder Video Input Module reset event
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- bit 27 Encoder DMA complete
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- bit 24 Decoder audio mode change detection event (through event notification)
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- bit 22 Decoder data request
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- bit 20 Decoder DMA complete
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- bit 19 Decoder VBI re-insertion
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- bit 18 Decoder DMA err (linked-list bad)
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Missing documentation
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---------------------
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- Encoder API post(?)
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- Decoder API post(?)
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- Decoder VTRACE event
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How to call the firmware API
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----------------------------
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@ -1,139 +0,0 @@
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This document describes the cx2341x memory map and documents some of the register
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space.
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Note: the memory long words are little-endian ('intel format').
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Warning! This information was figured out from searching through the memory and
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registers, this information may not be correct and is certainly not complete, and
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was not derived from anything more than searching through the memory space with
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commands like:
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ivtvctl -O min=0x02000000,max=0x020000ff
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So take this as is, I'm always searching for more stuff, it's a large
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register space :-).
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Memory Map
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==========
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The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
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(Base Address Register 0). The addresses here are offsets relative to the
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address held in BAR0.
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0x00000000-0x00ffffff Encoder memory space
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0x00000000-0x0003ffff Encode.rom
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???-??? MPEG buffer(s)
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???-??? Raw video capture buffer(s)
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???-??? Raw audio capture buffer(s)
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???-??? Display buffers (6 or 9)
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0x01000000-0x01ffffff Decoder memory space
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0x01000000-0x0103ffff Decode.rom
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???-??? MPEG buffers(s)
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0x0114b000-0x0115afff Audio.rom (deprecated?)
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0x02000000-0x0200ffff Register Space
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Registers
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=========
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The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
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All of these registers are 32 bits wide.
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DMA Registers 0x000-0xff:
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0x00 - Control:
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0=reset/cancel, 1=read, 2=write, 4=stop
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0x04 - DMA status:
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1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error
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0x08 - pci DMA pointer for read link list
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0x0c - pci DMA pointer for write link list
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0x10 - read/write DMA enable:
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1=read enable, 2=write enable
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0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
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0x18 - ??
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0x1c - always 0x20 or 32, smaller values slow down DMA transactions
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0x20 - always value of 0x780a010a
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0x24-0x3c - usually just random values???
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0x40 - Interrupt status
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0x44 - Write a bit here and shows up in Interrupt status 0x40
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0x48 - Interrupt Mask
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0x4C - always value of 0xfffdffff,
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if changed to 0xffffffff DMA write interrupts break.
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0x50 - always 0xffffffff
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0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
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3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the
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interrupt masks???).
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0x60-0x7C - random values
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0x80 - first write linked list reg, for Encoder Memory addr
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0x84 - first write linked list reg, for pci memory addr
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0x88 - first write linked list reg, for length of buffer in memory addr
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(|0x80000000 or this for last link)
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0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
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from linked list addr in reg 0x0c, firmware must push through or
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something.
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0xe0 - first (and only) read linked list reg, for pci memory addr
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0xe4 - first (and only) read linked list reg, for Decoder memory addr
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0xe8 - first (and only) read linked list reg, for length of buffer
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0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
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Memory locations for Encoder Buffers 0x700-0x7ff:
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These registers show offsets of memory locations pertaining to each
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buffer area used for encoding, have to shift them by <<1 first.
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0x07F8: Encoder SDRAM refresh
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0x07FC: Encoder SDRAM pre-charge
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Memory locations for Decoder Buffers 0x800-0x8ff:
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These registers show offsets of memory locations pertaining to each
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buffer area used for decoding, have to shift them by <<1 first.
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0x08F8: Decoder SDRAM refresh
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0x08FC: Decoder SDRAM pre-charge
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Other memory locations:
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0x2800: Video Display Module control
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0x2D00: AO (audio output?) control
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0x2D24: Bytes Flushed
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0x7000: LSB I2C write clock bit (inverted)
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0x7004: LSB I2C write data bit (inverted)
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0x7008: LSB I2C read clock bit
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0x700c: LSB I2C read data bit
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0x9008: GPIO get input state
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0x900c: GPIO set output state
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0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
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0x9050: SPU control
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0x9054: Reset HW blocks
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0x9058: VPU control
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0xA018: Bit6: interrupt pending?
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0xA064: APU command
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Interrupt Status Register
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=========================
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The definition of the bits in the interrupt status register 0x0040, and the
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interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to
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execute.
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Bit
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31 Encoder Start Capture
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30 Encoder EOS
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29 Encoder VBI capture
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28 Encoder Video Input Module reset event
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27 Encoder DMA complete
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24 Decoder audio mode change detection event (through event notification)
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22 Decoder data request
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20 Decoder DMA complete
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19 Decoder VBI re-insertion
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18 Decoder DMA err (linked-list bad)
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Missing
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Encoder API call completed
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Decoder API call completed
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Encoder API post(?)
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Decoder API post(?)
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Decoder VTRACE event
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