drm/i915: add platform tag to WA
v2: add more missing platform tags v3: change tag to cnp rather than using gen9,gen10 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171205190118.7088-2-lucas.demarchi@intel.com
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@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
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}
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}
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}
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}
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/* Display WA #1139 */
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/* Display WA #1139: glk */
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if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
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if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
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crtc_state->base.adjusted_mode.htotal > 5460)
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crtc_state->base.adjusted_mode.htotal > 5460)
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return false;
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return false;
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@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
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if (!HAS_PCH_CNP(dev_priv))
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if (!HAS_PCH_CNP(dev_priv))
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return;
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return;
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/* Display WA #1181 */
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/* Display WA #1181: cnp */
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I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
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I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
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CNP_PWM_CGE_GATING_DISABLE);
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CNP_PWM_CGE_GATING_DISABLE);
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}
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}
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