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Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 

Jeff Kirsher says:

====================
100GbE Intel Wired LAN Driver Updates 2020-05-22

This series contains updates to virtchnl and the ice driver.

Geert Uytterhoeven fixes a data structure alignment issue in the
virtchnl structures.

Henry adds Flow Director support which allows for the redirection on
ntuple rules over six patches.  Initially Henry adds the initial
infrastructure for Flow Director, and then later adds IPv4 and IPv6
support, as well as being able to display the ntuple rules.

Bret add Accelerated Receive Flow Steering (aRFS) support which is used
to steer receive flows to a specific queue.  Fixes a transmit timeout
when the VF link transitions from up/down/up because the transmit and
receive queue interrupts are not enabled as part of VF's link up.  Fixed
an issue when the default VF LAN address is changed and after reset the
PF will attempt to add the new MAC, which fails because it already
exists. This causes the VF to be disabled completely until it is removed
and enabled via sysfs.

Anirudh (Ani) makes a fix where the ice driver needs to call set_mac_cfg
to enable jumbo frames, so ensure it gets called during initialization
and after reset.  Fix bad register reads during a register dump in
ethtool by removing the bad registers.

Paul fixes an issue where the receive Malicious Driver Detection (MDD)
auto reset message was not being logged because it occurred after the VF
reset.

Victor adds a check for compatibility between the Dynamic Device
Personalization (DDP) package and the NIC firmware to ensure that
everything aligns.

Jesse fixes a administrative queue string call with the appropriate
error reporting variable.  Also fixed the loop variables that are
comparing or assigning signed against unsigned values.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2020-05-23 16:51:26 -07:00
parent 098205f3c6 c1e0883012
commit 2b1a7f741a
33 changed files with 5407 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/ethernet/intel/ice/Makefile
View File

@ -18,10 +18,13 @@ ice-y := ice_main.o \
ice_txrx_lib.o \
ice_txrx.o \
ice_fltr.o \
ice_fdir.o \
ice_ethtool_fdir.o \
ice_flex_pipe.o \
ice_flow.o \
ice_devlink.o \
ice_ethtool.o
ice-$(CONFIG_PCI_IOV) += ice_virtchnl_pf.o ice_sriov.o
ice-$(CONFIG_DCB) += ice_dcb.o ice_dcb_nl.o ice_dcb_lib.o
ice-$(CONFIG_RFS_ACCEL) += ice_arfs.o
ice-$(CONFIG_XDP_SOCKETS) += ice_xsk.o

53
drivers/net/ethernet/intel/ice/ice.h
View File

@ -34,6 +34,7 @@
#include <linux/ctype.h>
#include <linux/bpf.h>
#include <linux/avf/virtchnl.h>
#include <linux/cpu_rmap.h>
#include <net/devlink.h>
#include <net/ipv6.h>
#include <net/xdp_sock.h>
@ -50,7 +51,9 @@
#include "ice_sched.h"
#include "ice_virtchnl_pf.h"
#include "ice_sriov.h"
#include "ice_fdir.h"
#include "ice_xsk.h"
#include "ice_arfs.h"
extern const char ice_drv_ver[];
#define ICE_BAR0 0
@ -66,6 +69,7 @@ extern const char ice_drv_ver[];
#define ICE_AQ_LEN 64
#define ICE_MBXSQ_LEN 64
#define ICE_MIN_MSIX 2
#define ICE_FDIR_MSIX 1
#define ICE_NO_VSI 0xffff
#define ICE_VSI_MAP_CONTIG 0
#define ICE_VSI_MAP_SCATTER 1
@ -94,6 +98,7 @@ extern const char ice_drv_ver[];
#define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
#define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
#define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
#define ICE_TX_FDIRDESC(R, i) (&(((struct ice_fltr_desc *)((R)->desc))[i]))
/* Macro for each VSI in a PF */
#define ice_for_each_vsi(pf, i) \
@ -214,6 +219,7 @@ enum ice_state {
__ICE_CFG_BUSY,
__ICE_SERVICE_SCHED,
__ICE_SERVICE_DIS,
__ICE_FD_FLUSH_REQ,
__ICE_OICR_INTR_DIS, /* Global OICR interrupt disabled */
__ICE_MDD_VF_PRINT_PENDING, /* set when MDD event handle */
__ICE_VF_RESETS_DISABLED, /* disable resets during ice_remove */
@ -257,6 +263,8 @@ struct ice_vsi {
s16 vf_id; /* VF ID for SR-IOV VSIs */
u16 ethtype; /* Ethernet protocol for pause frame */
u16 num_gfltr;
u16 num_bfltr;
/* RSS config */
u16 rss_table_size; /* HW RSS table size */
@ -265,6 +273,14 @@ struct ice_vsi {
u8 *rss_lut_user; /* User configured lookup table entries */
u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */
/* aRFS members only allocated for the PF VSI */
#define ICE_MAX_ARFS_LIST 1024
#define ICE_ARFS_LST_MASK (ICE_MAX_ARFS_LIST - 1)
struct hlist_head *arfs_fltr_list;
struct ice_arfs_active_fltr_cntrs *arfs_fltr_cntrs;
spinlock_t arfs_lock; /* protects aRFS hash table and filter state */
atomic_t *arfs_last_fltr_id;
u16 max_frame;
u16 rx_buf_len;
@ -339,6 +355,7 @@ enum ice_pf_flags {
ICE_FLAG_SRIOV_CAPABLE,
ICE_FLAG_DCB_CAPABLE,
ICE_FLAG_DCB_ENA,
ICE_FLAG_FD_ENA,
ICE_FLAG_ADV_FEATURES,
ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA,
ICE_FLAG_NO_MEDIA,
@ -367,6 +384,8 @@ struct ice_pf {
*/
u16 sriov_base_vector;
u16 ctrl_vsi_idx; /* control VSI index in pf->vsi array */
struct ice_vsi **vsi; /* VSIs created by the driver */
struct ice_sw *first_sw; /* first switch created by firmware */
/* Virtchnl/SR-IOV config info */
@ -505,8 +524,27 @@ static inline struct ice_vsi *ice_get_main_vsi(struct ice_pf *pf)
return NULL;
}
/**
* ice_get_ctrl_vsi - Get the control VSI
* @pf: PF instance
*/
static inline struct ice_vsi *ice_get_ctrl_vsi(struct ice_pf *pf)
{
/* if pf->ctrl_vsi_idx is ICE_NO_VSI, control VSI was not set up */
if (!pf->vsi || pf->ctrl_vsi_idx == ICE_NO_VSI)
return NULL;
return pf->vsi[pf->ctrl_vsi_idx];
}
#define ICE_FD_STAT_CTR_BLOCK_COUNT 256
#define ICE_FD_STAT_PF_IDX(base_idx) \
((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT)
#define ICE_FD_SB_STAT_IDX(base_idx) ICE_FD_STAT_PF_IDX(base_idx)
int ice_vsi_setup_tx_rings(struct ice_vsi *vsi);
int ice_vsi_setup_rx_rings(struct ice_vsi *vsi);
int ice_vsi_open_ctrl(struct ice_vsi *vsi);
void ice_set_ethtool_ops(struct net_device *netdev);
void ice_set_ethtool_safe_mode_ops(struct net_device *netdev);
u16 ice_get_avail_txq_count(struct ice_pf *pf);
@ -530,7 +568,22 @@ int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset);
void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
const char *ice_stat_str(enum ice_status stat_err);
const char *ice_aq_str(enum ice_aq_err aq_err);
int
ice_fdir_write_fltr(struct ice_pf *pf, struct ice_fdir_fltr *input, bool add,
bool is_tun);
void ice_vsi_manage_fdir(struct ice_vsi *vsi, bool ena);
int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
int ice_del_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
int ice_get_ethtool_fdir_entry(struct ice_hw *hw, struct ethtool_rxnfc *cmd);
int
ice_get_fdir_fltr_ids(struct ice_hw *hw, struct ethtool_rxnfc *cmd,
u32 *rule_locs);
void ice_fdir_release_flows(struct ice_hw *hw);
void ice_fdir_replay_flows(struct ice_hw *hw);
void ice_fdir_replay_fltrs(struct ice_pf *pf);
int ice_fdir_create_dflt_rules(struct ice_pf *pf);
int ice_open(struct net_device *netdev);
int ice_stop(struct net_device *netdev);
void ice_service_task_schedule(struct ice_pf *pf);
#endif /* _ICE_H_ */

34
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
View File

@ -107,6 +107,7 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_RXQS 0x0041
#define ICE_AQC_CAPS_TXQS 0x0042
#define ICE_AQC_CAPS_MSIX 0x0043
#define ICE_AQC_CAPS_FD 0x0045
#define ICE_AQC_CAPS_MAX_MTU 0x0047
u8 major_ver;
@ -232,6 +233,11 @@ struct ice_aqc_get_sw_cfg_resp {
*/
#define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
#define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
#define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
#define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
@ -240,6 +246,9 @@ struct ice_aqc_get_sw_cfg_resp {
#define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
#define ICE_AQC_RES_TYPE_S 0
#define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
/* Allocate Resources command (indirect 0x0208)
* Free Resources command (indirect 0x0209)
*/
@ -1059,6 +1068,25 @@ struct ice_aqc_set_phy_cfg_data {
u8 rsvd1;
};
/* Set MAC Config command data structure (direct 0x0603) */
struct ice_aqc_set_mac_cfg {
__le16 max_frame_size;
u8 params;
#define ICE_AQ_SET_MAC_PACE_S 3
#define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
#define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
u8 tx_tmr_priority;
__le16 tx_tmr_value;
__le16 fc_refresh_threshold;
u8 drop_opts;
#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
#define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
u8 reserved[7];
};
/* Restart AN command data structure (direct 0x0605)
* Also used for response, with only the lport_num field present.
*/
@ -1675,10 +1703,12 @@ struct ice_pkg_ver {
};
#define ICE_PKG_NAME_SIZE 32
#define ICE_SEG_NAME_SIZE 28
struct ice_aqc_get_pkg_info {
struct ice_pkg_ver ver;
char name[ICE_PKG_NAME_SIZE];
char name[ICE_SEG_NAME_SIZE];
__le32 track_id;
u8 is_in_nvm;
u8 is_active;
u8 is_active_at_boot;
@ -1765,6 +1795,7 @@ struct ice_aq_desc {
struct ice_aqc_download_pkg download_pkg;
struct ice_aqc_set_mac_lb set_mac_lb;
struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
struct ice_aqc_set_mac_cfg set_mac_cfg;
struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
@ -1861,6 +1892,7 @@ enum ice_adminq_opc {
/* PHY commands */
ice_aqc_opc_get_phy_caps = 0x0600,
ice_aqc_opc_set_phy_cfg = 0x0601,
ice_aqc_opc_set_mac_cfg = 0x0603,
ice_aqc_opc_restart_an = 0x0605,
ice_aqc_opc_get_link_status = 0x0607,
ice_aqc_opc_set_event_mask = 0x0613,

663
drivers/net/ethernet/intel/ice/ice_arfs.c Normal file
View File

@ -0,0 +1,663 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2018-2020, Intel Corporation. */
#include "ice.h"
/**
* ice_is_arfs_active - helper to check is aRFS is active
* @vsi: VSI to check
*/
static bool ice_is_arfs_active(struct ice_vsi *vsi)
{
return !!vsi->arfs_fltr_list;
}
/**
* ice_is_arfs_using_perfect_flow - check if aRFS has active perfect filters
* @hw: pointer to the HW structure
* @flow_type: flow type as Flow Director understands it
*
* Flow Director will query this function to see if aRFS is currently using
* the specified flow_type for perfect (4-tuple) filters.
*/
bool
ice_is_arfs_using_perfect_flow(struct ice_hw *hw, enum ice_fltr_ptype flow_type)
{
struct ice_arfs_active_fltr_cntrs *arfs_fltr_cntrs;
struct ice_pf *pf = hw->back;
struct ice_vsi *vsi;
vsi = ice_get_main_vsi(pf);
if (!vsi)
return false;
arfs_fltr_cntrs = vsi->arfs_fltr_cntrs;
/* active counters can be updated by multiple CPUs */
smp_mb__before_atomic();
switch (flow_type) {
case ICE_FLTR_PTYPE_NONF_IPV4_UDP:
return atomic_read(&arfs_fltr_cntrs->active_udpv4_cnt) > 0;
case ICE_FLTR_PTYPE_NONF_IPV6_UDP:
return atomic_read(&arfs_fltr_cntrs->active_udpv6_cnt) > 0;
case ICE_FLTR_PTYPE_NONF_IPV4_TCP:
return atomic_read(&arfs_fltr_cntrs->active_tcpv4_cnt) > 0;
case ICE_FLTR_PTYPE_NONF_IPV6_TCP:
return atomic_read(&arfs_fltr_cntrs->active_tcpv6_cnt) > 0;
default:
return false;
}
}
/**
* ice_arfs_update_active_fltr_cntrs - update active filter counters for aRFS
* @vsi: VSI that aRFS is active on
* @entry: aRFS entry used to change counters
* @add: true to increment counter, false to decrement
*/
static void
ice_arfs_update_active_fltr_cntrs(struct ice_vsi *vsi,
struct ice_arfs_entry *entry, bool add)
{
struct ice_arfs_active_fltr_cntrs *fltr_cntrs = vsi->arfs_fltr_cntrs;
switch (entry->fltr_info.flow_type) {
case ICE_FLTR_PTYPE_NONF_IPV4_TCP:
if (add)
atomic_inc(&fltr_cntrs->active_tcpv4_cnt);
else
atomic_dec(&fltr_cntrs->active_tcpv4_cnt);
break;
case ICE_FLTR_PTYPE_NONF_IPV6_TCP:
if (add)
atomic_inc(&fltr_cntrs->active_tcpv6_cnt);
else
atomic_dec(&fltr_cntrs->active_tcpv6_cnt);
break;
case ICE_FLTR_PTYPE_NONF_IPV4_UDP:
if (add)
atomic_inc(&fltr_cntrs->active_udpv4_cnt);
else
atomic_dec(&fltr_cntrs->active_udpv4_cnt);
break;
case ICE_FLTR_PTYPE_NONF_IPV6_UDP:
if (add)
atomic_inc(&fltr_cntrs->active_udpv6_cnt);
else
atomic_dec(&fltr_cntrs->active_udpv6_cnt);
break;
default:
dev_err(ice_pf_to_dev(vsi->back), "aRFS: Failed to update filter counters, invalid filter type %d\n",
entry->fltr_info.flow_type);
}
}
/**
* ice_arfs_del_flow_rules - delete the rules passed in from HW
* @vsi: VSI for the flow rules that need to be deleted
* @del_list_head: head of the list of ice_arfs_entry(s) for rule deletion
*
* Loop through the delete list passed in and remove the rules from HW. After
* each rule is deleted, disconnect and free the ice_arfs_entry because it is no
* longer being referenced by the aRFS hash table.
*/
static void
ice_arfs_del_flow_rules(struct ice_vsi *vsi, struct hlist_head *del_list_head)
{
struct ice_arfs_entry *e;
struct hlist_node *n;
struct device *dev;
dev = ice_pf_to_dev(vsi->back);
hlist_for_each_entry_safe(e, n, del_list_head, list_entry) {
int result;
result = ice_fdir_write_fltr(vsi->back, &e->fltr_info, false,
false);
if (!result)
ice_arfs_update_active_fltr_cntrs(vsi, e, false);
else
dev_dbg(dev, "Unable to delete aRFS entry, err %d fltr_state %d fltr_id %d flow_id %d Q %d\n",
result, e->fltr_state, e->fltr_info.fltr_id,
e->flow_id, e->fltr_info.q_index);
/* The aRFS hash table is no longer referencing this entry */
hlist_del(&e->list_entry);
devm_kfree(dev, e);
}
}
/**
* ice_arfs_add_flow_rules - add the rules passed in from HW
* @vsi: VSI for the flow rules that need to be added
* @add_list_head: head of the list of ice_arfs_entry_ptr(s) for rule addition
*
* Loop through the add list passed in and remove the rules from HW. After each
* rule is added, disconnect and free the ice_arfs_entry_ptr node. Don't free
* the ice_arfs_entry(s) because they are still being referenced in the aRFS
* hash table.
*/
static void
ice_arfs_add_flow_rules(struct ice_vsi *vsi, struct hlist_head *add_list_head)
{
struct ice_arfs_entry_ptr *ep;
struct hlist_node *n;
struct device *dev;
dev = ice_pf_to_dev(vsi->back);
hlist_for_each_entry_safe(ep, n, add_list_head, list_entry) {
int result;
result = ice_fdir_write_fltr(vsi->back,
&ep->arfs_entry->fltr_info, true,
false);
if (!result)
ice_arfs_update_active_fltr_cntrs(vsi, ep->arfs_entry,
true);
else
dev_dbg(dev, "Unable to add aRFS entry, err %d fltr_state %d fltr_id %d flow_id %d Q %d\n",
result, ep->arfs_entry->fltr_state,
ep->arfs_entry->fltr_info.fltr_id,
ep->arfs_entry->flow_id,
ep->arfs_entry->fltr_info.q_index);
hlist_del(&ep->list_entry);
devm_kfree(dev, ep);
}
}
/**
* ice_arfs_is_flow_expired - check if the aRFS entry has expired
* @vsi: VSI containing the aRFS entry
* @arfs_entry: aRFS entry that's being checked for expiration
*
* Return true if the flow has expired, else false. This function should be used
* to determine whether or not an aRFS entry should be removed from the hardware
* and software structures.
*/
static bool
ice_arfs_is_flow_expired(struct ice_vsi *vsi, struct ice_arfs_entry *arfs_entry)
{
#define ICE_ARFS_TIME_DELTA_EXPIRATION msecs_to_jiffies(5000)
if (rps_may_expire_flow(vsi->netdev, arfs_entry->fltr_info.q_index,
arfs_entry->flow_id,
arfs_entry->fltr_info.fltr_id))
return true;
/* expiration timer only used for UDP filters */
if (arfs_entry->fltr_info.flow_type != ICE_FLTR_PTYPE_NONF_IPV4_UDP &&
arfs_entry->fltr_info.flow_type != ICE_FLTR_PTYPE_NONF_IPV6_UDP)
return false;
return time_in_range64(arfs_entry->time_activated +
ICE_ARFS_TIME_DELTA_EXPIRATION,
arfs_entry->time_activated, get_jiffies_64());
}
/**
* ice_arfs_update_flow_rules - add/delete aRFS rules in HW
* @vsi: the VSI to be forwarded to
* @idx: index into the table of aRFS filter lists. Obtained from skb->hash
* @add_list: list to populate with filters to be added to Flow Director
* @del_list: list to populate with filters to be deleted from Flow Director
*
* Iterate over the hlist at the index given in the aRFS hash table and
* determine if there are any aRFS entries that need to be either added or
* deleted in the HW. If the aRFS entry is marked as ICE_ARFS_INACTIVE the
* filter needs to be added to HW, else if it's marked as ICE_ARFS_ACTIVE and
* the flow has expired delete the filter from HW. The caller of this function
* is expected to add/delete rules on the add_list/del_list respectively.
*/
static void
ice_arfs_update_flow_rules(struct ice_vsi *vsi, u16 idx,
struct hlist_head *add_list,
struct hlist_head *del_list)
{
struct ice_arfs_entry *e;
struct hlist_node *n;
struct device *dev;
dev = ice_pf_to_dev(vsi->back);
/* go through the aRFS hlist at this idx and check for needed updates */
hlist_for_each_entry_safe(e, n, &vsi->arfs_fltr_list[idx], list_entry)
/* check if filter needs to be added to HW */
if (e->fltr_state == ICE_ARFS_INACTIVE) {
enum ice_fltr_ptype flow_type = e->fltr_info.flow_type;
struct ice_arfs_entry_ptr *ep =
devm_kzalloc(dev, sizeof(*ep), GFP_ATOMIC);
if (!ep)
continue;
INIT_HLIST_NODE(&ep->list_entry);
/* reference aRFS entry to add HW filter */
ep->arfs_entry = e;
hlist_add_head(&ep->list_entry, add_list);
e->fltr_state = ICE_ARFS_ACTIVE;
/* expiration timer only used for UDP flows */
if (flow_type == ICE_FLTR_PTYPE_NONF_IPV4_UDP ||
flow_type == ICE_FLTR_PTYPE_NONF_IPV6_UDP)
e->time_activated = get_jiffies_64();
} else if (e->fltr_state == ICE_ARFS_ACTIVE) {
/* check if filter needs to be removed from HW */
if (ice_arfs_is_flow_expired(vsi, e)) {
/* remove aRFS entry from hash table for delete
* and to prevent referencing it the next time
* through this hlist index
*/
hlist_del(&e->list_entry);
e->fltr_state = ICE_ARFS_TODEL;
/* save reference to aRFS entry for delete */
hlist_add_head(&e->list_entry, del_list);
}
}
}
/**
* ice_sync_arfs_fltrs - update all aRFS filters
* @pf: board private structure
*/
void ice_sync_arfs_fltrs(struct ice_pf *pf)
{
HLIST_HEAD(tmp_del_list);
HLIST_HEAD(tmp_add_list);
struct ice_vsi *pf_vsi;
unsigned int i;
pf_vsi = ice_get_main_vsi(pf);
if (!pf_vsi)
return;
if (!ice_is_arfs_active(pf_vsi))
return;
spin_lock_bh(&pf_vsi->arfs_lock);
/* Once we process aRFS for the PF VSI get out */
for (i = 0; i < ICE_MAX_ARFS_LIST; i++)
ice_arfs_update_flow_rules(pf_vsi, i, &tmp_add_list,
&tmp_del_list);
spin_unlock_bh(&pf_vsi->arfs_lock);
/* use list of ice_arfs_entry(s) for delete */
ice_arfs_del_flow_rules(pf_vsi, &tmp_del_list);
/* use list of ice_arfs_entry_ptr(s) for add */
ice_arfs_add_flow_rules(pf_vsi, &tmp_add_list);
}
/**
* ice_arfs_build_entry - builds an aRFS entry based on input
* @vsi: destination VSI for this flow
* @fk: flow dissector keys for creating the tuple
* @rxq_idx: Rx queue to steer this flow to
* @flow_id: passed down from the stack and saved for flow expiration
*
* returns an aRFS entry on success and NULL on failure
*/
static struct ice_arfs_entry *
ice_arfs_build_entry(struct ice_vsi *vsi, const struct flow_keys *fk,
u16 rxq_idx, u32 flow_id)
{
struct ice_arfs_entry *arfs_entry;
struct ice_fdir_fltr *fltr_info;
u8 ip_proto;
arfs_entry = devm_kzalloc(ice_pf_to_dev(vsi->back),
sizeof(*arfs_entry),
GFP_ATOMIC | __GFP_NOWARN);
if (!arfs_entry)
return NULL;
fltr_info = &arfs_entry->fltr_info;
fltr_info->q_index = rxq_idx;
fltr_info->dest_ctl = ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_QINDEX;
fltr_info->dest_vsi = vsi->idx;
ip_proto = fk->basic.ip_proto;
if (fk->basic.n_proto == htons(ETH_P_IP)) {
fltr_info->ip.v4.proto = ip_proto;
fltr_info->flow_type = (ip_proto == IPPROTO_TCP) ?
ICE_FLTR_PTYPE_NONF_IPV4_TCP :
ICE_FLTR_PTYPE_NONF_IPV4_UDP;
fltr_info->ip.v4.src_ip = fk->addrs.v4addrs.src;
fltr_info->ip.v4.dst_ip = fk->addrs.v4addrs.dst;
fltr_info->ip.v4.src_port = fk->ports.src;
fltr_info->ip.v4.dst_port = fk->ports.dst;
} else { /* ETH_P_IPV6 */
fltr_info->ip.v6.proto = ip_proto;
fltr_info->flow_type = (ip_proto == IPPROTO_TCP) ?
ICE_FLTR_PTYPE_NONF_IPV6_TCP :
ICE_FLTR_PTYPE_NONF_IPV6_UDP;
memcpy(&fltr_info->ip.v6.src_ip, &fk->addrs.v6addrs.src,
sizeof(struct in6_addr));
memcpy(&fltr_info->ip.v6.dst_ip, &fk->addrs.v6addrs.dst,
sizeof(struct in6_addr));
fltr_info->ip.v6.src_port = fk->ports.src;
fltr_info->ip.v6.dst_port = fk->ports.dst;
}
arfs_entry->flow_id = flow_id;
fltr_info->fltr_id =
atomic_inc_return(vsi->arfs_last_fltr_id) % RPS_NO_FILTER;
return arfs_entry;
}
/**
* ice_arfs_is_perfect_flow_set - Check to see if perfect flow is set
* @hw: pointer to HW structure
* @l3_proto: ETH_P_IP or ETH_P_IPV6 in network order
* @l4_proto: IPPROTO_UDP or IPPROTO_TCP
*
* We only support perfect (4-tuple) filters for aRFS. This function allows aRFS
* to check if perfect (4-tuple) flow rules are currently in place by Flow
* Director.
*/
static bool
ice_arfs_is_perfect_flow_set(struct ice_hw *hw, __be16 l3_proto, u8 l4_proto)
{
unsigned long *perfect_fltr = hw->fdir_perfect_fltr;
/* advanced Flow Director disabled, perfect filters always supported */
if (!perfect_fltr)
return true;
if (l3_proto == htons(ETH_P_IP) && l4_proto == IPPROTO_UDP)
return test_bit(ICE_FLTR_PTYPE_NONF_IPV4_UDP, perfect_fltr);
else if (l3_proto == htons(ETH_P_IP) && l4_proto == IPPROTO_TCP)
return test_bit(ICE_FLTR_PTYPE_NONF_IPV4_TCP, perfect_fltr);
else if (l3_proto == htons(ETH_P_IPV6) && l4_proto == IPPROTO_UDP)
return test_bit(ICE_FLTR_PTYPE_NONF_IPV6_UDP, perfect_fltr);
else if (l3_proto == htons(ETH_P_IPV6) && l4_proto == IPPROTO_TCP)
return test_bit(ICE_FLTR_PTYPE_NONF_IPV6_TCP, perfect_fltr);
return false;
}
/**
* ice_rx_flow_steer - steer the Rx flow to where application is being run
* @netdev: ptr to the netdev being adjusted
* @skb: buffer with required header information
* @rxq_idx: queue to which the flow needs to move
* @flow_id: flow identifier provided by the netdev
*
* Based on the skb, rxq_idx, and flow_id passed in add/update an entry in the
* aRFS hash table. Iterate over one of the hlists in the aRFS hash table and
* if the flow_id already exists in the hash table but the rxq_idx has changed
* mark the entry as ICE_ARFS_INACTIVE so it can get updated in HW, else
* if the entry is marked as ICE_ARFS_TODEL delete it from the aRFS hash table.
* If neither of the previous conditions are true then add a new entry in the
* aRFS hash table, which gets set to ICE_ARFS_INACTIVE by default so it can be
* added to HW.
*/
int
ice_rx_flow_steer(struct net_device *netdev, const struct sk_buff *skb,
u16 rxq_idx, u32 flow_id)
{
struct ice_netdev_priv *np = netdev_priv(netdev);
struct ice_arfs_entry *arfs_entry;
struct ice_vsi *vsi = np->vsi;
struct flow_keys fk;
struct ice_pf *pf;
__be16 n_proto;
u8 ip_proto;
u16 idx;
int ret;
/* failed to allocate memory for aRFS so don't crash */
if (unlikely(!vsi->arfs_fltr_list))
return -ENODEV;
pf = vsi->back;
if (skb->encapsulation)
return -EPROTONOSUPPORT;
if (!skb_flow_dissect_flow_keys(skb, &fk, 0))
return -EPROTONOSUPPORT;
n_proto = fk.basic.n_proto;
/* Support only IPV4 and IPV6 */
if ((n_proto == htons(ETH_P_IP) && !ip_is_fragment(ip_hdr(skb))) ||
n_proto == htons(ETH_P_IPV6))
ip_proto = fk.basic.ip_proto;
else
return -EPROTONOSUPPORT;
/* Support only TCP and UDP */
if (ip_proto != IPPROTO_TCP && ip_proto != IPPROTO_UDP)
return -EPROTONOSUPPORT;
/* only support 4-tuple filters for aRFS */
if (!ice_arfs_is_perfect_flow_set(&pf->hw, n_proto, ip_proto))
return -EOPNOTSUPP;
/* choose the aRFS list bucket based on skb hash */
idx = skb_get_hash_raw(skb) & ICE_ARFS_LST_MASK;
/* search for entry in the bucket */
spin_lock_bh(&vsi->arfs_lock);
hlist_for_each_entry(arfs_entry, &vsi->arfs_fltr_list[idx],
list_entry) {
struct ice_fdir_fltr *fltr_info;
/* keep searching for the already existing arfs_entry flow */
if (arfs_entry->flow_id != flow_id)
continue;
fltr_info = &arfs_entry->fltr_info;
ret = fltr_info->fltr_id;
if (fltr_info->q_index == rxq_idx ||
arfs_entry->fltr_state != ICE_ARFS_ACTIVE)
goto out;
/* update the queue to forward to on an already existing flow */
fltr_info->q_index = rxq_idx;
arfs_entry->fltr_state = ICE_ARFS_INACTIVE;
ice_arfs_update_active_fltr_cntrs(vsi, arfs_entry, false);
goto out_schedule_service_task;
}
arfs_entry = ice_arfs_build_entry(vsi, &fk, rxq_idx, flow_id);
if (!arfs_entry) {
ret = -ENOMEM;
goto out;
}
ret = arfs_entry->fltr_info.fltr_id;
INIT_HLIST_NODE(&arfs_entry->list_entry);
hlist_add_head(&arfs_entry->list_entry, &vsi->arfs_fltr_list[idx]);
out_schedule_service_task:
ice_service_task_schedule(pf);
out:
spin_unlock_bh(&vsi->arfs_lock);
return ret;
}
/**
* ice_init_arfs_cntrs - initialize aRFS counter values
* @vsi: VSI that aRFS counters need to be initialized on
*/
static int ice_init_arfs_cntrs(struct ice_vsi *vsi)
{
if (!vsi || vsi->type != ICE_VSI_PF)
return -EINVAL;
vsi->arfs_fltr_cntrs = kzalloc(sizeof(*vsi->arfs_fltr_cntrs),
GFP_KERNEL);
if (!vsi->arfs_fltr_cntrs)
return -ENOMEM;
vsi->arfs_last_fltr_id = kzalloc(sizeof(*vsi->arfs_last_fltr_id),
GFP_KERNEL);
if (!vsi->arfs_last_fltr_id) {
kfree(vsi->arfs_fltr_cntrs);
vsi->arfs_fltr_cntrs = NULL;
return -ENOMEM;
}
return 0;
}
/**
* ice_init_arfs - initialize aRFS resources
* @vsi: the VSI to be forwarded to
*/
void ice_init_arfs(struct ice_vsi *vsi)
{
struct hlist_head *arfs_fltr_list;
unsigned int i;
if (!vsi || vsi->type != ICE_VSI_PF)
return;
arfs_fltr_list = kzalloc(sizeof(*arfs_fltr_list) * ICE_MAX_ARFS_LIST,
GFP_KERNEL);
if (!arfs_fltr_list)
return;
if (ice_init_arfs_cntrs(vsi))
goto free_arfs_fltr_list;
for (i = 0; i < ICE_MAX_ARFS_LIST; i++)
INIT_HLIST_HEAD(&arfs_fltr_list[i]);
spin_lock_init(&vsi->arfs_lock);
vsi->arfs_fltr_list = arfs_fltr_list;
return;
free_arfs_fltr_list:
kfree(arfs_fltr_list);
}
/**
* ice_clear_arfs - clear the aRFS hash table and any memory used for aRFS
* @vsi: the VSI to be forwarded to
*/
void ice_clear_arfs(struct ice_vsi *vsi)
{
struct device *dev;
unsigned int i;
if (!vsi || vsi->type != ICE_VSI_PF || !vsi->back ||
!vsi->arfs_fltr_list)
return;
dev = ice_pf_to_dev(vsi->back);
for (i = 0; i < ICE_MAX_ARFS_LIST; i++) {
struct ice_arfs_entry *r;
struct hlist_node *n;
spin_lock_bh(&vsi->arfs_lock);
hlist_for_each_entry_safe(r, n, &vsi->arfs_fltr_list[i],
list_entry) {
hlist_del(&r->list_entry);
devm_kfree(dev, r);
}
spin_unlock_bh(&vsi->arfs_lock);
}
kfree(vsi->arfs_fltr_list);
vsi->arfs_fltr_list = NULL;
kfree(vsi->arfs_last_fltr_id);
vsi->arfs_last_fltr_id = NULL;
kfree(vsi->arfs_fltr_cntrs);
vsi->arfs_fltr_cntrs = NULL;
}
/**
* ice_free_cpu_rx_rmap - free setup CPU reverse map
* @vsi: the VSI to be forwarded to
*/
void ice_free_cpu_rx_rmap(struct ice_vsi *vsi)
{
struct net_device *netdev;
if (!vsi || vsi->type != ICE_VSI_PF || !vsi->arfs_fltr_list)
return;
netdev = vsi->netdev;
if (!netdev || !netdev->rx_cpu_rmap ||
netdev->reg_state != NETREG_REGISTERED)
return;
free_irq_cpu_rmap(netdev->rx_cpu_rmap);
netdev->rx_cpu_rmap = NULL;
}
/**
* ice_set_cpu_rx_rmap - setup CPU reverse map for each queue
* @vsi: the VSI to be forwarded to
*/
int ice_set_cpu_rx_rmap(struct ice_vsi *vsi)
{
struct net_device *netdev;
struct ice_pf *pf;
int base_idx, i;
if (!vsi || vsi->type != ICE_VSI_PF)
return -EINVAL;
pf = vsi->back;
netdev = vsi->netdev;
if (!pf || !netdev || !vsi->num_q_vectors ||
vsi->netdev->reg_state != NETREG_REGISTERED)
return -EINVAL;
netdev_dbg(netdev, "Setup CPU RMAP: vsi type 0x%x, ifname %s, q_vectors %d\n",
vsi->type, netdev->name, vsi->num_q_vectors);
netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(vsi->num_q_vectors);
if (unlikely(!netdev->rx_cpu_rmap))
return -EINVAL;
base_idx = vsi->base_vector;
for (i = 0; i < vsi->num_q_vectors; i++)
if (irq_cpu_rmap_add(netdev->rx_cpu_rmap,
pf->msix_entries[base_idx + i].vector)) {
ice_free_cpu_rx_rmap(vsi);
return -EINVAL;
}
return 0;
}
/**
* ice_remove_arfs - remove/clear all aRFS resources
* @pf: device private structure
*/
void ice_remove_arfs(struct ice_pf *pf)
{
struct ice_vsi *pf_vsi;
pf_vsi = ice_get_main_vsi(pf);
if (!pf_vsi)
return;
ice_free_cpu_rx_rmap(pf_vsi);
ice_clear_arfs(pf_vsi);
}
/**
* ice_rebuild_arfs - remove/clear all aRFS resources and rebuild after reset
* @pf: device private structure
*/
void ice_rebuild_arfs(struct ice_pf *pf)
{
struct ice_vsi *pf_vsi;
pf_vsi = ice_get_main_vsi(pf);
if (!pf_vsi)
return;
ice_remove_arfs(pf);
if (ice_set_cpu_rx_rmap(pf_vsi)) {
dev_err(ice_pf_to_dev(pf), "Failed to rebuild aRFS\n");
return;
}
ice_init_arfs(pf_vsi);
}

82
drivers/net/ethernet/intel/ice/ice_arfs.h Normal file
View File

@ -0,0 +1,82 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2018-2020, Intel Corporation. */
#ifndef _ICE_ARFS_H_
#define _ICE_ARFS_H_
enum ice_arfs_fltr_state {
ICE_ARFS_INACTIVE,
ICE_ARFS_ACTIVE,
ICE_ARFS_TODEL,
};
struct ice_arfs_entry {
struct ice_fdir_fltr fltr_info;
struct hlist_node list_entry;
u64 time_activated; /* only valid for UDP flows */
u32 flow_id;
/* fltr_state = 0 - ICE_ARFS_INACTIVE:
* filter needs to be updated or programmed in HW.
* fltr_state = 1 - ICE_ARFS_ACTIVE:
* filter is active and programmed in HW.
* fltr_state = 2 - ICE_ARFS_TODEL:
* filter has been deleted from HW and needs to be removed from
* the aRFS hash table.
*/
u8 fltr_state;
};
struct ice_arfs_entry_ptr {
struct ice_arfs_entry *arfs_entry;
struct hlist_node list_entry;
};
struct ice_arfs_active_fltr_cntrs {
atomic_t active_tcpv4_cnt;
atomic_t active_tcpv6_cnt;
atomic_t active_udpv4_cnt;
atomic_t active_udpv6_cnt;
};
#ifdef CONFIG_RFS_ACCEL
int
ice_rx_flow_steer(struct net_device *netdev, const struct sk_buff *skb,
u16 rxq_idx, u32 flow_id);
void ice_clear_arfs(struct ice_vsi *vsi);
void ice_free_cpu_rx_rmap(struct ice_vsi *vsi);
void ice_init_arfs(struct ice_vsi *vsi);
void ice_sync_arfs_fltrs(struct ice_pf *pf);
int ice_set_cpu_rx_rmap(struct ice_vsi *vsi);
void ice_remove_arfs(struct ice_pf *pf);
void ice_rebuild_arfs(struct ice_pf *pf);
bool
ice_is_arfs_using_perfect_flow(struct ice_hw *hw,
enum ice_fltr_ptype flow_type);
#else
#define ice_sync_arfs_fltrs(pf) do {} while (0)
#define ice_init_arfs(vsi) do {} while (0)
#define ice_clear_arfs(vsi) do {} while (0)
#define ice_remove_arfs(pf) do {} while (0)
#define ice_free_cpu_rx_rmap(vsi) do {} while (0)
#define ice_rebuild_arfs(pf) do {} while (0)
static inline int ice_set_cpu_rx_rmap(struct ice_vsi __always_unused *vsi)
{
return 0;
}
static inline int
ice_rx_flow_steer(struct net_device __always_unused *netdev,
const struct sk_buff __always_unused *skb,
u16 __always_unused rxq_idx, u32 __always_unused flow_id)
{
return -EOPNOTSUPP;
}
static inline bool
ice_is_arfs_using_perfect_flow(struct ice_hw __always_unused *hw,
enum ice_fltr_ptype __always_unused flow_type)
{
return false;
}
#endif /* CONFIG_RFS_ACCEL */
#endif /* _ICE_ARFS_H_ */

1
drivers/net/ethernet/intel/ice/ice_base.c
View File

@ -247,6 +247,7 @@ ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)
*/
switch (vsi->type) {
case ICE_VSI_LB:
case ICE_VSI_CTRL:
case ICE_VSI_PF:
tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
break;

105
drivers/net/ethernet/intel/ice/ice_common.c
View File

@ -315,6 +315,71 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
return 0;
}
/**
* ice_fill_tx_timer_and_fc_thresh
* @hw: pointer to the HW struct
* @cmd: pointer to MAC cfg structure
*
* Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
* descriptor
*/
static void
ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
struct ice_aqc_set_mac_cfg *cmd)
{
u16 fc_thres_val, tx_timer_val;
u32 val;
/* We read back the transmit timer and FC threshold value of
* LFC. Thus, we will use index =
* PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
*
* Also, because we are operating on transmit timer and FC
* threshold of LFC, we don't turn on any bit in tx_tmr_priority
*/
#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
/* Retrieve the transmit timer */
val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
tx_timer_val = val &
PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);
/* Retrieve the FC threshold */
val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);
}
/**
* ice_aq_set_mac_cfg
* @hw: pointer to the HW struct
* @max_frame_size: Maximum Frame Size to be supported
* @cd: pointer to command details structure or NULL
*
* Set MAC configuration (0x0603)
*/
enum ice_status
ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
{
struct ice_aqc_set_mac_cfg *cmd;
struct ice_aq_desc desc;
cmd = &desc.params.set_mac_cfg;
if (max_frame_size == 0)
return ICE_ERR_PARAM;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
cmd->max_frame_size = cpu_to_le16(max_frame_size);
ice_fill_tx_timer_and_fc_thresh(hw, cmd);
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
/**
* ice_init_fltr_mgmt_struct - initializes filter management list and locks
* @hw: pointer to the HW struct
@ -653,6 +718,10 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_cqinit;
/* Set bit to enable Flow Director filters */
wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
INIT_LIST_HEAD(&hw->fdir_list_head);
ice_clear_pxe_mode(hw);
status = ice_init_nvm(hw);
@ -741,6 +810,14 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
devm_kfree(ice_hw_to_dev(hw), mac_buf);
if (status)
goto err_unroll_fltr_mgmt_struct;
/* enable jumbo frame support at MAC level */
status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
if (status)
goto err_unroll_fltr_mgmt_struct;
/* Obtain counter base index which would be used by flow director */
status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
if (status)
goto err_unroll_fltr_mgmt_struct;
status = ice_init_hw_tbls(hw);
@ -770,6 +847,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
*/
void ice_deinit_hw(struct ice_hw *hw)
{
ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
ice_cleanup_fltr_mgmt_struct(hw);
ice_sched_cleanup_all(hw);
@ -1680,6 +1758,33 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
"%s: msix_vector_first_id = %d\n", prefix,
caps->msix_vector_first_id);
break;
case ICE_AQC_CAPS_FD:
if (dev_p) {
dev_p->num_flow_director_fltr = number;
ice_debug(hw, ICE_DBG_INIT,
"%s: num_flow_director_fltr = %d\n",
prefix,
dev_p->num_flow_director_fltr);
}
if (func_p) {
u32 reg_val, val;
reg_val = rd32(hw, GLQF_FD_SIZE);
val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
GLQF_FD_SIZE_FD_GSIZE_S;
func_p->fd_fltr_guar =
ice_get_num_per_func(hw, val);
val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
GLQF_FD_SIZE_FD_BSIZE_S;
func_p->fd_fltr_best_effort = val;
ice_debug(hw, ICE_DBG_INIT,
"%s: fd_fltr_guar = %d\n",
prefix, func_p->fd_fltr_guar);
ice_debug(hw, ICE_DBG_INIT,
"%s: fd_fltr_best_effort = %d\n",
prefix, func_p->fd_fltr_best_effort);
}
break;
case ICE_AQC_CAPS_MAX_MTU:
caps->max_mtu = number;
ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",

2
drivers/net/ethernet/intel/ice/ice_common.h
View File

@ -108,6 +108,8 @@ enum ice_status
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
struct ice_sq_cd *cd);
enum ice_status
ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
enum ice_status
ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
struct ice_link_status *link, struct ice_sq_cd *cd);
enum ice_status

9
drivers/net/ethernet/intel/ice/ice_dcb_nl.c
View File

@ -671,7 +671,7 @@ static bool
ice_dcbnl_find_app(struct ice_dcbx_cfg *cfg,
struct ice_dcb_app_priority_table *app)
{
int i;
unsigned int i;
for (i = 0; i < cfg->numapps; i++) {
if (app->selector == cfg->app[i].selector &&
@ -746,7 +746,8 @@ static int ice_dcbnl_delapp(struct net_device *netdev, struct dcb_app *app)
{
struct ice_pf *pf = ice_netdev_to_pf(netdev);
struct ice_dcbx_cfg *old_cfg, *new_cfg;
int i, j, ret = 0;
unsigned int i, j;
int ret = 0;
if (pf->dcbx_cap & DCB_CAP_DCBX_LLD_MANAGED)
return -EINVAL;
@ -869,7 +870,7 @@ void ice_dcbnl_set_all(struct ice_vsi *vsi)
struct ice_port_info *pi;
struct dcb_app sapp;
struct ice_pf *pf;
int i;
unsigned int i;
if (!netdev)
return;
@ -941,7 +942,7 @@ ice_dcbnl_flush_apps(struct ice_pf *pf, struct ice_dcbx_cfg *old_cfg,
struct ice_dcbx_cfg *new_cfg)
{
struct ice_vsi *main_vsi = ice_get_main_vsi(pf);
int i;
unsigned int i;
if (!main_vsi)
return;

47
drivers/net/ethernet/intel/ice/ice_ethtool.c
View File

@ -130,6 +130,8 @@ static const struct ice_stats ice_gstrings_pf_stats[] = {
ICE_PF_STAT("illegal_bytes.nic", stats.illegal_bytes),
ICE_PF_STAT("mac_local_faults.nic", stats.mac_local_faults),
ICE_PF_STAT("mac_remote_faults.nic", stats.mac_remote_faults),
ICE_PF_STAT("fdir_sb_match.nic", stats.fd_sb_match),
ICE_PF_STAT("fdir_sb_status.nic", stats.fd_sb_status),
};
static const u32 ice_regs_dump_list[] = {
@ -140,9 +142,6 @@ static const u32 ice_regs_dump_list[] = {
QINT_RQCTL(0),
PFINT_OICR_ENA,
QRX_ITR(0),
PF0INT_ITR_0(0),
PF0INT_ITR_1(0),
PF0INT_ITR_2(0),
};
struct ice_priv_flag {
@ -206,7 +205,7 @@ ice_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
struct ice_pf *pf = np->vsi->back;
struct ice_hw *hw = &pf->hw;
u32 *regs_buf = (u32 *)p;
int i;
unsigned int i;
regs->version = 1;
@ -309,7 +308,7 @@ ice_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom,
*/
static bool ice_active_vfs(struct ice_pf *pf)
{
int i;
unsigned int i;
ice_for_each_vf(pf, i) {
struct ice_vf *vf = &pf->vf[i];
@ -379,7 +378,7 @@ static int ice_reg_pattern_test(struct ice_hw *hw, u32 reg, u32 mask)
0x00000000, 0xFFFFFFFF
};
u32 val, orig_val;
int i;
unsigned int i;
orig_val = rd32(hw, reg);
for (i = 0; i < ARRAY_SIZE(patterns); ++i) {
@ -432,7 +431,7 @@ static u64 ice_reg_test(struct net_device *netdev)
GLINT_ITR(2, 1) - GLINT_ITR(2, 0)},
{GLINT_CTL, 0xffff0001, 1, 0}
};
int i;
unsigned int i;
netdev_dbg(netdev, "Register test\n");
for (i = 0; i < ARRAY_SIZE(ice_reg_list); ++i) {
@ -2535,6 +2534,10 @@ static int ice_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
struct ice_vsi *vsi = np->vsi;
switch (cmd->cmd) {
case ETHTOOL_SRXCLSRLINS:
return ice_add_fdir_ethtool(vsi, cmd);
case ETHTOOL_SRXCLSRLDEL:
return ice_del_fdir_ethtool(vsi, cmd);
case ETHTOOL_SRXFH:
return ice_set_rss_hash_opt(vsi, cmd);
default:
@ -2558,12 +2561,27 @@ ice_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
struct ice_netdev_priv *np = netdev_priv(netdev);
struct ice_vsi *vsi = np->vsi;
int ret = -EOPNOTSUPP;
struct ice_hw *hw;
hw = &vsi->back->hw;
switch (cmd->cmd) {
case ETHTOOL_GRXRINGS:
cmd->data = vsi->rss_size;
ret = 0;
break;
case ETHTOOL_GRXCLSRLCNT:
cmd->rule_cnt = hw->fdir_active_fltr;
/* report total rule count */
cmd->data = ice_get_fdir_cnt_all(hw);
ret = 0;
break;
case ETHTOOL_GRXCLSRULE:
ret = ice_get_ethtool_fdir_entry(hw, cmd);
break;
case ETHTOOL_GRXCLSRLALL:
ret = ice_get_fdir_fltr_ids(hw, cmd, (u32 *)rule_locs);
break;
case ETHTOOL_GRXFH:
ice_get_rss_hash_opt(vsi, cmd);
ret = 0;
@ -3184,6 +3202,10 @@ ice_get_channels(struct net_device *dev, struct ethtool_channels *ch)
ch->combined_count = ice_get_combined_cnt(vsi);
ch->rx_count = vsi->num_rxq - ch->combined_count;
ch->tx_count = vsi->num_txq - ch->combined_count;
/* report other queues */
ch->other_count = test_bit(ICE_FLAG_FD_ENA, pf->flags) ? 1 : 0;
ch->max_other = ch->other_count;
}
/**
@ -3229,7 +3251,7 @@ static int ice_vsi_set_dflt_rss_lut(struct ice_vsi *vsi, int req_rss_size)
if (status) {
dev_err(dev, "Cannot set RSS lut, err %s aq_err %s\n",
ice_stat_str(status),
ice_aq_str(hw->adminq.rq_last_status));
ice_aq_str(hw->adminq.sq_last_status));
err = -EIO;
}
@ -3256,9 +3278,14 @@ static int ice_set_channels(struct net_device *dev, struct ethtool_channels *ch)
return -EOPNOTSUPP;
}
/* do not support changing other_count */
if (ch->other_count)
if (ch->other_count != (test_bit(ICE_FLAG_FD_ENA, pf->flags) ? 1U : 0U))
return -EINVAL;
if (test_bit(ICE_FLAG_FD_ENA, pf->flags) && pf->hw.fdir_active_fltr) {
netdev_err(dev, "Cannot set channels when Flow Director filters are active\n");
return -EOPNOTSUPP;
}
curr_combined = ice_get_combined_cnt(vsi);
/* these checks are for cases where user didn't specify a particular
@ -3732,10 +3759,10 @@ ice_get_module_eeprom(struct net_device *netdev,
struct ice_hw *hw = &pf->hw;
enum ice_status status;
bool is_sfp = false;
unsigned int i;
u16 offset = 0;
u8 value = 0;
u8 page = 0;
int i;
status = ice_aq_sff_eeprom(hw, 0, addr, offset, page, 0,
&value, 1, 0, NULL);

1672
drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c Normal file
View File

File diff suppressed because it is too large Load Diff

840
drivers/net/ethernet/intel/ice/ice_fdir.c Normal file
View File

@ -0,0 +1,840 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2018-2020, Intel Corporation. */
#include "ice_common.h"
/* These are training packet headers used to program flow director filters. */
static const u8 ice_fdir_tcpv4_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00,
0x20, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 ice_fdir_udpv4_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x1C, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00,
};
static const u8 ice_fdir_sctpv4_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x20, 0x00, 0x00, 0x40, 0x00, 0x40, 0x84,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_ipv4_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x14, 0x00, 0x00, 0x40, 0x00, 0x40, 0x10,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00
};
static const u8 ice_fdir_tcpv6_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
0x00, 0x00, 0x00, 0x14, 0x06, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x50, 0x00, 0x20, 0x00, 0x00, 0x00,
0x00, 0x00,
};
static const u8 ice_fdir_udpv6_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
0x00, 0x00, 0x00, 0x08, 0x11, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
};
static const u8 ice_fdir_sctpv6_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
0x00, 0x00, 0x00, 0x0C, 0x84, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00,
};
static const u8 ice_fdir_ipv6_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00,
0x00, 0x00, 0x00, 0x00, 0x3B, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_tcp4_tun_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x5a, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00,
0x45, 0x00, 0x00, 0x28, 0x00, 0x00, 0x40, 0x00,
0x40, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x50, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_udp4_tun_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x4e, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00,
0x45, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x40, 0x00,
0x40, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_sctp4_tun_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x52, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00,
0x45, 0x00, 0x00, 0x20, 0x00, 0x01, 0x00, 0x00,
0x40, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_ip4_tun_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x46, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00,
0x45, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00,
0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_tcp6_tun_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x6e, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, 0x00, 0x14, 0x06, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_udp6_tun_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x62, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x11, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_sctp6_tun_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x66, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x84, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
static const u8 ice_fdir_ip6_tun_pkt[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
0x00, 0x5a, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd,
0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
/* Flow Director no-op training packet table */
static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
{
ICE_FLTR_PTYPE_NONF_IPV4_TCP,
sizeof(ice_fdir_tcpv4_pkt), ice_fdir_tcpv4_pkt,
sizeof(ice_fdir_tcp4_tun_pkt), ice_fdir_tcp4_tun_pkt,
},
{
ICE_FLTR_PTYPE_NONF_IPV4_UDP,
sizeof(ice_fdir_udpv4_pkt), ice_fdir_udpv4_pkt,
sizeof(ice_fdir_udp4_tun_pkt), ice_fdir_udp4_tun_pkt,
},
{
ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
sizeof(ice_fdir_sctpv4_pkt), ice_fdir_sctpv4_pkt,
sizeof(ice_fdir_sctp4_tun_pkt), ice_fdir_sctp4_tun_pkt,
},
{
ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
sizeof(ice_fdir_ipv4_pkt), ice_fdir_ipv4_pkt,
sizeof(ice_fdir_ip4_tun_pkt), ice_fdir_ip4_tun_pkt,
},
{
ICE_FLTR_PTYPE_NONF_IPV6_TCP,
sizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt,
sizeof(ice_fdir_tcp6_tun_pkt), ice_fdir_tcp6_tun_pkt,
},
{
ICE_FLTR_PTYPE_NONF_IPV6_UDP,
sizeof(ice_fdir_udpv6_pkt), ice_fdir_udpv6_pkt,
sizeof(ice_fdir_udp6_tun_pkt), ice_fdir_udp6_tun_pkt,
},
{
ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
sizeof(ice_fdir_sctpv6_pkt), ice_fdir_sctpv6_pkt,
sizeof(ice_fdir_sctp6_tun_pkt), ice_fdir_sctp6_tun_pkt,
},
{
ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
sizeof(ice_fdir_ipv6_pkt), ice_fdir_ipv6_pkt,
sizeof(ice_fdir_ip6_tun_pkt), ice_fdir_ip6_tun_pkt,
},
};
#define ICE_FDIR_NUM_PKT ARRAY_SIZE(ice_fdir_pkt)
/**
* ice_set_dflt_val_fd_desc
* @fd_fltr_ctx: pointer to fd filter descriptor
*/
static void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)
{
fd_fltr_ctx->comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO;
fd_fltr_ctx->comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL;
fd_fltr_ctx->fd_space = ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST;
fd_fltr_ctx->cnt_ena = ICE_FXD_FLTR_QW0_STAT_ENA_PKTS;
fd_fltr_ctx->evict_ena = ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE;
fd_fltr_ctx->toq = ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX;
fd_fltr_ctx->toq_prio = ICE_FXD_FLTR_QW0_TO_Q_PRIO1;
fd_fltr_ctx->dpu_recipe = ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT;
fd_fltr_ctx->drop = ICE_FXD_FLTR_QW0_DROP_NO;
fd_fltr_ctx->flex_prio = ICE_FXD_FLTR_QW0_FLEX_PRI_NONE;
fd_fltr_ctx->flex_mdid = ICE_FXD_FLTR_QW0_FLEX_MDID0;
fd_fltr_ctx->flex_val = ICE_FXD_FLTR_QW0_FLEX_VAL0;
fd_fltr_ctx->dtype = ICE_TX_DESC_DTYPE_FLTR_PROG;
fd_fltr_ctx->desc_prof_prio = ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO;
fd_fltr_ctx->desc_prof = ICE_FXD_FLTR_QW1_PROF_ZERO;
fd_fltr_ctx->swap = ICE_FXD_FLTR_QW1_SWAP_SET;
fd_fltr_ctx->fdid_prio = ICE_FXD_FLTR_QW1_FDID_PRI_ONE;
fd_fltr_ctx->fdid_mdid = ICE_FXD_FLTR_QW1_FDID_MDID_FD;
fd_fltr_ctx->fdid = ICE_FXD_FLTR_QW1_FDID_ZERO;
}
/**
* ice_set_fd_desc_val
* @ctx: pointer to fd filter descriptor context
* @fdir_desc: populated with fd filter descriptor values
*/
static void
ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *ctx,
struct ice_fltr_desc *fdir_desc)
{
u64 qword;
/* prep QW0 of FD filter programming desc */
qword = ((u64)ctx->qindex << ICE_FXD_FLTR_QW0_QINDEX_S) &
ICE_FXD_FLTR_QW0_QINDEX_M;
qword |= ((u64)ctx->comp_q << ICE_FXD_FLTR_QW0_COMP_Q_S) &
ICE_FXD_FLTR_QW0_COMP_Q_M;
qword |= ((u64)ctx->comp_report << ICE_FXD_FLTR_QW0_COMP_REPORT_S) &
ICE_FXD_FLTR_QW0_COMP_REPORT_M;
qword |= ((u64)ctx->fd_space << ICE_FXD_FLTR_QW0_FD_SPACE_S) &
ICE_FXD_FLTR_QW0_FD_SPACE_M;
qword |= ((u64)ctx->cnt_index << ICE_FXD_FLTR_QW0_STAT_CNT_S) &
ICE_FXD_FLTR_QW0_STAT_CNT_M;
qword |= ((u64)ctx->cnt_ena << ICE_FXD_FLTR_QW0_STAT_ENA_S) &
ICE_FXD_FLTR_QW0_STAT_ENA_M;
qword |= ((u64)ctx->evict_ena << ICE_FXD_FLTR_QW0_EVICT_ENA_S) &
ICE_FXD_FLTR_QW0_EVICT_ENA_M;
qword |= ((u64)ctx->toq << ICE_FXD_FLTR_QW0_TO_Q_S) &
ICE_FXD_FLTR_QW0_TO_Q_M;
qword |= ((u64)ctx->toq_prio << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) &
ICE_FXD_FLTR_QW0_TO_Q_PRI_M;
qword |= ((u64)ctx->dpu_recipe << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) &
ICE_FXD_FLTR_QW0_DPU_RECIPE_M;
qword |= ((u64)ctx->drop << ICE_FXD_FLTR_QW0_DROP_S) &
ICE_FXD_FLTR_QW0_DROP_M;
qword |= ((u64)ctx->flex_prio << ICE_FXD_FLTR_QW0_FLEX_PRI_S) &
ICE_FXD_FLTR_QW0_FLEX_PRI_M;
qword |= ((u64)ctx->flex_mdid << ICE_FXD_FLTR_QW0_FLEX_MDID_S) &
ICE_FXD_FLTR_QW0_FLEX_MDID_M;
qword |= ((u64)ctx->flex_val << ICE_FXD_FLTR_QW0_FLEX_VAL_S) &
ICE_FXD_FLTR_QW0_FLEX_VAL_M;
fdir_desc->qidx_compq_space_stat = cpu_to_le64(qword);
/* prep QW1 of FD filter programming desc */
qword = ((u64)ctx->dtype << ICE_FXD_FLTR_QW1_DTYPE_S) &
ICE_FXD_FLTR_QW1_DTYPE_M;
qword |= ((u64)ctx->pcmd << ICE_FXD_FLTR_QW1_PCMD_S) &
ICE_FXD_FLTR_QW1_PCMD_M;
qword |= ((u64)ctx->desc_prof_prio << ICE_FXD_FLTR_QW1_PROF_PRI_S) &
ICE_FXD_FLTR_QW1_PROF_PRI_M;
qword |= ((u64)ctx->desc_prof << ICE_FXD_FLTR_QW1_PROF_S) &
ICE_FXD_FLTR_QW1_PROF_M;
qword |= ((u64)ctx->fd_vsi << ICE_FXD_FLTR_QW1_FD_VSI_S) &
ICE_FXD_FLTR_QW1_FD_VSI_M;
qword |= ((u64)ctx->swap << ICE_FXD_FLTR_QW1_SWAP_S) &
ICE_FXD_FLTR_QW1_SWAP_M;
qword |= ((u64)ctx->fdid_prio << ICE_FXD_FLTR_QW1_FDID_PRI_S) &
ICE_FXD_FLTR_QW1_FDID_PRI_M;
qword |= ((u64)ctx->fdid_mdid << ICE_FXD_FLTR_QW1_FDID_MDID_S) &
ICE_FXD_FLTR_QW1_FDID_MDID_M;
qword |= ((u64)ctx->fdid << ICE_FXD_FLTR_QW1_FDID_S) &
ICE_FXD_FLTR_QW1_FDID_M;
fdir_desc->dtype_cmd_vsi_fdid = cpu_to_le64(qword);
}
/**
* ice_fdir_get_prgm_desc - set a fdir descriptor from a fdir filter struct
* @hw: pointer to the hardware structure
* @input: filter
* @fdesc: filter descriptor
* @add: if add is true, this is an add operation, false implies delete
*/
void
ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input,
struct ice_fltr_desc *fdesc, bool add)
{
struct ice_fd_fltr_desc_ctx fdir_fltr_ctx = { 0 };
/* set default context info */
ice_set_dflt_val_fd_desc(&fdir_fltr_ctx);
/* change sideband filtering values */
fdir_fltr_ctx.fdid = input->fltr_id;
if (input->dest_ctl == ICE_FLTR_PRGM_DESC_DEST_DROP_PKT) {
fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_YES;
fdir_fltr_ctx.qindex = 0;
} else {
fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_NO;
fdir_fltr_ctx.qindex = input->q_index;
}
fdir_fltr_ctx.cnt_ena = ICE_FXD_FLTR_QW0_STAT_ENA_PKTS;
fdir_fltr_ctx.cnt_index = input->cnt_index;
fdir_fltr_ctx.fd_vsi = ice_get_hw_vsi_num(hw, input->dest_vsi);
fdir_fltr_ctx.evict_ena = ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE;
fdir_fltr_ctx.toq_prio = 3;
fdir_fltr_ctx.pcmd = add ? ICE_FXD_FLTR_QW1_PCMD_ADD :
ICE_FXD_FLTR_QW1_PCMD_REMOVE;
fdir_fltr_ctx.swap = ICE_FXD_FLTR_QW1_SWAP_NOT_SET;
fdir_fltr_ctx.comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO;
fdir_fltr_ctx.comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL;
fdir_fltr_ctx.fdid_prio = 3;
fdir_fltr_ctx.desc_prof = 1;
fdir_fltr_ctx.desc_prof_prio = 3;
ice_set_fd_desc_val(&fdir_fltr_ctx, fdesc);
}
/**
* ice_alloc_fd_res_cntr - obtain counter resource for FD type
* @hw: pointer to the hardware structure
* @cntr_id: returns counter index
*/
enum ice_status ice_alloc_fd_res_cntr(struct ice_hw *hw, u16 *cntr_id)
{
return ice_alloc_res_cntr(hw, ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK,
ICE_AQC_RES_TYPE_FLAG_DEDICATED, 1, cntr_id);
}
/**
* ice_free_fd_res_cntr - Free counter resource for FD type
* @hw: pointer to the hardware structure
* @cntr_id: counter index to be freed
*/
enum ice_status ice_free_fd_res_cntr(struct ice_hw *hw, u16 cntr_id)
{
return ice_free_res_cntr(hw, ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK,
ICE_AQC_RES_TYPE_FLAG_DEDICATED, 1, cntr_id);
}
/**
* ice_alloc_fd_guar_item - allocate resource for FD guaranteed entries
* @hw: pointer to the hardware structure
* @cntr_id: returns counter index
* @num_fltr: number of filter entries to be allocated
*/
enum ice_status
ice_alloc_fd_guar_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr)
{
return ice_alloc_res_cntr(hw, ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES,
ICE_AQC_RES_TYPE_FLAG_DEDICATED, num_fltr,
cntr_id);
}
/**
* ice_alloc_fd_shrd_item - allocate resource for flow director shared entries
* @hw: pointer to the hardware structure
* @cntr_id: returns counter index
* @num_fltr: number of filter entries to be allocated
*/
enum ice_status
ice_alloc_fd_shrd_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr)
{
return ice_alloc_res_cntr(hw, ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES,
ICE_AQC_RES_TYPE_FLAG_DEDICATED, num_fltr,
cntr_id);
}
/**
* ice_get_fdir_cnt_all - get the number of Flow Director filters
* @hw: hardware data structure
*
* Returns the number of filters available on device
*/
int ice_get_fdir_cnt_all(struct ice_hw *hw)
{
return hw->func_caps.fd_fltr_guar + hw->func_caps.fd_fltr_best_effort;
}
/**
* ice_pkt_insert_ipv6_addr - insert a be32 IPv6 address into a memory buffer
* @pkt: packet buffer
* @offset: offset into buffer
* @addr: IPv6 address to convert and insert into pkt at offset
*/
static void ice_pkt_insert_ipv6_addr(u8 *pkt, int offset, __be32 *addr)
{
int idx;
for (idx = 0; idx < ICE_IPV6_ADDR_LEN_AS_U32; idx++)
memcpy(pkt + offset + idx * sizeof(*addr), &addr[idx],
sizeof(*addr));
}
/**
* ice_pkt_insert_u16 - insert a be16 value into a memory buffer
* @pkt: packet buffer
* @offset: offset into buffer
* @data: 16 bit value to convert and insert into pkt at offset
*/
static void ice_pkt_insert_u16(u8 *pkt, int offset, __be16 data)
{
memcpy(pkt + offset, &data, sizeof(data));
}
/**
* ice_pkt_insert_u32 - insert a be32 value into a memory buffer
* @pkt: packet buffer
* @offset: offset into buffer
* @data: 32 bit value to convert and insert into pkt at offset
*/
static void ice_pkt_insert_u32(u8 *pkt, int offset, __be32 data)
{
memcpy(pkt + offset, &data, sizeof(data));
}
/**
* ice_fdir_get_gen_prgm_pkt - generate a training packet
* @hw: pointer to the hardware structure
* @input: flow director filter data structure
* @pkt: pointer to return filter packet
* @frag: generate a fragment packet
* @tun: true implies generate a tunnel packet
*/
enum ice_status
ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
u8 *pkt, bool frag, bool tun)
{
enum ice_fltr_ptype flow;
u16 tnl_port;
u8 *loc;
u16 idx;
if (input->flow_type == ICE_FLTR_PTYPE_NONF_IPV4_OTHER) {
switch (input->ip.v4.proto) {
case IPPROTO_TCP:
flow = ICE_FLTR_PTYPE_NONF_IPV4_TCP;
break;
case IPPROTO_UDP:
flow = ICE_FLTR_PTYPE_NONF_IPV4_UDP;
break;
case IPPROTO_SCTP:
flow = ICE_FLTR_PTYPE_NONF_IPV4_SCTP;
break;
case IPPROTO_IP:
flow = ICE_FLTR_PTYPE_NONF_IPV4_OTHER;
break;
default:
return ICE_ERR_PARAM;
}
} else if (input->flow_type == ICE_FLTR_PTYPE_NONF_IPV6_OTHER) {
switch (input->ip.v6.proto) {
case IPPROTO_TCP:
flow = ICE_FLTR_PTYPE_NONF_IPV6_TCP;
break;
case IPPROTO_UDP:
flow = ICE_FLTR_PTYPE_NONF_IPV6_UDP;
break;
case IPPROTO_SCTP:
flow = ICE_FLTR_PTYPE_NONF_IPV6_SCTP;
break;
case IPPROTO_IP:
flow = ICE_FLTR_PTYPE_NONF_IPV6_OTHER;
break;
default:
return ICE_ERR_PARAM;
}
} else {
flow = input->flow_type;
}
for (idx = 0; idx < ICE_FDIR_NUM_PKT; idx++)
if (ice_fdir_pkt[idx].flow == flow)
break;
if (idx == ICE_FDIR_NUM_PKT)
return ICE_ERR_PARAM;
if (!tun) {
memcpy(pkt, ice_fdir_pkt[idx].pkt, ice_fdir_pkt[idx].pkt_len);
loc = pkt;
} else {
if (!ice_get_open_tunnel_port(hw, TNL_ALL, &tnl_port))
return ICE_ERR_DOES_NOT_EXIST;
if (!ice_fdir_pkt[idx].tun_pkt)
return ICE_ERR_PARAM;
memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
ice_fdir_pkt[idx].tun_pkt_len);
ice_pkt_insert_u16(pkt, ICE_IPV4_UDP_DST_PORT_OFFSET,
htons(tnl_port));
loc = &pkt[ICE_FDIR_TUN_PKT_OFF];
}
/* Reverse the src and dst, since the HW expects them to be from Tx
* perspective. The input from user is from Rx filter perspective.
*/
switch (flow) {
case ICE_FLTR_PTYPE_NONF_IPV4_TCP:
ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
input->ip.v4.src_ip);
ice_pkt_insert_u16(loc, ICE_IPV4_TCP_DST_PORT_OFFSET,
input->ip.v4.src_port);
ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
input->ip.v4.dst_ip);
ice_pkt_insert_u16(loc, ICE_IPV4_TCP_SRC_PORT_OFFSET,
input->ip.v4.dst_port);
if (frag)
loc[20] = ICE_FDIR_IPV4_PKT_FLAG_DF;
break;
case ICE_FLTR_PTYPE_NONF_IPV4_UDP:
ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
input->ip.v4.src_ip);
ice_pkt_insert_u16(loc, ICE_IPV4_UDP_DST_PORT_OFFSET,
input->ip.v4.src_port);
ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
input->ip.v4.dst_ip);
ice_pkt_insert_u16(loc, ICE_IPV4_UDP_SRC_PORT_OFFSET,
input->ip.v4.dst_port);
break;
case ICE_FLTR_PTYPE_NONF_IPV4_SCTP:
ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
input->ip.v4.src_ip);
ice_pkt_insert_u16(loc, ICE_IPV4_SCTP_DST_PORT_OFFSET,
input->ip.v4.src_port);
ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
input->ip.v4.dst_ip);
ice_pkt_insert_u16(loc, ICE_IPV4_SCTP_SRC_PORT_OFFSET,
input->ip.v4.dst_port);
break;
case ICE_FLTR_PTYPE_NONF_IPV4_OTHER:
ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
input->ip.v4.src_ip);
ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
input->ip.v4.dst_ip);
ice_pkt_insert_u16(loc, ICE_IPV4_PROTO_OFFSET, 0);
break;
case ICE_FLTR_PTYPE_NONF_IPV6_TCP:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET,
input->ip.v6.dst_ip);
ice_pkt_insert_u16(loc, ICE_IPV6_TCP_DST_PORT_OFFSET,
input->ip.v6.src_port);
ice_pkt_insert_u16(loc, ICE_IPV6_TCP_SRC_PORT_OFFSET,
input->ip.v6.dst_port);
break;
case ICE_FLTR_PTYPE_NONF_IPV6_UDP:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET,
input->ip.v6.dst_ip);
ice_pkt_insert_u16(loc, ICE_IPV6_UDP_DST_PORT_OFFSET,
input->ip.v6.src_port);
ice_pkt_insert_u16(loc, ICE_IPV6_UDP_SRC_PORT_OFFSET,
input->ip.v6.dst_port);
break;
case ICE_FLTR_PTYPE_NONF_IPV6_SCTP:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET,
input->ip.v6.dst_ip);
ice_pkt_insert_u16(loc, ICE_IPV6_SCTP_DST_PORT_OFFSET,
input->ip.v6.src_port);
ice_pkt_insert_u16(loc, ICE_IPV6_SCTP_SRC_PORT_OFFSET,
input->ip.v6.dst_port);
break;
case ICE_FLTR_PTYPE_NONF_IPV6_OTHER:
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
input->ip.v6.src_ip);
ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_SRC_ADDR_OFFSET,
input->ip.v6.dst_ip);
break;
default:
return ICE_ERR_PARAM;
}
if (input->flex_fltr)
ice_pkt_insert_u16(loc, input->flex_offset, input->flex_word);
return 0;
}
/**
* ice_fdir_has_frag - does flow type have 2 ptypes
* @flow: flow ptype
*
* returns true is there is a fragment packet for this ptype
*/
bool ice_fdir_has_frag(enum ice_fltr_ptype flow)
{
if (flow == ICE_FLTR_PTYPE_NONF_IPV4_OTHER)
return true;
else
return false;
}
/**
* ice_fdir_find_by_idx - find filter with idx
* @hw: pointer to hardware structure
* @fltr_idx: index to find.
*
* Returns pointer to filter if found or null
*/
struct ice_fdir_fltr *
ice_fdir_find_fltr_by_idx(struct ice_hw *hw, u32 fltr_idx)
{
struct ice_fdir_fltr *rule;
list_for_each_entry(rule, &hw->fdir_list_head, fltr_node) {
/* rule ID found in the list */
if (fltr_idx == rule->fltr_id)
return rule;
if (fltr_idx < rule->fltr_id)
break;
}
return NULL;
}
/**
* ice_fdir_list_add_fltr - add a new node to the flow director filter list
* @hw: hardware structure
* @fltr: filter node to add to structure
*/
void ice_fdir_list_add_fltr(struct ice_hw *hw, struct ice_fdir_fltr *fltr)
{
struct ice_fdir_fltr *rule, *parent = NULL;
list_for_each_entry(rule, &hw->fdir_list_head, fltr_node) {
/* rule ID found or pass its spot in the list */
if (rule->fltr_id >= fltr->fltr_id)
break;
parent = rule;
}
if (parent)
list_add(&fltr->fltr_node, &parent->fltr_node);
else
list_add(&fltr->fltr_node, &hw->fdir_list_head);
}
/**
* ice_fdir_update_cntrs - increment / decrement filter counter
* @hw: pointer to hardware structure
* @flow: filter flow type
* @add: true implies filters added
*/
void
ice_fdir_update_cntrs(struct ice_hw *hw, enum ice_fltr_ptype flow, bool add)
{
int incr;
incr = add ? 1 : -1;
hw->fdir_active_fltr += incr;
if (flow == ICE_FLTR_PTYPE_NONF_NONE || flow >= ICE_FLTR_PTYPE_MAX)
ice_debug(hw, ICE_DBG_SW, "Unknown filter type %d\n", flow);
else
hw->fdir_fltr_cnt[flow] += incr;
}
/**
* ice_cmp_ipv6_addr - compare 2 IP v6 addresses
* @a: IP v6 address
* @b: IP v6 address
*
* Returns 0 on equal, returns non-0 if different
*/
static int ice_cmp_ipv6_addr(__be32 *a, __be32 *b)
{
return memcmp(a, b, 4 * sizeof(__be32));
}
/**
* ice_fdir_comp_rules - compare 2 filters
* @a: a Flow Director filter data structure
* @b: a Flow Director filter data structure
* @v6: bool true if v6 filter
*
* Returns true if the filters match
*/
static bool
ice_fdir_comp_rules(struct ice_fdir_fltr *a, struct ice_fdir_fltr *b, bool v6)
{
enum ice_fltr_ptype flow_type = a->flow_type;
/* The calling function already checks that the two filters have the
* same flow_type.
*/
if (!v6) {
if (flow_type == ICE_FLTR_PTYPE_NONF_IPV4_TCP ||
flow_type == ICE_FLTR_PTYPE_NONF_IPV4_UDP ||
flow_type == ICE_FLTR_PTYPE_NONF_IPV4_SCTP) {
if (a->ip.v4.dst_ip == b->ip.v4.dst_ip &&
a->ip.v4.src_ip == b->ip.v4.src_ip &&
a->ip.v4.dst_port == b->ip.v4.dst_port &&
a->ip.v4.src_port == b->ip.v4.src_port)
return true;
} else if (flow_type == ICE_FLTR_PTYPE_NONF_IPV4_OTHER) {
if (a->ip.v4.dst_ip == b->ip.v4.dst_ip &&
a->ip.v4.src_ip == b->ip.v4.src_ip &&
a->ip.v4.l4_header == b->ip.v4.l4_header &&
a->ip.v4.proto == b->ip.v4.proto &&
a->ip.v4.ip_ver == b->ip.v4.ip_ver &&
a->ip.v4.tos == b->ip.v4.tos)
return true;
}
} else {
if (flow_type == ICE_FLTR_PTYPE_NONF_IPV6_UDP ||
flow_type == ICE_FLTR_PTYPE_NONF_IPV6_TCP ||
flow_type == ICE_FLTR_PTYPE_NONF_IPV6_SCTP) {
if (a->ip.v6.dst_port == b->ip.v6.dst_port &&
a->ip.v6.src_port == b->ip.v6.src_port &&
!ice_cmp_ipv6_addr(a->ip.v6.dst_ip,
b->ip.v6.dst_ip) &&
!ice_cmp_ipv6_addr(a->ip.v6.src_ip,
b->ip.v6.src_ip))
return true;
} else if (flow_type == ICE_FLTR_PTYPE_NONF_IPV6_OTHER) {
if (a->ip.v6.dst_port == b->ip.v6.dst_port &&
a->ip.v6.src_port == b->ip.v6.src_port)
return true;
}
}
return false;
}
/**
* ice_fdir_is_dup_fltr - test if filter is already in list for PF
* @hw: hardware data structure
* @input: Flow Director filter data structure
*
* Returns true if the filter is found in the list
*/
bool ice_fdir_is_dup_fltr(struct ice_hw *hw, struct ice_fdir_fltr *input)
{
struct ice_fdir_fltr *rule;
bool ret = false;
list_for_each_entry(rule, &hw->fdir_list_head, fltr_node) {
enum ice_fltr_ptype flow_type;
if (rule->flow_type != input->flow_type)
continue;
flow_type = input->flow_type;
if (flow_type == ICE_FLTR_PTYPE_NONF_IPV4_TCP ||
flow_type == ICE_FLTR_PTYPE_NONF_IPV4_UDP ||
flow_type == ICE_FLTR_PTYPE_NONF_IPV4_SCTP ||
flow_type == ICE_FLTR_PTYPE_NONF_IPV4_OTHER)
ret = ice_fdir_comp_rules(rule, input, false);
else
ret = ice_fdir_comp_rules(rule, input, true);
if (ret) {
if (rule->fltr_id == input->fltr_id &&
rule->q_index != input->q_index)
ret = false;
else
break;
}
}
return ret;
}

166
drivers/net/ethernet/intel/ice/ice_fdir.h Normal file
View File

@ -0,0 +1,166 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2018-2020, Intel Corporation. */
#ifndef _ICE_FDIR_H_
#define _ICE_FDIR_H_
#define ICE_FDIR_TUN_PKT_OFF 50
#define ICE_FDIR_MAX_RAW_PKT_SIZE (512 + ICE_FDIR_TUN_PKT_OFF)
/* macros for offsets into packets for flow director programming */
#define ICE_IPV4_SRC_ADDR_OFFSET 26
#define ICE_IPV4_DST_ADDR_OFFSET 30
#define ICE_IPV4_TCP_SRC_PORT_OFFSET 34
#define ICE_IPV4_TCP_DST_PORT_OFFSET 36
#define ICE_IPV4_UDP_SRC_PORT_OFFSET 34
#define ICE_IPV4_UDP_DST_PORT_OFFSET 36
#define ICE_IPV4_SCTP_SRC_PORT_OFFSET 34
#define ICE_IPV4_SCTP_DST_PORT_OFFSET 36
#define ICE_IPV4_PROTO_OFFSET 23
#define ICE_IPV6_SRC_ADDR_OFFSET 22
#define ICE_IPV6_DST_ADDR_OFFSET 38
#define ICE_IPV6_TCP_SRC_PORT_OFFSET 54
#define ICE_IPV6_TCP_DST_PORT_OFFSET 56
#define ICE_IPV6_UDP_SRC_PORT_OFFSET 54
#define ICE_IPV6_UDP_DST_PORT_OFFSET 56
#define ICE_IPV6_SCTP_SRC_PORT_OFFSET 54
#define ICE_IPV6_SCTP_DST_PORT_OFFSET 56
/* IP v4 has 2 flag bits that enable fragment processing: DF and MF. DF
* requests that the packet not be fragmented. MF indicates that a packet has
* been fragmented.
*/
#define ICE_FDIR_IPV4_PKT_FLAG_DF 0x20
enum ice_fltr_prgm_desc_dest {
ICE_FLTR_PRGM_DESC_DEST_DROP_PKT,
ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_QINDEX,
};
enum ice_fltr_prgm_desc_fd_status {
ICE_FLTR_PRGM_DESC_FD_STATUS_NONE,
ICE_FLTR_PRGM_DESC_FD_STATUS_FD_ID,
};
/* Flow Director (FD) Filter Programming descriptor */
struct ice_fd_fltr_desc_ctx {
u32 fdid;
u16 qindex;
u16 cnt_index;
u16 fd_vsi;
u16 flex_val;
u8 comp_q;
u8 comp_report;
u8 fd_space;
u8 cnt_ena;
u8 evict_ena;
u8 toq;
u8 toq_prio;
u8 dpu_recipe;
u8 drop;
u8 flex_prio;
u8 flex_mdid;
u8 dtype;
u8 pcmd;
u8 desc_prof_prio;
u8 desc_prof;
u8 swap;
u8 fdid_prio;
u8 fdid_mdid;
};
#define ICE_FLTR_PRGM_FLEX_WORD_SIZE sizeof(__be16)
struct ice_rx_flow_userdef {
u16 flex_word;
u16 flex_offset;
u16 flex_fltr;
};
struct ice_fdir_v4 {
__be32 dst_ip;
__be32 src_ip;
__be16 dst_port;
__be16 src_port;
__be32 l4_header;
__be32 sec_parm_idx; /* security parameter index */
u8 tos;
u8 ip_ver;
u8 proto;
};
#define ICE_IPV6_ADDR_LEN_AS_U32 4
struct ice_fdir_v6 {
__be32 dst_ip[ICE_IPV6_ADDR_LEN_AS_U32];
__be32 src_ip[ICE_IPV6_ADDR_LEN_AS_U32];
__be16 dst_port;
__be16 src_port;
__be32 l4_header; /* next header */
__be32 sec_parm_idx; /* security parameter index */
u8 tc;
u8 proto;
};
struct ice_fdir_extra {
u8 dst_mac[ETH_ALEN]; /* dest MAC address */
u32 usr_def[2]; /* user data */
__be16 vlan_type; /* VLAN ethertype */
__be16 vlan_tag; /* VLAN tag info */
};
struct ice_fdir_fltr {
struct list_head fltr_node;
enum ice_fltr_ptype flow_type;
union {
struct ice_fdir_v4 v4;
struct ice_fdir_v6 v6;
} ip, mask;
struct ice_fdir_extra ext_data;
struct ice_fdir_extra ext_mask;
/* flex byte filter data */
__be16 flex_word;
u16 flex_offset;
u16 flex_fltr;
/* filter control */
u16 q_index;
u16 dest_vsi;
u8 dest_ctl;
u8 fltr_status;
u16 cnt_index;
u32 fltr_id;
};
/* Dummy packet filter definition structure */
struct ice_fdir_base_pkt {
enum ice_fltr_ptype flow;
u16 pkt_len;
const u8 *pkt;
u16 tun_pkt_len;
const u8 *tun_pkt;
};
enum ice_status ice_alloc_fd_res_cntr(struct ice_hw *hw, u16 *cntr_id);
enum ice_status ice_free_fd_res_cntr(struct ice_hw *hw, u16 cntr_id);
enum ice_status
ice_alloc_fd_guar_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr);
enum ice_status
ice_alloc_fd_shrd_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr);
void
ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input,
struct ice_fltr_desc *fdesc, bool add);
enum ice_status
ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
u8 *pkt, bool frag, bool tun);
int ice_get_fdir_cnt_all(struct ice_hw *hw);
bool ice_fdir_is_dup_fltr(struct ice_hw *hw, struct ice_fdir_fltr *input);
bool ice_fdir_has_frag(enum ice_fltr_ptype flow);
struct ice_fdir_fltr *
ice_fdir_find_fltr_by_idx(struct ice_hw *hw, u32 fltr_idx);
void
ice_fdir_update_cntrs(struct ice_hw *hw, enum ice_fltr_ptype flow, bool add);
void ice_fdir_list_add_fltr(struct ice_hw *hw, struct ice_fdir_fltr *input);
#endif /* _ICE_FDIR_H_ */

376
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
View File

@ -864,8 +864,9 @@ ice_find_seg_in_pkg(struct ice_hw *hw, u32 seg_type,
u32 i;
ice_debug(hw, ICE_DBG_PKG, "Package format version: %d.%d.%d.%d\n",
pkg_hdr->format_ver.major, pkg_hdr->format_ver.minor,
pkg_hdr->format_ver.update, pkg_hdr->format_ver.draft);
pkg_hdr->pkg_format_ver.major, pkg_hdr->pkg_format_ver.minor,
pkg_hdr->pkg_format_ver.update,
pkg_hdr->pkg_format_ver.draft);
/* Search all package segments for the requested segment type */
for (i = 0; i < le32_to_cpu(pkg_hdr->seg_count); i++) {
@ -1035,13 +1036,15 @@ ice_download_pkg(struct ice_hw *hw, struct ice_seg *ice_seg)
{
struct ice_buf_table *ice_buf_tbl;
ice_debug(hw, ICE_DBG_PKG, "Segment version: %d.%d.%d.%d\n",
ice_seg->hdr.seg_ver.major, ice_seg->hdr.seg_ver.minor,
ice_seg->hdr.seg_ver.update, ice_seg->hdr.seg_ver.draft);
ice_debug(hw, ICE_DBG_PKG, "Segment format version: %d.%d.%d.%d\n",
ice_seg->hdr.seg_format_ver.major,
ice_seg->hdr.seg_format_ver.minor,
ice_seg->hdr.seg_format_ver.update,
ice_seg->hdr.seg_format_ver.draft);
ice_debug(hw, ICE_DBG_PKG, "Seg: type 0x%X, size %d, name %s\n",
le32_to_cpu(ice_seg->hdr.seg_type),
le32_to_cpu(ice_seg->hdr.seg_size), ice_seg->hdr.seg_name);
le32_to_cpu(ice_seg->hdr.seg_size), ice_seg->hdr.seg_id);
ice_buf_tbl = ice_find_buf_table(ice_seg);
@ -1086,14 +1089,16 @@ ice_init_pkg_info(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr)
seg_hdr = ice_find_seg_in_pkg(hw, SEGMENT_TYPE_ICE, pkg_hdr);
if (seg_hdr) {
hw->ice_pkg_ver = seg_hdr->seg_ver;
memcpy(hw->ice_pkg_name, seg_hdr->seg_name,
hw->ice_pkg_ver = seg_hdr->seg_format_ver;
memcpy(hw->ice_pkg_name, seg_hdr->seg_id,
sizeof(hw->ice_pkg_name));
ice_debug(hw, ICE_DBG_PKG, "Ice Pkg: %d.%d.%d.%d, %s\n",
seg_hdr->seg_ver.major, seg_hdr->seg_ver.minor,
seg_hdr->seg_ver.update, seg_hdr->seg_ver.draft,
seg_hdr->seg_name);
ice_debug(hw, ICE_DBG_PKG, "Ice Seg: %d.%d.%d.%d, %s\n",
seg_hdr->seg_format_ver.major,
seg_hdr->seg_format_ver.minor,
seg_hdr->seg_format_ver.update,
seg_hdr->seg_format_ver.draft,
seg_hdr->seg_id);
} else {
ice_debug(hw, ICE_DBG_INIT,
"Did not find ice segment in driver package\n");
@ -1134,9 +1139,11 @@ static enum ice_status ice_get_pkg_info(struct ice_hw *hw)
if (pkg_info->pkg_info[i].is_active) {
flags[place++] = 'A';
hw->active_pkg_ver = pkg_info->pkg_info[i].ver;
hw->active_track_id =
le32_to_cpu(pkg_info->pkg_info[i].track_id);
memcpy(hw->active_pkg_name,
pkg_info->pkg_info[i].name,
sizeof(hw->active_pkg_name));
sizeof(pkg_info->pkg_info[i].name));
hw->active_pkg_in_nvm = pkg_info->pkg_info[i].is_in_nvm;
}
if (pkg_info->pkg_info[i].is_active_at_boot)
@ -1176,10 +1183,10 @@ static enum ice_status ice_verify_pkg(struct ice_pkg_hdr *pkg, u32 len)
if (len < sizeof(*pkg))
return ICE_ERR_BUF_TOO_SHORT;
if (pkg->format_ver.major != ICE_PKG_FMT_VER_MAJ ||
pkg->format_ver.minor != ICE_PKG_FMT_VER_MNR ||
pkg->format_ver.update != ICE_PKG_FMT_VER_UPD ||
pkg->format_ver.draft != ICE_PKG_FMT_VER_DFT)
if (pkg->pkg_format_ver.major != ICE_PKG_FMT_VER_MAJ ||
pkg->pkg_format_ver.minor != ICE_PKG_FMT_VER_MNR ||
pkg->pkg_format_ver.update != ICE_PKG_FMT_VER_UPD ||
pkg->pkg_format_ver.draft != ICE_PKG_FMT_VER_DFT)
return ICE_ERR_CFG;
/* pkg must have at least one segment */
@ -1260,6 +1267,68 @@ static enum ice_status ice_chk_pkg_version(struct ice_pkg_ver *pkg_ver)
return 0;
}
/**
* ice_chk_pkg_compat
* @hw: pointer to the hardware structure
* @ospkg: pointer to the package hdr
* @seg: pointer to the package segment hdr
*
* This function checks the package version compatibility with driver and NVM
*/
static enum ice_status
ice_chk_pkg_compat(struct ice_hw *hw, struct ice_pkg_hdr *ospkg,
struct ice_seg **seg)
{
struct ice_aqc_get_pkg_info_resp *pkg;
enum ice_status status;
u16 size;
u32 i;
/* Check package version compatibility */
status = ice_chk_pkg_version(&hw->pkg_ver);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Package version check failed.\n");
return status;
}
/* find ICE segment in given package */
*seg = (struct ice_seg *)ice_find_seg_in_pkg(hw, SEGMENT_TYPE_ICE,
ospkg);
if (!*seg) {
ice_debug(hw, ICE_DBG_INIT, "no ice segment in package.\n");
return ICE_ERR_CFG;
}
/* Check if FW is compatible with the OS package */
size = struct_size(pkg, pkg_info, ICE_PKG_CNT - 1);
pkg = kzalloc(size, GFP_KERNEL);
if (!pkg)
return ICE_ERR_NO_MEMORY;
status = ice_aq_get_pkg_info_list(hw, pkg, size, NULL);
if (status)
goto fw_ddp_compat_free_alloc;
for (i = 0; i < le32_to_cpu(pkg->count); i++) {
/* loop till we find the NVM package */
if (!pkg->pkg_info[i].is_in_nvm)
continue;
if ((*seg)->hdr.seg_format_ver.major !=
pkg->pkg_info[i].ver.major ||
(*seg)->hdr.seg_format_ver.minor >
pkg->pkg_info[i].ver.minor) {
status = ICE_ERR_FW_DDP_MISMATCH;
ice_debug(hw, ICE_DBG_INIT,
"OS package is not compatible with NVM.\n");
}
/* done processing NVM package so break */
break;
}
fw_ddp_compat_free_alloc:
kfree(pkg);
return status;
}
/**
* ice_init_pkg - initialize/download package
* @hw: pointer to the hardware structure
@ -1310,17 +1379,10 @@ enum ice_status ice_init_pkg(struct ice_hw *hw, u8 *buf, u32 len)
/* before downloading the package, check package version for
* compatibility with driver
*/
status = ice_chk_pkg_version(&hw->pkg_ver);
status = ice_chk_pkg_compat(hw, pkg, &seg);
if (status)
return status;
/* find segment in given package */
seg = (struct ice_seg *)ice_find_seg_in_pkg(hw, SEGMENT_TYPE_ICE, pkg);
if (!seg) {
ice_debug(hw, ICE_DBG_INIT, "no ice segment in package.\n");
return ICE_ERR_CFG;
}
/* initialize package hints and then download package */
ice_init_pkg_hints(hw, seg);
status = ice_download_pkg(hw, seg);
@ -1632,6 +1694,34 @@ ice_find_free_tunnel_entry(struct ice_hw *hw, enum ice_tunnel_type type,
return false;
}
/**
* ice_get_open_tunnel_port - retrieve an open tunnel port
* @hw: pointer to the HW structure
* @type: tunnel type (TNL_ALL will return any open port)
* @port: returns open port
*/
bool
ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
u16 *port)
{
bool res = false;
u16 i;
mutex_lock(&hw->tnl_lock);
for (i = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++)
if (hw->tnl.tbl[i].valid && hw->tnl.tbl[i].in_use &&
(type == TNL_ALL || hw->tnl.tbl[i].type == type)) {
*port = hw->tnl.tbl[i].port;
res = true;
break;
}
mutex_unlock(&hw->tnl_lock);
return res;
}
/**
* ice_create_tunnel
* @hw: pointer to the HW structure
@ -2332,6 +2422,12 @@ ice_find_prof_id(struct ice_hw *hw, enum ice_block blk,
u16 off;
u8 i;
/* For FD, we don't want to re-use a existed profile with the same
* field vector and mask. This will cause rule interference.
*/
if (blk == ICE_BLK_FD)
return ICE_ERR_DOES_NOT_EXIST;
for (i = 0; i < (u8)es->count; i++) {
off = i * es->fvw;
@ -2353,6 +2449,9 @@ ice_find_prof_id(struct ice_hw *hw, enum ice_block blk,
static bool ice_prof_id_rsrc_type(enum ice_block blk, u16 *rsrc_type)
{
switch (blk) {
case ICE_BLK_FD:
*rsrc_type = ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID;
break;
case ICE_BLK_RSS:
*rsrc_type = ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID;
break;
@ -2370,6 +2469,9 @@ static bool ice_prof_id_rsrc_type(enum ice_block blk, u16 *rsrc_type)
static bool ice_tcam_ent_rsrc_type(enum ice_block blk, u16 *rsrc_type)
{
switch (blk) {
case ICE_BLK_FD:
*rsrc_type = ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM;
break;
case ICE_BLK_RSS:
*rsrc_type = ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM;
break;
@ -2813,6 +2915,12 @@ static void ice_free_flow_profs(struct ice_hw *hw, u8 blk_idx)
mutex_lock(&hw->fl_profs_locks[blk_idx]);
list_for_each_entry_safe(p, tmp, &hw->fl_profs[blk_idx], l_entry) {
struct ice_flow_entry *e, *t;
list_for_each_entry_safe(e, t, &p->entries, l_entry)
ice_flow_rem_entry(hw, (enum ice_block)blk_idx,
ICE_FLOW_ENTRY_HNDL(e));
list_del(&p->l_entry);
devm_kfree(ice_hw_to_dev(hw), p);
}
@ -3441,6 +3549,212 @@ ice_upd_prof_hw(struct ice_hw *hw, enum ice_block blk,
return status;
}
/**
* ice_update_fd_mask - set Flow Director Field Vector mask for a profile
* @hw: pointer to the HW struct
* @prof_id: profile ID
* @mask_sel: mask select
*
* This function enable any of the masks selected by the mask select parameter
* for the profile specified.
*/
static void ice_update_fd_mask(struct ice_hw *hw, u16 prof_id, u32 mask_sel)
{
wr32(hw, GLQF_FDMASK_SEL(prof_id), mask_sel);
ice_debug(hw, ICE_DBG_INIT, "fd mask(%d): %x = %x\n", prof_id,
GLQF_FDMASK_SEL(prof_id), mask_sel);
}
struct ice_fd_src_dst_pair {
u8 prot_id;
u8 count;
u16 off;
};
static const struct ice_fd_src_dst_pair ice_fd_pairs[] = {
/* These are defined in pairs */
{ ICE_PROT_IPV4_OF_OR_S, 2, 12 },
{ ICE_PROT_IPV4_OF_OR_S, 2, 16 },
{ ICE_PROT_IPV4_IL, 2, 12 },
{ ICE_PROT_IPV4_IL, 2, 16 },
{ ICE_PROT_IPV6_OF_OR_S, 8, 8 },
{ ICE_PROT_IPV6_OF_OR_S, 8, 24 },
{ ICE_PROT_IPV6_IL, 8, 8 },
{ ICE_PROT_IPV6_IL, 8, 24 },
{ ICE_PROT_TCP_IL, 1, 0 },
{ ICE_PROT_TCP_IL, 1, 2 },
{ ICE_PROT_UDP_OF, 1, 0 },
{ ICE_PROT_UDP_OF, 1, 2 },
{ ICE_PROT_UDP_IL_OR_S, 1, 0 },
{ ICE_PROT_UDP_IL_OR_S, 1, 2 },
{ ICE_PROT_SCTP_IL, 1, 0 },
{ ICE_PROT_SCTP_IL, 1, 2 }
};
#define ICE_FD_SRC_DST_PAIR_COUNT ARRAY_SIZE(ice_fd_pairs)
/**
* ice_update_fd_swap - set register appropriately for a FD FV extraction
* @hw: pointer to the HW struct
* @prof_id: profile ID
* @es: extraction sequence (length of array is determined by the block)
*/
static enum ice_status
ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es)
{
DECLARE_BITMAP(pair_list, ICE_FD_SRC_DST_PAIR_COUNT);
u8 pair_start[ICE_FD_SRC_DST_PAIR_COUNT] = { 0 };
#define ICE_FD_FV_NOT_FOUND (-2)
s8 first_free = ICE_FD_FV_NOT_FOUND;
u8 used[ICE_MAX_FV_WORDS] = { 0 };
s8 orig_free, si;
u32 mask_sel = 0;
u8 i, j, k;
bitmap_zero(pair_list, ICE_FD_SRC_DST_PAIR_COUNT);
/* This code assumes that the Flow Director field vectors are assigned
* from the end of the FV indexes working towards the zero index, that
* only complete fields will be included and will be consecutive, and
* that there are no gaps between valid indexes.
*/
/* Determine swap fields present */
for (i = 0; i < hw->blk[ICE_BLK_FD].es.fvw; i++) {
/* Find the first free entry, assuming right to left population.
* This is where we can start adding additional pairs if needed.
*/
if (first_free == ICE_FD_FV_NOT_FOUND && es[i].prot_id !=
ICE_PROT_INVALID)
first_free = i - 1;
for (j = 0; j < ICE_FD_SRC_DST_PAIR_COUNT; j++)
if (es[i].prot_id == ice_fd_pairs[j].prot_id &&
es[i].off == ice_fd_pairs[j].off) {
set_bit(j, pair_list);
pair_start[j] = i;
}
}
orig_free = first_free;
/* determine missing swap fields that need to be added */
for (i = 0; i < ICE_FD_SRC_DST_PAIR_COUNT; i += 2) {
u8 bit1 = test_bit(i + 1, pair_list);
u8 bit0 = test_bit(i, pair_list);
if (bit0 ^ bit1) {
u8 index;
/* add the appropriate 'paired' entry */
if (!bit0)
index = i;
else
index = i + 1;
/* check for room */
if (first_free + 1 < (s8)ice_fd_pairs[index].count)
return ICE_ERR_MAX_LIMIT;
/* place in extraction sequence */
for (k = 0; k < ice_fd_pairs[index].count; k++) {
es[first_free - k].prot_id =
ice_fd_pairs[index].prot_id;
es[first_free - k].off =
ice_fd_pairs[index].off + (k * 2);
if (k > first_free)
return ICE_ERR_OUT_OF_RANGE;
/* keep track of non-relevant fields */
mask_sel |= BIT(first_free - k);
}
pair_start[index] = first_free;
first_free -= ice_fd_pairs[index].count;
}
}
/* fill in the swap array */
si = hw->blk[ICE_BLK_FD].es.fvw - 1;
while (si >= 0) {
u8 indexes_used = 1;
/* assume flat at this index */
#define ICE_SWAP_VALID 0x80
used[si] = si | ICE_SWAP_VALID;
if (orig_free == ICE_FD_FV_NOT_FOUND || si <= orig_free) {
si -= indexes_used;
continue;
}
/* check for a swap location */
for (j = 0; j < ICE_FD_SRC_DST_PAIR_COUNT; j++)
if (es[si].prot_id == ice_fd_pairs[j].prot_id &&
es[si].off == ice_fd_pairs[j].off) {
u8 idx;
/* determine the appropriate matching field */
idx = j + ((j % 2) ? -1 : 1);
indexes_used = ice_fd_pairs[idx].count;
for (k = 0; k < indexes_used; k++) {
used[si - k] = (pair_start[idx] - k) |
ICE_SWAP_VALID;
}
break;
}
si -= indexes_used;
}
/* for each set of 4 swap and 4 inset indexes, write the appropriate
* register
*/
for (j = 0; j < hw->blk[ICE_BLK_FD].es.fvw / 4; j++) {
u32 raw_swap = 0;
u32 raw_in = 0;
for (k = 0; k < 4; k++) {
u8 idx;
idx = (j * 4) + k;
if (used[idx] && !(mask_sel & BIT(idx))) {
raw_swap |= used[idx] << (k * BITS_PER_BYTE);
#define ICE_INSET_DFLT 0x9f
raw_in |= ICE_INSET_DFLT << (k * BITS_PER_BYTE);
}
}
/* write the appropriate swap register set */
wr32(hw, GLQF_FDSWAP(prof_id, j), raw_swap);
ice_debug(hw, ICE_DBG_INIT, "swap wr(%d, %d): %x = %08x\n",
prof_id, j, GLQF_FDSWAP(prof_id, j), raw_swap);
/* write the appropriate inset register set */
wr32(hw, GLQF_FDINSET(prof_id, j), raw_in);
ice_debug(hw, ICE_DBG_INIT, "inset wr(%d, %d): %x = %08x\n",
prof_id, j, GLQF_FDINSET(prof_id, j), raw_in);
}
/* initially clear the mask select for this profile */
ice_update_fd_mask(hw, prof_id, 0);
return 0;
}
/**
* ice_add_prof - add profile
* @hw: pointer to the HW struct
@ -3476,6 +3790,18 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
status = ice_alloc_prof_id(hw, blk, &prof_id);
if (status)
goto err_ice_add_prof;
if (blk == ICE_BLK_FD) {
/* For Flow Director block, the extraction sequence may
* need to be altered in the case where there are paired
* fields that have no match. This is necessary because
* for Flow Director, src and dest fields need to paired
* for filter programming and these values are swapped
* during Tx.
*/
status = ice_update_fd_swap(hw, prof_id, es);
if (status)
goto err_ice_add_prof;
}
/* and write new es */
ice_write_es(hw, blk, prof_id, es);

3
drivers/net/ethernet/intel/ice/ice_flex_pipe.h
View File

@ -18,6 +18,9 @@
#define ICE_PKG_CNT 4
bool
ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
u16 *port);
enum ice_status
ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port);
enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all);

8
drivers/net/ethernet/intel/ice/ice_flex_type.h
View File

@ -20,7 +20,7 @@ struct ice_fv {
/* Package and segment headers and tables */
struct ice_pkg_hdr {
struct ice_pkg_ver format_ver;
struct ice_pkg_ver pkg_format_ver;
__le32 seg_count;
__le32 seg_offset[1];
};
@ -30,9 +30,9 @@ struct ice_generic_seg_hdr {
#define SEGMENT_TYPE_METADATA 0x00000001
#define SEGMENT_TYPE_ICE 0x00000010
__le32 seg_type;
struct ice_pkg_ver seg_ver;
struct ice_pkg_ver seg_format_ver;
__le32 seg_size;
char seg_name[ICE_PKG_NAME_SIZE];
char seg_id[ICE_PKG_NAME_SIZE];
};
/* ice specific segment */
@ -75,7 +75,7 @@ struct ice_buf_table {
struct ice_global_metadata_seg {
struct ice_generic_seg_hdr hdr;
struct ice_pkg_ver pkg_ver;
__le32 track_id;
__le32 rsvd;
char pkg_name[ICE_PKG_NAME_SIZE];
};

319
drivers/net/ethernet/intel/ice/ice_flow.c
View File

@ -193,6 +193,40 @@ ice_flow_val_hdrs(struct ice_flow_seg_info *segs, u8 segs_cnt)
return 0;
}
/* Sizes of fixed known protocol headers without header options */
#define ICE_FLOW_PROT_HDR_SZ_MAC 14
#define ICE_FLOW_PROT_HDR_SZ_IPV4 20
#define ICE_FLOW_PROT_HDR_SZ_IPV6 40
#define ICE_FLOW_PROT_HDR_SZ_TCP 20
#define ICE_FLOW_PROT_HDR_SZ_UDP 8
#define ICE_FLOW_PROT_HDR_SZ_SCTP 12
/**
* ice_flow_calc_seg_sz - calculates size of a packet segment based on headers
* @params: information about the flow to be processed
* @seg: index of packet segment whose header size is to be determined
*/
static u16 ice_flow_calc_seg_sz(struct ice_flow_prof_params *params, u8 seg)
{
u16 sz = ICE_FLOW_PROT_HDR_SZ_MAC;
/* L3 headers */
if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_IPV4)
sz += ICE_FLOW_PROT_HDR_SZ_IPV4;
else if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_IPV6)
sz += ICE_FLOW_PROT_HDR_SZ_IPV6;
/* L4 headers */
if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_TCP)
sz += ICE_FLOW_PROT_HDR_SZ_TCP;
else if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_UDP)
sz += ICE_FLOW_PROT_HDR_SZ_UDP;
else if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_SCTP)
sz += ICE_FLOW_PROT_HDR_SZ_SCTP;
return sz;
}
/**
* ice_flow_proc_seg_hdrs - process protocol headers present in pkt segments
* @params: information about the flow to be processed
@ -347,6 +381,81 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
return 0;
}
/**
* ice_flow_xtract_raws - Create extract sequence entries for raw bytes
* @hw: pointer to the HW struct
* @params: information about the flow to be processed
* @seg: index of packet segment whose raw fields are to be be extracted
*/
static enum ice_status
ice_flow_xtract_raws(struct ice_hw *hw, struct ice_flow_prof_params *params,
u8 seg)
{
u16 fv_words;
u16 hdrs_sz;
u8 i;
if (!params->prof->segs[seg].raws_cnt)
return 0;
if (params->prof->segs[seg].raws_cnt >
ARRAY_SIZE(params->prof->segs[seg].raws))
return ICE_ERR_MAX_LIMIT;
/* Offsets within the segment headers are not supported */
hdrs_sz = ice_flow_calc_seg_sz(params, seg);
if (!hdrs_sz)
return ICE_ERR_PARAM;
fv_words = hw->blk[params->blk].es.fvw;
for (i = 0; i < params->prof->segs[seg].raws_cnt; i++) {
struct ice_flow_seg_fld_raw *raw;
u16 off, cnt, j;
raw = &params->prof->segs[seg].raws[i];
/* Storing extraction information */
raw->info.xtrct.prot_id = ICE_PROT_MAC_OF_OR_S;
raw->info.xtrct.off = (raw->off / ICE_FLOW_FV_EXTRACT_SZ) *
ICE_FLOW_FV_EXTRACT_SZ;
raw->info.xtrct.disp = (raw->off % ICE_FLOW_FV_EXTRACT_SZ) *
BITS_PER_BYTE;
raw->info.xtrct.idx = params->es_cnt;
/* Determine the number of field vector entries this raw field
* consumes.
*/
cnt = DIV_ROUND_UP(raw->info.xtrct.disp +
(raw->info.src.last * BITS_PER_BYTE),
(ICE_FLOW_FV_EXTRACT_SZ * BITS_PER_BYTE));
off = raw->info.xtrct.off;
for (j = 0; j < cnt; j++) {
u16 idx;
/* Make sure the number of extraction sequence required
* does not exceed the block's capability
*/
if (params->es_cnt >= hw->blk[params->blk].es.count ||
params->es_cnt >= ICE_MAX_FV_WORDS)
return ICE_ERR_MAX_LIMIT;
/* some blocks require a reversed field vector layout */
if (hw->blk[params->blk].es.reverse)
idx = fv_words - params->es_cnt - 1;
else
idx = params->es_cnt;
params->es[idx].prot_id = raw->info.xtrct.prot_id;
params->es[idx].off = off;
params->es_cnt++;
off += ICE_FLOW_FV_EXTRACT_SZ;
}
}
return 0;
}
/**
* ice_flow_create_xtrct_seq - Create an extraction sequence for given segments
* @hw: pointer to the HW struct
@ -373,6 +482,11 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw,
if (status)
return status;
}
/* Process raw matching bytes */
status = ice_flow_xtract_raws(hw, params, i);
if (status)
return status;
}
return status;
@ -397,10 +511,8 @@ ice_flow_proc_segs(struct ice_hw *hw, struct ice_flow_prof_params *params)
return status;
switch (params->blk) {
case ICE_BLK_FD:
case ICE_BLK_RSS:
/* Only header information is provided for RSS configuration.
* No further processing is needed.
*/
status = 0;
break;
default:
@ -481,6 +593,43 @@ ice_flow_find_prof_id(struct ice_hw *hw, enum ice_block blk, u64 prof_id)
return NULL;
}
/**
* ice_dealloc_flow_entry - Deallocate flow entry memory
* @hw: pointer to the HW struct
* @entry: flow entry to be removed
*/
static void
ice_dealloc_flow_entry(struct ice_hw *hw, struct ice_flow_entry *entry)
{
if (!entry)
return;
if (entry->entry)
devm_kfree(ice_hw_to_dev(hw), entry->entry);
devm_kfree(ice_hw_to_dev(hw), entry);
}
/**
* ice_flow_rem_entry_sync - Remove a flow entry
* @hw: pointer to the HW struct
* @blk: classification stage
* @entry: flow entry to be removed
*/
static enum ice_status
ice_flow_rem_entry_sync(struct ice_hw *hw, enum ice_block __always_unused blk,
struct ice_flow_entry *entry)
{
if (!entry)
return ICE_ERR_BAD_PTR;
list_del(&entry->l_entry);
ice_dealloc_flow_entry(hw, entry);
return 0;
}
/**
* ice_flow_add_prof_sync - Add a flow profile for packet segments and fields
* @hw: pointer to the HW struct
@ -568,6 +717,21 @@ ice_flow_rem_prof_sync(struct ice_hw *hw, enum ice_block blk,
{
enum ice_status status;
/* Remove all remaining flow entries before removing the flow profile */
if (!list_empty(&prof->entries)) {
struct ice_flow_entry *e, *t;
mutex_lock(&prof->entries_lock);
list_for_each_entry_safe(e, t, &prof->entries, l_entry) {
status = ice_flow_rem_entry_sync(hw, blk, e);
if (status)
break;
}
mutex_unlock(&prof->entries_lock);
}
/* Remove all hardware profiles associated with this flow profile */
status = ice_rem_prof(hw, blk, prof->id);
if (!status) {
@ -653,7 +817,7 @@ ice_flow_disassoc_prof(struct ice_hw *hw, enum ice_block blk,
* @segs_cnt: number of packet segments provided
* @prof: stores the returned flow profile added
*/
static enum ice_status
enum ice_status
ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,
u64 prof_id, struct ice_flow_seg_info *segs, u8 segs_cnt,
struct ice_flow_prof **prof)
@ -691,7 +855,7 @@ ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,
* @blk: the block for which the flow profile is to be removed
* @prof_id: unique ID of the flow profile to be removed
*/
static enum ice_status
enum ice_status
ice_flow_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id)
{
struct ice_flow_prof *prof;
@ -714,6 +878,113 @@ ice_flow_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id)
return status;
}
/**
* ice_flow_add_entry - Add a flow entry
* @hw: pointer to the HW struct
* @blk: classification stage
* @prof_id: ID of the profile to add a new flow entry to
* @entry_id: unique ID to identify this flow entry
* @vsi_handle: software VSI handle for the flow entry
* @prio: priority of the flow entry
* @data: pointer to a data buffer containing flow entry's match values/masks
* @entry_h: pointer to buffer that receives the new flow entry's handle
*/
enum ice_status
ice_flow_add_entry(struct ice_hw *hw, enum ice_block blk, u64 prof_id,
u64 entry_id, u16 vsi_handle, enum ice_flow_priority prio,
void *data, u64 *entry_h)
{
struct ice_flow_entry *e = NULL;
struct ice_flow_prof *prof;
enum ice_status status;
/* No flow entry data is expected for RSS */
if (!entry_h || (!data && blk != ICE_BLK_RSS))
return ICE_ERR_BAD_PTR;
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
mutex_lock(&hw->fl_profs_locks[blk]);
prof = ice_flow_find_prof_id(hw, blk, prof_id);
if (!prof) {
status = ICE_ERR_DOES_NOT_EXIST;
} else {
/* Allocate memory for the entry being added and associate
* the VSI to the found flow profile
*/
e = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*e), GFP_KERNEL);
if (!e)
status = ICE_ERR_NO_MEMORY;
else
status = ice_flow_assoc_prof(hw, blk, prof, vsi_handle);
}
mutex_unlock(&hw->fl_profs_locks[blk]);
if (status)
goto out;
e->id = entry_id;
e->vsi_handle = vsi_handle;
e->prof = prof;
e->priority = prio;
switch (blk) {
case ICE_BLK_FD:
case ICE_BLK_RSS:
break;
default:
status = ICE_ERR_NOT_IMPL;
goto out;
}
mutex_lock(&prof->entries_lock);
list_add(&e->l_entry, &prof->entries);
mutex_unlock(&prof->entries_lock);
*entry_h = ICE_FLOW_ENTRY_HNDL(e);
out:
if (status && e) {
if (e->entry)
devm_kfree(ice_hw_to_dev(hw), e->entry);
devm_kfree(ice_hw_to_dev(hw), e);
}
return status;
}
/**
* ice_flow_rem_entry - Remove a flow entry
* @hw: pointer to the HW struct
* @blk: classification stage
* @entry_h: handle to the flow entry to be removed
*/
enum ice_status ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk,
u64 entry_h)
{
struct ice_flow_entry *entry;
struct ice_flow_prof *prof;
enum ice_status status = 0;
if (entry_h == ICE_FLOW_ENTRY_HANDLE_INVAL)
return ICE_ERR_PARAM;
entry = ICE_FLOW_ENTRY_PTR(entry_h);
/* Retain the pointer to the flow profile as the entry will be freed */
prof = entry->prof;
if (prof) {
mutex_lock(&prof->entries_lock);
status = ice_flow_rem_entry_sync(hw, blk, entry);
mutex_unlock(&prof->entries_lock);
}
return status;
}
/**
* ice_flow_set_fld_ext - specifies locations of field from entry's input buffer
* @seg: packet segment the field being set belongs to
@ -776,7 +1047,7 @@ ice_flow_set_fld_ext(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
* create the content of a match entry. This function should only be used for
* fixed-size data structures.
*/
static void
void
ice_flow_set_fld(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
u16 val_loc, u16 mask_loc, u16 last_loc, bool range)
{
@ -786,6 +1057,42 @@ ice_flow_set_fld(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
ice_flow_set_fld_ext(seg, fld, t, val_loc, mask_loc, last_loc);
}
/**
* ice_flow_add_fld_raw - sets locations of a raw field from entry's input buf
* @seg: packet segment the field being set belongs to
* @off: offset of the raw field from the beginning of the segment in bytes
* @len: length of the raw pattern to be matched
* @val_loc: location of the value to match from entry's input buffer
* @mask_loc: location of mask value from entry's input buffer
*
* This function specifies the offset of the raw field to be match from the
* beginning of the specified packet segment, and the locations, in the form of
* byte offsets from the start of the input buffer for a flow entry, from where
* the value to match and the mask value to be extracted. These locations are
* then stored in the flow profile. When adding flow entries to the associated
* flow profile, these locations can be used to quickly extract the values to
* create the content of a match entry. This function should only be used for
* fixed-size data structures.
*/
void
ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
u16 val_loc, u16 mask_loc)
{
if (seg->raws_cnt < ICE_FLOW_SEG_RAW_FLD_MAX) {
seg->raws[seg->raws_cnt].off = off;
seg->raws[seg->raws_cnt].info.type = ICE_FLOW_FLD_TYPE_SIZE;
seg->raws[seg->raws_cnt].info.src.val = val_loc;
seg->raws[seg->raws_cnt].info.src.mask = mask_loc;
/* The "last" field is used to store the length of the field */
seg->raws[seg->raws_cnt].info.src.last = len;
}
/* Overflows of "raws" will be handled as an error condition later in
* the flow when this information is processed.
*/
seg->raws_cnt++;
}
#define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \
(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)

44
drivers/net/ethernet/intel/ice/ice_flow.h
View File

@ -128,6 +128,7 @@ enum ice_flow_priority {
};
#define ICE_FLOW_SEG_MAX 2
#define ICE_FLOW_SEG_RAW_FLD_MAX 2
#define ICE_FLOW_FV_EXTRACT_SZ 2
#define ICE_FLOW_SET_HDRS(seg, val) ((seg)->hdrs |= (u32)(val))
@ -164,14 +165,38 @@ struct ice_flow_fld_info {
struct ice_flow_seg_xtrct xtrct;
};
struct ice_flow_seg_fld_raw {
struct ice_flow_fld_info info;
u16 off; /* Offset from the start of the segment */
};
struct ice_flow_seg_info {
u32 hdrs; /* Bitmask indicating protocol headers present */
u64 match; /* Bitmask indicating header fields to be matched */
u64 range; /* Bitmask indicating header fields matched as ranges */
struct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX];
u8 raws_cnt; /* Number of raw fields to be matched */
struct ice_flow_seg_fld_raw raws[ICE_FLOW_SEG_RAW_FLD_MAX];
};
/* This structure describes a flow entry, and is tracked only in this file */
struct ice_flow_entry {
struct list_head l_entry;
u64 id;
struct ice_flow_prof *prof;
/* Flow entry's content */
void *entry;
enum ice_flow_priority priority;
u16 vsi_handle;
u16 entry_sz;
};
#define ICE_FLOW_ENTRY_HNDL(e) ((u64)e)
#define ICE_FLOW_ENTRY_PTR(h) ((struct ice_flow_entry *)(h))
struct ice_flow_prof {
struct list_head l_entry;
@ -197,7 +222,24 @@ struct ice_rss_cfg {
u32 packet_hdr;
};
enum ice_status ice_flow_rem_entry(struct ice_hw *hw, u64 entry_h);
enum ice_status
ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,
u64 prof_id, struct ice_flow_seg_info *segs, u8 segs_cnt,
struct ice_flow_prof **prof);
enum ice_status
ice_flow_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id);
enum ice_status
ice_flow_add_entry(struct ice_hw *hw, enum ice_block blk, u64 prof_id,
u64 entry_id, u16 vsi, enum ice_flow_priority prio,
void *data, u64 *entry_h);
enum ice_status
ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk, u64 entry_h);
void
ice_flow_set_fld(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
u16 val_loc, u16 mask_loc, u16 last_loc, bool range);
void
ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
u16 val_loc, u16 mask_loc);
void ice_rem_vsi_rss_list(struct ice_hw *hw, u16 vsi_handle);
enum ice_status ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle);
enum ice_status

26
drivers/net/ethernet/intel/ice/ice_hw_autogen.h
View File

@ -6,9 +6,6 @@
#ifndef _ICE_HW_AUTOGEN_H_
#define _ICE_HW_AUTOGEN_H_
#define PF0INT_ITR_0(_i) (0x03000004 + ((_i) * 4096))
#define PF0INT_ITR_1(_i) (0x03000008 + ((_i) * 4096))
#define PF0INT_ITR_2(_i) (0x0300000C + ((_i) * 4096))
#define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
#define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
#define QTX_COMM_HEAD_HEAD_S 0
@ -219,6 +216,11 @@
#define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
#define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4))
#define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32))
#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0)
#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32))
#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0)
#define GL_MDCK_TX_TDPU 0x00049348
#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
#define GL_MDET_RX 0x00294C00
@ -290,6 +292,20 @@
#define GL_PWR_MODE_CTL 0x000B820C
#define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
#define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30)
#define GLQF_FD_CNT 0x00460018
#define GLQF_FD_CNT_FD_BCNT_S 16
#define GLQF_FD_CNT_FD_BCNT_M ICE_M(0x7FFF, 16)
#define GLQF_FD_SIZE 0x00460010
#define GLQF_FD_SIZE_FD_GSIZE_S 0
#define GLQF_FD_SIZE_FD_GSIZE_M ICE_M(0x7FFF, 0)
#define GLQF_FD_SIZE_FD_BSIZE_S 16
#define GLQF_FD_SIZE_FD_BSIZE_M ICE_M(0x7FFF, 16)
#define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512))
#define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4))
#define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512))
#define PFQF_FD_ENA 0x0043A000
#define PFQF_FD_ENA_FD_ENA_M BIT(0)
#define PFQF_FD_SIZE 0x00460100
#define GLDCB_RTCTQ_RXQNUM_S 0
#define GLDCB_RTCTQ_RXQNUM_M ICE_M(0x7FF, 0)
#define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8))
@ -333,6 +349,7 @@
#define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8))
#define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8))
#define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8))
#define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8))
#define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8))
#define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8))
#define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8))
@ -343,6 +360,9 @@
#define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4))
#define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8))
#define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8))
#define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4))
#define VSIQF_FD_CNT_FD_GCNT_S 0
#define VSIQF_FD_CNT_FD_GCNT_M ICE_M(0x3FFF, 0)
#define VSIQF_HKEY_MAX_INDEX 12
#define VSIQF_HLUT_MAX_INDEX 15
#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))

101
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
View File

@ -40,6 +40,104 @@ union ice_32byte_rx_desc {
} wb; /* writeback */
};
struct ice_fltr_desc {
__le64 qidx_compq_space_stat;
__le64 dtype_cmd_vsi_fdid;
};
#define ICE_FXD_FLTR_QW0_QINDEX_S 0
#define ICE_FXD_FLTR_QW0_QINDEX_M (0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S)
#define ICE_FXD_FLTR_QW0_COMP_Q_S 11
#define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)
#define ICE_FXD_FLTR_QW0_COMP_Q_ZERO 0x0ULL
#define ICE_FXD_FLTR_QW0_COMP_REPORT_S 12
#define ICE_FXD_FLTR_QW0_COMP_REPORT_M \
(0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S)
#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL 0x1ULL
#define ICE_FXD_FLTR_QW0_FD_SPACE_S 14
#define ICE_FXD_FLTR_QW0_FD_SPACE_M (0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S)
#define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST 0x2ULL
#define ICE_FXD_FLTR_QW0_STAT_CNT_S 16
#define ICE_FXD_FLTR_QW0_STAT_CNT_M \
(0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S)
#define ICE_FXD_FLTR_QW0_STAT_ENA_S 29
#define ICE_FXD_FLTR_QW0_STAT_ENA_M (0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S)
#define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS 0x1ULL
#define ICE_FXD_FLTR_QW0_EVICT_ENA_S 31
#define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)
#define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE 0x0ULL
#define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE 0x1ULL
#define ICE_FXD_FLTR_QW0_TO_Q_S 32
#define ICE_FXD_FLTR_QW0_TO_Q_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S)
#define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX 0x0ULL
#define ICE_FXD_FLTR_QW0_TO_Q_PRI_S 35
#define ICE_FXD_FLTR_QW0_TO_Q_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S)
#define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 0x1ULL
#define ICE_FXD_FLTR_QW0_DPU_RECIPE_S 38
#define ICE_FXD_FLTR_QW0_DPU_RECIPE_M \
(0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S)
#define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT 0x0ULL
#define ICE_FXD_FLTR_QW0_DROP_S 40
#define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)
#define ICE_FXD_FLTR_QW0_DROP_NO 0x0ULL
#define ICE_FXD_FLTR_QW0_DROP_YES 0x1ULL
#define ICE_FXD_FLTR_QW0_FLEX_PRI_S 41
#define ICE_FXD_FLTR_QW0_FLEX_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S)
#define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE 0x0ULL
#define ICE_FXD_FLTR_QW0_FLEX_MDID_S 44
#define ICE_FXD_FLTR_QW0_FLEX_MDID_M (0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S)
#define ICE_FXD_FLTR_QW0_FLEX_MDID0 0x0ULL
#define ICE_FXD_FLTR_QW0_FLEX_VAL_S 48
#define ICE_FXD_FLTR_QW0_FLEX_VAL_M \
(0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S)
#define ICE_FXD_FLTR_QW0_FLEX_VAL0 0x0ULL
#define ICE_FXD_FLTR_QW1_DTYPE_S 0
#define ICE_FXD_FLTR_QW1_DTYPE_M (0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S)
#define ICE_FXD_FLTR_QW1_PCMD_S 4
#define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)
#define ICE_FXD_FLTR_QW1_PCMD_ADD 0x0ULL
#define ICE_FXD_FLTR_QW1_PCMD_REMOVE 0x1ULL
#define ICE_FXD_FLTR_QW1_PROF_PRI_S 5
#define ICE_FXD_FLTR_QW1_PROF_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S)
#define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO 0x0ULL
#define ICE_FXD_FLTR_QW1_PROF_S 8
#define ICE_FXD_FLTR_QW1_PROF_M (0x3FULL << ICE_FXD_FLTR_QW1_PROF_S)
#define ICE_FXD_FLTR_QW1_PROF_ZERO 0x0ULL
#define ICE_FXD_FLTR_QW1_FD_VSI_S 14
#define ICE_FXD_FLTR_QW1_FD_VSI_M (0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S)
#define ICE_FXD_FLTR_QW1_SWAP_S 24
#define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)
#define ICE_FXD_FLTR_QW1_SWAP_NOT_SET 0x0ULL
#define ICE_FXD_FLTR_QW1_SWAP_SET 0x1ULL
#define ICE_FXD_FLTR_QW1_FDID_PRI_S 25
#define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
#define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL
#define ICE_FXD_FLTR_QW1_FDID_MDID_S 28
#define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)
#define ICE_FXD_FLTR_QW1_FDID_MDID_FD 0x05ULL
#define ICE_FXD_FLTR_QW1_FDID_S 32
#define ICE_FXD_FLTR_QW1_FDID_M \
(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
#define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL
struct ice_rx_ptype_decoded {
u32 ptype:10;
u32 known:1;
@ -346,6 +444,7 @@ struct ice_tx_desc {
enum ice_tx_desc_dtype_value {
ICE_TX_DESC_DTYPE_DATA = 0x0,
ICE_TX_DESC_DTYPE_CTX = 0x1,
ICE_TX_DESC_DTYPE_FLTR_PROG = 0x8,
/* DESC_DONE - HW has completed write-back of descriptor */
ICE_TX_DESC_DTYPE_DESC_DONE = 0xF,
};
@ -357,12 +456,14 @@ enum ice_tx_desc_cmd_bits {
ICE_TX_DESC_CMD_EOP = 0x0001,
ICE_TX_DESC_CMD_RS = 0x0002,
ICE_TX_DESC_CMD_IL2TAG1 = 0x0008,
ICE_TX_DESC_CMD_DUMMY = 0x0010,
ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020,
ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040,
ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060,
ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100,
ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200,
ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300,
ICE_TX_DESC_CMD_RE = 0x0400,
};
#define ICE_TXD_QW1_OFFSET_S 16

228
drivers/net/ethernet/intel/ice/ice_lib.c
View File

@ -19,6 +19,8 @@ const char *ice_vsi_type_str(enum ice_vsi_type vsi_type)
return "ICE_VSI_PF";
case ICE_VSI_VF:
return "ICE_VSI_VF";
case ICE_VSI_CTRL:
return "ICE_VSI_CTRL";
case ICE_VSI_LB:
return "ICE_VSI_LB";
default:
@ -123,6 +125,7 @@ static void ice_vsi_set_num_desc(struct ice_vsi *vsi)
{
switch (vsi->type) {
case ICE_VSI_PF:
case ICE_VSI_CTRL:
case ICE_VSI_LB:
vsi->num_rx_desc = ICE_DFLT_NUM_RX_DESC;
vsi->num_tx_desc = ICE_DFLT_NUM_TX_DESC;
@ -187,6 +190,11 @@ static void ice_vsi_set_num_qs(struct ice_vsi *vsi, u16 vf_id)
*/
vsi->num_q_vectors = pf->num_msix_per_vf - ICE_NONQ_VECS_VF;
break;
case ICE_VSI_CTRL:
vsi->alloc_txq = 1;
vsi->alloc_rxq = 1;
vsi->num_q_vectors = 1;
break;
case ICE_VSI_LB:
vsi->alloc_txq = 1;
vsi->alloc_rxq = 1;
@ -322,7 +330,7 @@ int ice_vsi_clear(struct ice_vsi *vsi)
/* updates the PF for this cleared VSI */
pf->vsi[vsi->idx] = NULL;
if (vsi->idx < pf->next_vsi)
if (vsi->idx < pf->next_vsi && vsi->type != ICE_VSI_CTRL)
pf->next_vsi = vsi->idx;
ice_vsi_free_arrays(vsi);
@ -332,6 +340,25 @@ int ice_vsi_clear(struct ice_vsi *vsi)
return 0;
}
/**
* ice_msix_clean_ctrl_vsi - MSIX mode interrupt handler for ctrl VSI
* @irq: interrupt number
* @data: pointer to a q_vector
*/
static irqreturn_t ice_msix_clean_ctrl_vsi(int __always_unused irq, void *data)
{
struct ice_q_vector *q_vector = (struct ice_q_vector *)data;
if (!q_vector->tx.ring)
return IRQ_HANDLED;
#define FDIR_RX_DESC_CLEAN_BUDGET 64
ice_clean_rx_irq(q_vector->rx.ring, FDIR_RX_DESC_CLEAN_BUDGET);
ice_clean_ctrl_tx_irq(q_vector->tx.ring);
return IRQ_HANDLED;
}
/**
* ice_msix_clean_rings - MSIX mode Interrupt Handler
* @irq: interrupt number
@ -383,8 +410,6 @@ ice_vsi_alloc(struct ice_pf *pf, enum ice_vsi_type vsi_type, u16 vf_id)
vsi->back = pf;
set_bit(__ICE_DOWN, vsi->state);
vsi->idx = pf->next_vsi;
if (vsi_type == ICE_VSI_VF)
ice_vsi_set_num_qs(vsi, vf_id);
else
@ -398,6 +423,13 @@ ice_vsi_alloc(struct ice_pf *pf, enum ice_vsi_type vsi_type, u16 vf_id)
/* Setup default MSIX irq handler for VSI */
vsi->irq_handler = ice_msix_clean_rings;
break;
case ICE_VSI_CTRL:
if (ice_vsi_alloc_arrays(vsi))
goto err_rings;
/* Setup ctrl VSI MSIX irq handler */
vsi->irq_handler = ice_msix_clean_ctrl_vsi;
break;
case ICE_VSI_VF:
if (ice_vsi_alloc_arrays(vsi))
goto err_rings;
@ -411,12 +443,20 @@ ice_vsi_alloc(struct ice_pf *pf, enum ice_vsi_type vsi_type, u16 vf_id)
goto unlock_pf;
}
/* fill VSI slot in the PF struct */
pf->vsi[pf->next_vsi] = vsi;
if (vsi->type == ICE_VSI_CTRL) {
/* Use the last VSI slot as the index for the control VSI */
vsi->idx = pf->num_alloc_vsi - 1;
pf->ctrl_vsi_idx = vsi->idx;
pf->vsi[vsi->idx] = vsi;
} else {
/* fill slot and make note of the index */
vsi->idx = pf->next_vsi;
pf->vsi[pf->next_vsi] = vsi;
/* prepare pf->next_vsi for next use */
pf->next_vsi = ice_get_free_slot(pf->vsi, pf->num_alloc_vsi,
pf->next_vsi);
/* prepare pf->next_vsi for next use */
pf->next_vsi = ice_get_free_slot(pf->vsi, pf->num_alloc_vsi,
pf->next_vsi);
}
goto unlock_pf;
err_rings:
@ -427,6 +467,48 @@ ice_vsi_alloc(struct ice_pf *pf, enum ice_vsi_type vsi_type, u16 vf_id)
return vsi;
}
/**
* ice_alloc_fd_res - Allocate FD resource for a VSI
* @vsi: pointer to the ice_vsi
*
* This allocates the FD resources
*
* Returns 0 on success, -EPERM on no-op or -EIO on failure
*/
static int ice_alloc_fd_res(struct ice_vsi *vsi)
{
struct ice_pf *pf = vsi->back;
u32 g_val, b_val;
/* Flow Director filters are only allocated/assigned to the PF VSI which
* passes the traffic. The CTRL VSI is only used to add/delete filters
* so we don't allocate resources to it
*/
/* FD filters from guaranteed pool per VSI */
g_val = pf->hw.func_caps.fd_fltr_guar;
if (!g_val)
return -EPERM;
/* FD filters from best effort pool */
b_val = pf->hw.func_caps.fd_fltr_best_effort;
if (!b_val)
return -EPERM;
if (vsi->type != ICE_VSI_PF)
return -EPERM;
if (!test_bit(ICE_FLAG_FD_ENA, pf->flags))
return -EPERM;
vsi->num_gfltr = g_val / pf->num_alloc_vsi;
/* each VSI gets same "best_effort" quota */
vsi->num_bfltr = b_val;
return 0;
}
/**
* ice_vsi_get_qs - Assign queues from PF to VSI
* @vsi: the VSI to assign queues to
@ -583,8 +665,8 @@ static void ice_vsi_set_rss_params(struct ice_vsi *vsi)
case ICE_VSI_LB:
break;
default:
dev_warn(ice_pf_to_dev(pf), "Unknown VSI type %d\n",
vsi->type);
dev_dbg(ice_pf_to_dev(pf), "Unsupported VSI type %s\n",
ice_vsi_type_str(vsi->type));
break;
}
}
@ -753,6 +835,51 @@ static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)
ctxt->info.q_mapping[1] = cpu_to_le16(vsi->num_rxq);
}
/**
* ice_set_fd_vsi_ctx - Set FD VSI context before adding a VSI
* @ctxt: the VSI context being set
* @vsi: the VSI being configured
*/
static void ice_set_fd_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)
{
u8 dflt_q_group, dflt_q_prio;
u16 dflt_q, report_q, val;
if (vsi->type != ICE_VSI_PF && vsi->type != ICE_VSI_CTRL)
return;
val = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
ctxt->info.valid_sections |= cpu_to_le16(val);
dflt_q = 0;
dflt_q_group = 0;
report_q = 0;
dflt_q_prio = 0;
/* enable flow director filtering/programming */
val = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
ctxt->info.fd_options = cpu_to_le16(val);
/* max of allocated flow director filters */
ctxt->info.max_fd_fltr_dedicated =
cpu_to_le16(vsi->num_gfltr);
/* max of shared flow director filters any VSI may program */
ctxt->info.max_fd_fltr_shared =
cpu_to_le16(vsi->num_bfltr);
/* default queue index within the VSI of the default FD */
val = ((dflt_q << ICE_AQ_VSI_FD_DEF_Q_S) &
ICE_AQ_VSI_FD_DEF_Q_M);
/* target queue or queue group to the FD filter */
val |= ((dflt_q_group << ICE_AQ_VSI_FD_DEF_GRP_S) &
ICE_AQ_VSI_FD_DEF_GRP_M);
ctxt->info.fd_def_q = cpu_to_le16(val);
/* queue index on which FD filter completion is reported */
val = ((report_q << ICE_AQ_VSI_FD_REPORT_Q_S) &
ICE_AQ_VSI_FD_REPORT_Q_M);
/* priority of the default qindex action */
val |= ((dflt_q_prio << ICE_AQ_VSI_FD_DEF_PRIORITY_S) &
ICE_AQ_VSI_FD_DEF_PRIORITY_M);
ctxt->info.fd_report_opt = cpu_to_le16(val);
}
/**
* ice_set_rss_vsi_ctx - Set RSS VSI context before adding a VSI
* @ctxt: the VSI context being set
@ -778,13 +905,10 @@ static void ice_set_rss_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)
lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI;
hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
break;
case ICE_VSI_LB:
default:
dev_dbg(dev, "Unsupported VSI type %s\n",
ice_vsi_type_str(vsi->type));
return;
default:
dev_warn(dev, "Unknown VSI type %d\n", vsi->type);
return;
}
ctxt->info.q_opt_rss = ((lut_type << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) &
@ -816,6 +940,7 @@ static int ice_vsi_init(struct ice_vsi *vsi, bool init_vsi)
ctxt->info = vsi->info;
switch (vsi->type) {
case ICE_VSI_CTRL:
case ICE_VSI_LB:
case ICE_VSI_PF:
ctxt->flags = ICE_AQ_VSI_TYPE_PF;
@ -831,12 +956,15 @@ static int ice_vsi_init(struct ice_vsi *vsi, bool init_vsi)
}
ice_set_dflt_vsi_ctx(ctxt);
if (test_bit(ICE_FLAG_FD_ENA, pf->flags))
ice_set_fd_vsi_ctx(ctxt, vsi);
/* if the switch is in VEB mode, allow VSI loopback */
if (vsi->vsw->bridge_mode == BRIDGE_MODE_VEB)
ctxt->info.sw_flags |= ICE_AQ_VSI_SW_FLAG_ALLOW_LB;
/* Set LUT type and HASH type if RSS is enabled */
if (test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
if (test_bit(ICE_FLAG_RSS_ENA, pf->flags) &&
vsi->type != ICE_VSI_CTRL) {
ice_set_rss_vsi_ctx(ctxt, vsi);
/* if updating VSI context, make sure to set valid_section:
* to indicate which section of VSI context being updated
@ -1986,10 +2114,12 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,
if (vsi->type == ICE_VSI_VF)
vsi->vf_id = vf_id;
ice_alloc_fd_res(vsi);
if (ice_vsi_get_qs(vsi)) {
dev_err(dev, "Failed to allocate queues. vsi->idx = %d\n",
vsi->idx);
goto unroll_get_qs;
goto unroll_vsi_alloc;
}
/* set RSS capabilities */
@ -2004,6 +2134,7 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,
goto unroll_get_qs;
switch (vsi->type) {
case ICE_VSI_CTRL:
case ICE_VSI_PF:
ret = ice_vsi_alloc_q_vectors(vsi);
if (ret)
@ -2034,14 +2165,17 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,
ice_vsi_map_rings_to_vectors(vsi);
/* Do not exit if configuring RSS had an issue, at least
* receive traffic on first queue. Hence no need to capture
* return value
*/
if (test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
ice_vsi_cfg_rss_lut_key(vsi);
ice_vsi_set_rss_flow_fld(vsi);
}
/* ICE_VSI_CTRL does not need RSS so skip RSS processing */
if (vsi->type != ICE_VSI_CTRL)
/* Do not exit if configuring RSS had an issue, at
* least receive traffic on first queue. Hence no
* need to capture return value
*/
if (test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
ice_vsi_cfg_rss_lut_key(vsi);
ice_vsi_set_rss_flow_fld(vsi);
}
ice_init_arfs(vsi);
break;
case ICE_VSI_VF:
/* VF driver will take care of creating netdev for this type and
@ -2122,6 +2256,7 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,
ice_vsi_delete(vsi);
unroll_get_qs:
ice_vsi_put_qs(vsi);
unroll_vsi_alloc:
ice_vsi_clear(vsi);
return NULL;
@ -2274,6 +2409,8 @@ int ice_ena_vsi(struct ice_vsi *vsi, bool locked)
if (!locked)
rtnl_unlock();
}
} else if (vsi->type == ICE_VSI_CTRL) {
err = ice_vsi_open_ctrl(vsi);
}
return err;
@ -2303,6 +2440,8 @@ void ice_dis_vsi(struct ice_vsi *vsi, bool locked)
} else {
ice_vsi_close(vsi);
}
} else if (vsi->type == ICE_VSI_CTRL) {
ice_vsi_close(vsi);
}
}
@ -2610,6 +2749,8 @@ int ice_vsi_rebuild(struct ice_vsi *vsi, bool init_vsi)
goto err_vsi;
ice_vsi_get_qs(vsi);
ice_alloc_fd_res(vsi);
ice_vsi_set_tc_cfg(vsi);
/* Initialize VSI struct elements and create VSI in FW */
@ -2618,6 +2759,7 @@ int ice_vsi_rebuild(struct ice_vsi *vsi, bool init_vsi)
goto err_vsi;
switch (vsi->type) {
case ICE_VSI_CTRL:
case ICE_VSI_PF:
ret = ice_vsi_alloc_q_vectors(vsi);
if (ret)
@ -2642,12 +2784,14 @@ int ice_vsi_rebuild(struct ice_vsi *vsi, bool init_vsi)
if (ret)
goto err_vectors;
}
/* Do not exit if configuring RSS had an issue, at least
* receive traffic on first queue. Hence no need to capture
* return value
*/
if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
ice_vsi_cfg_rss_lut_key(vsi);
/* ICE_VSI_CTRL does not need RSS so skip RSS processing */
if (vsi->type != ICE_VSI_CTRL)
/* Do not exit if configuring RSS had an issue, at
* least receive traffic on first queue. Hence no
* need to capture return value
*/
if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
ice_vsi_cfg_rss_lut_key(vsi);
break;
case ICE_VSI_VF:
ret = ice_vsi_alloc_q_vectors(vsi);
@ -2848,6 +2992,30 @@ void ice_update_rx_ring_stats(struct ice_ring *rx_ring, u64 pkts, u64 bytes)
u64_stats_update_end(&rx_ring->syncp);
}
/**
* ice_status_to_errno - convert from enum ice_status to Linux errno
* @err: ice_status value to convert
*/
int ice_status_to_errno(enum ice_status err)
{
switch (err) {
case ICE_SUCCESS:
return 0;
case ICE_ERR_DOES_NOT_EXIST:
return -ENOENT;
case ICE_ERR_OUT_OF_RANGE:
return -ENOTTY;
case ICE_ERR_PARAM:
return -EINVAL;
case ICE_ERR_NO_MEMORY:
return -ENOMEM;
case ICE_ERR_MAX_LIMIT:
return -EAGAIN;
default:
return -EINVAL;
}
}
/**
* ice_is_dflt_vsi_in_use - check if the default forwarding VSI is being used
* @sw: switch to check if its default forwarding VSI is free

2
drivers/net/ethernet/intel/ice/ice_lib.h
View File

@ -92,6 +92,8 @@ void ice_update_rx_ring_stats(struct ice_ring *ring, u64 pkts, u64 bytes);
void ice_vsi_cfg_frame_size(struct ice_vsi *vsi);
int ice_status_to_errno(enum ice_status err);
u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran);
enum ice_status

272
drivers/net/ethernet/intel/ice/ice_main.c
View File

@ -452,7 +452,7 @@ static void
ice_prepare_for_reset(struct ice_pf *pf)
{
struct ice_hw *hw = &pf->hw;
int i;
unsigned int i;
/* already prepared for reset */
if (test_bit(__ICE_PREPARED_FOR_RESET, pf->state))
@ -1113,7 +1113,7 @@ static void ice_clean_mailboxq_subtask(struct ice_pf *pf)
*
* If not already scheduled, this puts the task into the work queue.
*/
static void ice_service_task_schedule(struct ice_pf *pf)
void ice_service_task_schedule(struct ice_pf *pf)
{
if (!test_bit(__ICE_SERVICE_DIS, pf->state) &&
!test_and_set_bit(__ICE_SERVICE_SCHED, pf->state) &&
@ -1188,8 +1188,8 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
{
struct device *dev = ice_pf_to_dev(pf);
struct ice_hw *hw = &pf->hw;
unsigned int i;
u32 reg;
int i;
if (!test_and_clear_bit(__ICE_MDD_EVENT_PENDING, pf->state)) {
/* Since the VF MDD event logging is rate limited, check if
@ -1322,8 +1322,13 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
* PF can be configured to reset the VF through ethtool
* private flag mdd-auto-reset-vf.
*/
if (test_bit(ICE_FLAG_MDD_AUTO_RESET_VF, pf->flags))
if (test_bit(ICE_FLAG_MDD_AUTO_RESET_VF, pf->flags)) {
/* VF MDD event counters will be cleared by
* reset, so print the event prior to reset.
*/
ice_print_vf_rx_mdd_event(vf);
ice_reset_vf(&pf->vf[i], false);
}
}
}
@ -1483,7 +1488,7 @@ static void ice_service_task(struct work_struct *work)
ice_process_vflr_event(pf);
ice_clean_mailboxq_subtask(pf);
ice_sync_arfs_fltrs(pf);
/* Clear __ICE_SERVICE_SCHED flag to allow scheduling next event */
ice_service_task_complete(pf);
@ -1642,9 +1647,14 @@ static int ice_vsi_req_irq_msix(struct ice_vsi *vsi, char *basename)
}
/* register for affinity change notifications */
q_vector->affinity_notify.notify = ice_irq_affinity_notify;
q_vector->affinity_notify.release = ice_irq_affinity_release;
irq_set_affinity_notifier(irq_num, &q_vector->affinity_notify);
if (!IS_ENABLED(CONFIG_RFS_ACCEL)) {
struct irq_affinity_notify *affinity_notify;
affinity_notify = &q_vector->affinity_notify;
affinity_notify->notify = ice_irq_affinity_notify;
affinity_notify->release = ice_irq_affinity_release;
irq_set_affinity_notifier(irq_num, affinity_notify);
}
/* assign the mask for this irq */
irq_set_affinity_hint(irq_num, &q_vector->affinity_mask);
@ -1656,8 +1666,9 @@ static int ice_vsi_req_irq_msix(struct ice_vsi *vsi, char *basename)
free_q_irqs:
while (vector) {
vector--;
irq_num = pf->msix_entries[base + vector].vector,
irq_set_affinity_notifier(irq_num, NULL);
irq_num = pf->msix_entries[base + vector].vector;
if (!IS_ENABLED(CONFIG_RFS_ACCEL))
irq_set_affinity_notifier(irq_num, NULL);
irq_set_affinity_hint(irq_num, NULL);
devm_free_irq(dev, irq_num, &vsi->q_vectors[vector]);
}
@ -2319,6 +2330,7 @@ static void ice_set_netdev_features(struct net_device *netdev)
dflt_features = NETIF_F_SG |
NETIF_F_HIGHDMA |
NETIF_F_NTUPLE |
NETIF_F_RXHASH;
csumo_features = NETIF_F_RXCSUM |
@ -2458,6 +2470,20 @@ ice_pf_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi)
return ice_vsi_setup(pf, pi, ICE_VSI_PF, ICE_INVAL_VFID);
}
/**
* ice_ctrl_vsi_setup - Set up a control VSI
* @pf: board private structure
* @pi: pointer to the port_info instance
*
* Returns pointer to the successfully allocated VSI software struct
* on success, otherwise returns NULL on failure.
*/
static struct ice_vsi *
ice_ctrl_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi)
{
return ice_vsi_setup(pf, pi, ICE_VSI_CTRL, ICE_INVAL_VFID);
}
/**
* ice_lb_vsi_setup - Set up a loopback VSI
* @pf: board private structure
@ -2596,12 +2622,22 @@ static int ice_setup_pf_sw(struct ice_pf *pf)
*/
ice_napi_add(vsi);
status = ice_set_cpu_rx_rmap(vsi);
if (status) {
dev_err(ice_pf_to_dev(pf), "Failed to set CPU Rx map VSI %d error %d\n",
vsi->vsi_num, status);
status = -EINVAL;
goto unroll_napi_add;
}
status = ice_init_mac_fltr(pf);
if (status)
goto unroll_napi_add;
goto free_cpu_rx_map;
return status;
free_cpu_rx_map:
ice_free_cpu_rx_rmap(vsi);
unroll_napi_add:
if (vsi) {
ice_napi_del(vsi);
@ -2706,6 +2742,23 @@ static void ice_set_pf_caps(struct ice_pf *pf)
if (func_caps->common_cap.rss_table_size)
set_bit(ICE_FLAG_RSS_ENA, pf->flags);
clear_bit(ICE_FLAG_FD_ENA, pf->flags);
if (func_caps->fd_fltr_guar > 0 || func_caps->fd_fltr_best_effort > 0) {
u16 unused;
/* ctrl_vsi_idx will be set to a valid value when flow director
* is setup by ice_init_fdir
*/
pf->ctrl_vsi_idx = ICE_NO_VSI;
set_bit(ICE_FLAG_FD_ENA, pf->flags);
/* force guaranteed filter pool for PF */
ice_alloc_fd_guar_item(&pf->hw, &unused,
func_caps->fd_fltr_guar);
/* force shared filter pool for PF */
ice_alloc_fd_shrd_item(&pf->hw, &unused,
func_caps->fd_fltr_best_effort);
}
pf->max_pf_txqs = func_caps->common_cap.num_txq;
pf->max_pf_rxqs = func_caps->common_cap.num_rxq;
}
@ -2772,6 +2825,15 @@ static int ice_ena_msix_range(struct ice_pf *pf)
v_budget += needed;
v_left -= needed;
/* reserve one vector for flow director */
if (test_bit(ICE_FLAG_FD_ENA, pf->flags)) {
needed = ICE_FDIR_MSIX;
if (v_left < needed)
goto no_hw_vecs_left_err;
v_budget += needed;
v_left -= needed;
}
pf->msix_entries = devm_kcalloc(dev, v_budget,
sizeof(*pf->msix_entries), GFP_KERNEL);
@ -2796,8 +2858,10 @@ static int ice_ena_msix_range(struct ice_pf *pf)
if (v_actual < v_budget) {
dev_warn(dev, "not enough OS MSI-X vectors. requested = %d, obtained = %d\n",
v_budget, v_actual);
/* 2 vectors for LAN (traffic + OICR) */
/* 2 vectors each for LAN and RDMA (traffic + OICR), one for flow director */
#define ICE_MIN_LAN_VECS 2
#define ICE_MIN_RDMA_VECS 2
#define ICE_MIN_VECS (ICE_MIN_LAN_VECS + ICE_MIN_RDMA_VECS + 1)
if (v_actual < ICE_MIN_LAN_VECS) {
/* error if we can't get minimum vectors */
@ -2988,6 +3052,9 @@ ice_log_pkg_init(struct ice_hw *hw, enum ice_status *status)
*status = ICE_ERR_NOT_SUPPORTED;
}
break;
case ICE_ERR_FW_DDP_MISMATCH:
dev_err(dev, "The firmware loaded on the device is not compatible with the DDP package. Please update the device's NVM. Entering safe mode.\n");
break;
case ICE_ERR_BUF_TOO_SHORT:
case ICE_ERR_CFG:
dev_err(dev, "The DDP package file is invalid. Entering Safe Mode.\n");
@ -3102,6 +3169,53 @@ static enum ice_status ice_send_version(struct ice_pf *pf)
return ice_aq_send_driver_ver(&pf->hw, &dv, NULL);
}
/**
* ice_init_fdir - Initialize flow director VSI and configuration
* @pf: pointer to the PF instance
*
* returns 0 on success, negative on error
*/
static int ice_init_fdir(struct ice_pf *pf)
{
struct device *dev = ice_pf_to_dev(pf);
struct ice_vsi *ctrl_vsi;
int err;
/* Side Band Flow Director needs to have a control VSI.
* Allocate it and store it in the PF.
*/
ctrl_vsi = ice_ctrl_vsi_setup(pf, pf->hw.port_info);
if (!ctrl_vsi) {
dev_dbg(dev, "could not create control VSI\n");
return -ENOMEM;
}
err = ice_vsi_open_ctrl(ctrl_vsi);
if (err) {
dev_dbg(dev, "could not open control VSI\n");
goto err_vsi_open;
}
mutex_init(&pf->hw.fdir_fltr_lock);
err = ice_fdir_create_dflt_rules(pf);
if (err)
goto err_fdir_rule;
return 0;
err_fdir_rule:
ice_fdir_release_flows(&pf->hw);
ice_vsi_close(ctrl_vsi);
err_vsi_open:
ice_vsi_release(ctrl_vsi);
if (pf->ctrl_vsi_idx != ICE_NO_VSI) {
pf->vsi[pf->ctrl_vsi_idx] = NULL;
pf->ctrl_vsi_idx = ICE_NO_VSI;
}
return err;
}
/**
* ice_get_opt_fw_name - return optional firmware file name or NULL
* @pf: pointer to the PF instance
@ -3362,6 +3476,10 @@ ice_probe(struct pci_dev *pdev, const struct pci_device_id __always_unused *ent)
/* initialize DDP driven features */
/* Note: Flow director init failure is non-fatal to load */
if (ice_init_fdir(pf))
dev_err(dev, "could not initialize flow director\n");
/* Note: DCB init failure is non-fatal to load */
if (ice_init_pf_dcb(pf, false)) {
clear_bit(ICE_FLAG_DCB_CAPABLE, pf->flags);
@ -3424,6 +3542,9 @@ static void ice_remove(struct pci_dev *pdev)
set_bit(__ICE_DOWN, pf->state);
ice_service_task_stop(pf);
mutex_destroy(&(&pf->hw)->fdir_fltr_lock);
if (!ice_is_safe_mode(pf))
ice_remove_arfs(pf);
ice_devlink_destroy_port(pf);
ice_vsi_release_all(pf);
ice_free_irq_msix_misc(pf);
@ -3940,6 +4061,16 @@ ice_set_features(struct net_device *netdev, netdev_features_t features)
(netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
ret = ice_cfg_vlan_pruning(vsi, false, false);
if ((features & NETIF_F_NTUPLE) &&
!(netdev->features & NETIF_F_NTUPLE)) {
ice_vsi_manage_fdir(vsi, true);
ice_init_arfs(vsi);
} else if (!(features & NETIF_F_NTUPLE) &&
(netdev->features & NETIF_F_NTUPLE)) {
ice_vsi_manage_fdir(vsi, false);
ice_clear_arfs(vsi);
}
return ret;
}
@ -4179,6 +4310,7 @@ void ice_update_pf_stats(struct ice_pf *pf)
{
struct ice_hw_port_stats *prev_ps, *cur_ps;
struct ice_hw *hw = &pf->hw;
u16 fd_ctr_base;
u8 port;
port = hw->port_info->lport;
@ -4267,6 +4399,12 @@ void ice_update_pf_stats(struct ice_pf *pf)
ice_stat_update40(hw, GLPRT_PTC9522L(port), pf->stat_prev_loaded,
&prev_ps->tx_size_big, &cur_ps->tx_size_big);
fd_ctr_base = hw->fd_ctr_base;
ice_stat_update40(hw,
GLSTAT_FD_CNT0L(ICE_FD_SB_STAT_IDX(fd_ctr_base)),
pf->stat_prev_loaded, &prev_ps->fd_sb_match,
&cur_ps->fd_sb_match);
ice_stat_update32(hw, GLPRT_LXONRXC(port), pf->stat_prev_loaded,
&prev_ps->link_xon_rx, &cur_ps->link_xon_rx);
@ -4310,6 +4448,8 @@ void ice_update_pf_stats(struct ice_pf *pf)
ice_stat_update32(hw, GLPRT_RJC(port), pf->stat_prev_loaded,
&prev_ps->rx_jabber, &cur_ps->rx_jabber);
cur_ps->fd_sb_status = test_bit(ICE_FLAG_FD_ENA, pf->flags) ? 1 : 0;
pf->stat_prev_loaded = true;
}
@ -4494,6 +4634,62 @@ int ice_vsi_setup_rx_rings(struct ice_vsi *vsi)
return err;
}
/**
* ice_vsi_open_ctrl - open control VSI for use
* @vsi: the VSI to open
*
* Initialization of the Control VSI
*
* Returns 0 on success, negative value on error
*/
int ice_vsi_open_ctrl(struct ice_vsi *vsi)
{
char int_name[ICE_INT_NAME_STR_LEN];
struct ice_pf *pf = vsi->back;
struct device *dev;
int err;
dev = ice_pf_to_dev(pf);
/* allocate descriptors */
err = ice_vsi_setup_tx_rings(vsi);
if (err)
goto err_setup_tx;
err = ice_vsi_setup_rx_rings(vsi);
if (err)
goto err_setup_rx;
err = ice_vsi_cfg(vsi);
if (err)
goto err_setup_rx;
snprintf(int_name, sizeof(int_name) - 1, "%s-%s:ctrl",
dev_driver_string(dev), dev_name(dev));
err = ice_vsi_req_irq_msix(vsi, int_name);
if (err)
goto err_setup_rx;
ice_vsi_cfg_msix(vsi);
err = ice_vsi_start_all_rx_rings(vsi);
if (err)
goto err_up_complete;
clear_bit(__ICE_DOWN, vsi->state);
ice_vsi_ena_irq(vsi);
return 0;
err_up_complete:
ice_down(vsi);
err_setup_rx:
ice_vsi_free_rx_rings(vsi);
err_setup_tx:
ice_vsi_free_tx_rings(vsi);
return err;
}
/**
* ice_vsi_open - Called when a network interface is made active
* @vsi: the VSI to open
@ -4713,6 +4909,12 @@ static void ice_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type)
goto err_init_ctrlq;
}
ret = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
if (ret) {
dev_err(dev, "set_mac_cfg failed %s\n", ice_stat_str(ret));
goto err_init_ctrlq;
}
err = ice_sched_init_port(hw->port_info);
if (err)
goto err_sched_init_port;
@ -4728,6 +4930,21 @@ static void ice_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type)
goto err_sched_init_port;
}
if (test_bit(ICE_FLAG_FD_ENA, pf->flags)) {
wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
if (!rd32(hw, PFQF_FD_SIZE)) {
u16 unused, guar, b_effort;
guar = hw->func_caps.fd_fltr_guar;
b_effort = hw->func_caps.fd_fltr_best_effort;
/* force guaranteed filter pool for PF */
ice_alloc_fd_guar_item(hw, &unused, guar);
/* force shared filter pool for PF */
ice_alloc_fd_shrd_item(hw, &unused, b_effort);
}
}
if (test_bit(ICE_FLAG_DCB_ENA, pf->flags))
ice_dcb_rebuild(pf);
@ -4746,6 +4963,24 @@ static void ice_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type)
}
}
/* If Flow Director is active */
if (test_bit(ICE_FLAG_FD_ENA, pf->flags)) {
err = ice_vsi_rebuild_by_type(pf, ICE_VSI_CTRL);
if (err) {
dev_err(dev, "control VSI rebuild failed: %d\n", err);
goto err_vsi_rebuild;
}
/* replay HW Flow Director recipes */
if (hw->fdir_prof)
ice_fdir_replay_flows(hw);
/* replay Flow Director filters */
ice_fdir_replay_fltrs(pf);
ice_rebuild_arfs(pf);
}
ice_update_pf_netdev_link(pf);
/* tell the firmware we are up */
@ -4954,6 +5189,8 @@ const char *ice_stat_str(enum ice_status stat_err)
return "ICE_ERR_HW_TABLE";
case ICE_ERR_DOES_NOT_EXIST:
return "ICE_ERR_DOES_NOT_EXIST";
case ICE_ERR_FW_DDP_MISMATCH:
return "ICE_ERR_FW_DDP_MISMATCH";
case ICE_ERR_AQ_ERROR:
return "ICE_ERR_AQ_ERROR";
case ICE_ERR_AQ_TIMEOUT:
@ -4995,7 +5232,7 @@ int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
if (status) {
dev_err(dev, "Cannot set RSS key, err %s aq_err %s\n",
ice_stat_str(status),
ice_aq_str(hw->adminq.rq_last_status));
ice_aq_str(hw->adminq.sq_last_status));
return -EIO;
}
}
@ -5006,7 +5243,7 @@ int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
if (status) {
dev_err(dev, "Cannot set RSS lut, err %s aq_err %s\n",
ice_stat_str(status),
ice_aq_str(hw->adminq.rq_last_status));
ice_aq_str(hw->adminq.sq_last_status));
return -EIO;
}
}
@ -5039,7 +5276,7 @@ int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
if (status) {
dev_err(dev, "Cannot get RSS key, err %s aq_err %s\n",
ice_stat_str(status),
ice_aq_str(hw->adminq.rq_last_status));
ice_aq_str(hw->adminq.sq_last_status));
return -EIO;
}
}
@ -5050,7 +5287,7 @@ int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
if (status) {
dev_err(dev, "Cannot get RSS lut, err %s aq_err %s\n",
ice_stat_str(status),
ice_aq_str(hw->adminq.rq_last_status));
ice_aq_str(hw->adminq.sq_last_status));
return -EIO;
}
}
@ -5523,6 +5760,9 @@ static const struct net_device_ops ice_netdev_ops = {
.ndo_bridge_setlink = ice_bridge_setlink,
.ndo_fdb_add = ice_fdb_add,
.ndo_fdb_del = ice_fdb_del,
#ifdef CONFIG_RFS_ACCEL
.ndo_rx_flow_steer = ice_rx_flow_steer,
#endif
.ndo_tx_timeout = ice_tx_timeout,
.ndo_bpf = ice_xdp,
.ndo_xdp_xmit = ice_xdp_xmit,

2
drivers/net/ethernet/intel/ice/ice_protocol_type.h
View File

@ -12,11 +12,13 @@
*/
enum ice_prot_id {
ICE_PROT_ID_INVAL = 0,
ICE_PROT_MAC_OF_OR_S = 1,
ICE_PROT_IPV4_OF_OR_S = 32,
ICE_PROT_IPV4_IL = 33,
ICE_PROT_IPV6_OF_OR_S = 40,
ICE_PROT_IPV6_IL = 41,
ICE_PROT_TCP_IL = 49,
ICE_PROT_UDP_OF = 52,
ICE_PROT_UDP_IL_OR_S = 53,
ICE_PROT_GRE_OF = 64,
ICE_PROT_SCTP_IL = 96,

2
drivers/net/ethernet/intel/ice/ice_status.h
View File

@ -27,6 +27,8 @@ enum ice_status {
ICE_ERR_MAX_LIMIT = -17,
ICE_ERR_RESET_ONGOING = -18,
ICE_ERR_HW_TABLE = -19,
ICE_ERR_FW_DDP_MISMATCH = -20,
ICE_ERR_NVM_CHECKSUM = -51,
ICE_ERR_BUF_TOO_SHORT = -52,
ICE_ERR_NVM_BLANK_MODE = -53,

75
drivers/net/ethernet/intel/ice/ice_switch.c
View File

@ -2677,6 +2677,81 @@ void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle)
ice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_PROMISC_VLAN);
}
/**
* ice_alloc_res_cntr - allocating resource counter
* @hw: pointer to the hardware structure
* @type: type of resource
* @alloc_shared: if set it is shared else dedicated
* @num_items: number of entries requested for FD resource type
* @counter_id: counter index returned by AQ call
*/
enum ice_status
ice_alloc_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items,
u16 *counter_id)
{
struct ice_aqc_alloc_free_res_elem *buf;
enum ice_status status;
u16 buf_len;
/* Allocate resource */
buf_len = sizeof(*buf);
buf = kzalloc(buf_len, GFP_KERNEL);
if (!buf)
return ICE_ERR_NO_MEMORY;
buf->num_elems = cpu_to_le16(num_items);
buf->res_type = cpu_to_le16(((type << ICE_AQC_RES_TYPE_S) &
ICE_AQC_RES_TYPE_M) | alloc_shared);
status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
ice_aqc_opc_alloc_res, NULL);
if (status)
goto exit;
*counter_id = le16_to_cpu(buf->elem[0].e.sw_resp);
exit:
kfree(buf);
return status;
}
/**
* ice_free_res_cntr - free resource counter
* @hw: pointer to the hardware structure
* @type: type of resource
* @alloc_shared: if set it is shared else dedicated
* @num_items: number of entries to be freed for FD resource type
* @counter_id: counter ID resource which needs to be freed
*/
enum ice_status
ice_free_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items,
u16 counter_id)
{
struct ice_aqc_alloc_free_res_elem *buf;
enum ice_status status;
u16 buf_len;
/* Free resource */
buf_len = sizeof(*buf);
buf = kzalloc(buf_len, GFP_KERNEL);
if (!buf)
return ICE_ERR_NO_MEMORY;
buf->num_elems = cpu_to_le16(num_items);
buf->res_type = cpu_to_le16(((type << ICE_AQC_RES_TYPE_S) &
ICE_AQC_RES_TYPE_M) | alloc_shared);
buf->elem[0].e.sw_resp = cpu_to_le16(counter_id);
status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
ice_aqc_opc_free_res, NULL);
if (status)
ice_debug(hw, ICE_DBG_SW,
"counter resource could not be freed\n");
kfree(buf);
return status;
}
/**
* ice_replay_vsi_fltr - Replay filters for requested VSI
* @hw: pointer to the hardware structure

7
drivers/net/ethernet/intel/ice/ice_switch.h
View File

@ -208,6 +208,13 @@ void ice_clear_all_vsi_ctx(struct ice_hw *hw);
/* Switch config */
enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw);
enum ice_status
ice_alloc_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items,
u16 *counter_id);
enum ice_status
ice_free_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items,
u16 counter_id);
/* Switch/bridge related commands */
enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw);
enum ice_status ice_add_mac(struct ice_hw *hw, struct list_head *m_lst);

182
drivers/net/ethernet/intel/ice/ice_txrx.c
View File

@ -15,6 +15,90 @@
#define ICE_RX_HDR_SIZE 256
#define FDIR_DESC_RXDID 0x40
#define ICE_FDIR_CLEAN_DELAY 10
/**
* ice_prgm_fdir_fltr - Program a Flow Director filter
* @vsi: VSI to send dummy packet
* @fdir_desc: flow director descriptor
* @raw_packet: allocated buffer for flow director
*/
int
ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
u8 *raw_packet)
{
struct ice_tx_buf *tx_buf, *first;
struct ice_fltr_desc *f_desc;
struct ice_tx_desc *tx_desc;
struct ice_ring *tx_ring;
struct device *dev;
dma_addr_t dma;
u32 td_cmd;
u16 i;
/* VSI and Tx ring */
if (!vsi)
return -ENOENT;
tx_ring = vsi->tx_rings[0];
if (!tx_ring || !tx_ring->desc)
return -ENOENT;
dev = tx_ring->dev;
/* we are using two descriptors to add/del a filter and we can wait */
for (i = ICE_FDIR_CLEAN_DELAY; ICE_DESC_UNUSED(tx_ring) < 2; i--) {
if (!i)
return -EAGAIN;
msleep_interruptible(1);
}
dma = dma_map_single(dev, raw_packet, ICE_FDIR_MAX_RAW_PKT_SIZE,
DMA_TO_DEVICE);
if (dma_mapping_error(dev, dma))
return -EINVAL;
/* grab the next descriptor */
i = tx_ring->next_to_use;
first = &tx_ring->tx_buf[i];
f_desc = ICE_TX_FDIRDESC(tx_ring, i);
memcpy(f_desc, fdir_desc, sizeof(*f_desc));
i++;
i = (i < tx_ring->count) ? i : 0;
tx_desc = ICE_TX_DESC(tx_ring, i);
tx_buf = &tx_ring->tx_buf[i];
i++;
tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
memset(tx_buf, 0, sizeof(*tx_buf));
dma_unmap_len_set(tx_buf, len, ICE_FDIR_MAX_RAW_PKT_SIZE);
dma_unmap_addr_set(tx_buf, dma, dma);
tx_desc->buf_addr = cpu_to_le64(dma);
td_cmd = ICE_TXD_LAST_DESC_CMD | ICE_TX_DESC_CMD_DUMMY |
ICE_TX_DESC_CMD_RE;
tx_buf->tx_flags = ICE_TX_FLAGS_DUMMY_PKT;
tx_buf->raw_buf = raw_packet;
tx_desc->cmd_type_offset_bsz =
ice_build_ctob(td_cmd, 0, ICE_FDIR_MAX_RAW_PKT_SIZE, 0);
/* Force memory write to complete before letting h/w know
* there are new descriptors to fetch.
*/
wmb();
/* mark the data descriptor to be watched */
first->next_to_watch = tx_desc;
writel(tx_ring->next_to_use, tx_ring->tail);
return 0;
}
/**
* ice_unmap_and_free_tx_buf - Release a Tx buffer
* @ring: the ring that owns the buffer
@ -24,7 +108,9 @@ static void
ice_unmap_and_free_tx_buf(struct ice_ring *ring, struct ice_tx_buf *tx_buf)
{
if (tx_buf->skb) {
if (ice_ring_is_xdp(ring))
if (tx_buf->tx_flags & ICE_TX_FLAGS_DUMMY_PKT)
devm_kfree(ring->dev, tx_buf->raw_buf);
else if (ice_ring_is_xdp(ring))
page_frag_free(tx_buf->raw_buf);
else
dev_kfree_skb_any(tx_buf->skb);
@ -599,7 +685,8 @@ bool ice_alloc_rx_bufs(struct ice_ring *rx_ring, u16 cleaned_count)
struct ice_rx_buf *bi;
/* do nothing if no valid netdev defined */
if (!rx_ring->netdev || !cleaned_count)
if ((!rx_ring->netdev && rx_ring->vsi->type != ICE_VSI_CTRL) ||
!cleaned_count)
return false;
/* get the Rx descriptor and buffer based on next_to_use */
@ -997,7 +1084,7 @@ ice_is_non_eop(struct ice_ring *rx_ring, union ice_32b_rx_flex_desc *rx_desc,
*
* Returns amount of work completed
*/
static int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget)
int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget)
{
unsigned int total_rx_bytes = 0, total_rx_pkts = 0;
u16 cleaned_count = ICE_DESC_UNUSED(rx_ring);
@ -1040,6 +1127,12 @@ static int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget)
*/
dma_rmb();
if (rx_desc->wb.rxdid == FDIR_DESC_RXDID || !rx_ring->netdev) {
ice_put_rx_buf(rx_ring, NULL);
cleaned_count++;
continue;
}
size = le16_to_cpu(rx_desc->wb.pkt_len) &
ICE_RX_FLX_DESC_PKT_LEN_M;
@ -2378,3 +2471,86 @@ netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev)
return ice_xmit_frame_ring(skb, tx_ring);
}
/**
* ice_clean_ctrl_tx_irq - interrupt handler for flow director Tx queue
* @tx_ring: tx_ring to clean
*/
void ice_clean_ctrl_tx_irq(struct ice_ring *tx_ring)
{
struct ice_vsi *vsi = tx_ring->vsi;
s16 i = tx_ring->next_to_clean;
int budget = ICE_DFLT_IRQ_WORK;
struct ice_tx_desc *tx_desc;
struct ice_tx_buf *tx_buf;
tx_buf = &tx_ring->tx_buf[i];
tx_desc = ICE_TX_DESC(tx_ring, i);
i -= tx_ring->count;
do {
struct ice_tx_desc *eop_desc = tx_buf->next_to_watch;
/* if next_to_watch is not set then there is no pending work */
if (!eop_desc)
break;
/* prevent any other reads prior to eop_desc */
smp_rmb();
/* if the descriptor isn't done, no work to do */
if (!(eop_desc->cmd_type_offset_bsz &
cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE)))
break;
/* clear next_to_watch to prevent false hangs */
tx_buf->next_to_watch = NULL;
tx_desc->buf_addr = 0;
tx_desc->cmd_type_offset_bsz = 0;
/* move past filter desc */
tx_buf++;
tx_desc++;
i++;
if (unlikely(!i)) {
i -= tx_ring->count;
tx_buf = tx_ring->tx_buf;
tx_desc = ICE_TX_DESC(tx_ring, 0);
}
/* unmap the data header */
if (dma_unmap_len(tx_buf, len))
dma_unmap_single(tx_ring->dev,
dma_unmap_addr(tx_buf, dma),
dma_unmap_len(tx_buf, len),
DMA_TO_DEVICE);
if (tx_buf->tx_flags & ICE_TX_FLAGS_DUMMY_PKT)
devm_kfree(tx_ring->dev, tx_buf->raw_buf);
/* clear next_to_watch to prevent false hangs */
tx_buf->raw_buf = NULL;
tx_buf->tx_flags = 0;
tx_buf->next_to_watch = NULL;
dma_unmap_len_set(tx_buf, len, 0);
tx_desc->buf_addr = 0;
tx_desc->cmd_type_offset_bsz = 0;
/* move past eop_desc for start of next FD desc */
tx_buf++;
tx_desc++;
i++;
if (unlikely(!i)) {
i -= tx_ring->count;
tx_buf = tx_ring->tx_buf;
tx_desc = ICE_TX_DESC(tx_ring, 0);
}
budget--;
} while (likely(budget));
i += tx_ring->count;
tx_ring->next_to_clean = i;
/* re-enable interrupt if needed */
ice_irq_dynamic_ena(&vsi->back->hw, vsi, vsi->q_vectors[0]);
}

10
drivers/net/ethernet/intel/ice/ice_txrx.h
View File

@ -113,6 +113,10 @@ static inline int ice_skb_pad(void)
#define ICE_TX_FLAGS_TSO BIT(0)
#define ICE_TX_FLAGS_HW_VLAN BIT(1)
#define ICE_TX_FLAGS_SW_VLAN BIT(2)
/* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be
* freed instead of returned like skb packets.
*/
#define ICE_TX_FLAGS_DUMMY_PKT BIT(3)
#define ICE_TX_FLAGS_IPV4 BIT(5)
#define ICE_TX_FLAGS_IPV6 BIT(6)
#define ICE_TX_FLAGS_TUNNEL BIT(7)
@ -374,5 +378,9 @@ int ice_setup_rx_ring(struct ice_ring *rx_ring);
void ice_free_tx_ring(struct ice_ring *tx_ring);
void ice_free_rx_ring(struct ice_ring *rx_ring);
int ice_napi_poll(struct napi_struct *napi, int budget);
int
ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
u8 *raw_packet);
int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget);
void ice_clean_ctrl_tx_irq(struct ice_ring *tx_ring);
#endif /* _ICE_TXRX_H_ */

59
drivers/net/ethernet/intel/ice/ice_type.h
View File

@ -118,7 +118,8 @@ enum ice_media_type {
enum ice_vsi_type {
ICE_VSI_PF = 0,
ICE_VSI_VF,
ICE_VSI_VF = 1,
ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
ICE_VSI_LB = 6,
};
@ -161,6 +162,38 @@ struct ice_phy_info {
u8 get_link_info;
};
/* protocol enumeration for filters */
enum ice_fltr_ptype {
/* NONE - used for undef/error */
ICE_FLTR_PTYPE_NONF_NONE = 0,
ICE_FLTR_PTYPE_NONF_IPV4_UDP,
ICE_FLTR_PTYPE_NONF_IPV4_TCP,
ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
ICE_FLTR_PTYPE_FRAG_IPV4,
ICE_FLTR_PTYPE_NONF_IPV6_UDP,
ICE_FLTR_PTYPE_NONF_IPV6_TCP,
ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
ICE_FLTR_PTYPE_MAX,
};
enum ice_fd_hw_seg {
ICE_FD_HW_SEG_NON_TUN = 0,
ICE_FD_HW_SEG_TUN,
ICE_FD_HW_SEG_MAX,
};
/* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
#define ICE_MAX_FDIR_VSI_PER_FILTER 2
struct ice_fd_hw_prof {
struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
int cnt;
u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
};
/* Common HW capabilities for SW use */
struct ice_hw_common_caps {
u32 valid_functions;
@ -197,6 +230,8 @@ struct ice_hw_func_caps {
u32 num_allocd_vfs; /* Number of allocated VFs */
u32 vf_base_id; /* Logical ID of the first VF */
u32 guar_num_vsi;
u32 fd_fltr_guar; /* Number of filters guaranteed */
u32 fd_fltr_best_effort; /* Number of best effort filters */
};
/* Device wide capabilities */
@ -204,6 +239,7 @@ struct ice_hw_dev_caps {
struct ice_hw_common_caps common_cap;
u32 num_vfs_exposed; /* Total number of VFs exposed */
u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
u32 num_flow_director_fltr; /* Number of FD filters available */
u32 num_funcs;
};
@ -489,6 +525,8 @@ struct ice_hw {
u64 debug_mask; /* bitmap for debug mask */
enum ice_mac_type mac_type;
u16 fd_ctr_base; /* FD counter base index */
/* pci info */
u16 device_id;
u16 vendor_id;
@ -559,6 +597,7 @@ struct ice_hw {
/* Active package version (currently active) */
struct ice_pkg_ver active_pkg_ver;
u32 active_track_id;
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
u8 active_pkg_in_nvm;
@ -587,6 +626,21 @@ struct ice_hw {
struct ice_blk_info blk[ICE_BLK_COUNT];
struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
struct list_head fl_profs[ICE_BLK_COUNT];
/* Flow Director filter info */
int fdir_active_fltr;
struct mutex fdir_fltr_lock; /* protect Flow Director */
struct list_head fdir_list_head;
/* Book-keeping of side-band filter count per flow-type.
* This is used to detect and handle input set changes for
* respective flow-type.
*/
u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
struct ice_fd_hw_prof **fdir_prof;
DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
struct mutex rss_locks; /* protect RSS configuration */
struct list_head rss_list_head;
};
@ -648,6 +702,9 @@ struct ice_hw_port_stats {
u64 tx_size_1023; /* ptc1023 */
u64 tx_size_1522; /* ptc1522 */
u64 tx_size_big; /* ptc9522 */
/* flow director stats */
u32 fd_sb_status;
u64 fd_sb_match;
};
/* Checksum and Shadow RAM pointers */

120
drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c
View File

@ -80,7 +80,7 @@ ice_vc_vf_broadcast(struct ice_pf *pf, enum virtchnl_ops v_opcode,
enum virtchnl_status_code v_retval, u8 *msg, u16 msglen)
{
struct ice_hw *hw = &pf->hw;
int i;
unsigned int i;
ice_for_each_vf(pf, i) {
struct ice_vf *vf = &pf->vf[i];
@ -325,7 +325,7 @@ void ice_free_vfs(struct ice_pf *pf)
{
struct device *dev = ice_pf_to_dev(pf);
struct ice_hw *hw = &pf->hw;
int tmp, i;
unsigned int tmp, i;
if (!pf->vf)
return;
@ -2316,6 +2316,52 @@ static bool ice_vc_validate_vqs_bitmaps(struct virtchnl_queue_select *vqs)
return true;
}
/**
* ice_vf_ena_txq_interrupt - enable Tx queue interrupt via QINT_TQCTL
* @vsi: VSI of the VF to configure
* @q_idx: VF queue index used to determine the queue in the PF's space
*/
static void ice_vf_ena_txq_interrupt(struct ice_vsi *vsi, u32 q_idx)
{
struct ice_hw *hw = &vsi->back->hw;
u32 pfq = vsi->txq_map[q_idx];
u32 reg;
reg = rd32(hw, QINT_TQCTL(pfq));
/* MSI-X index 0 in the VF's space is always for the OICR, which means
* this is most likely a poll mode VF driver, so don't enable an
* interrupt that was never configured via VIRTCHNL_OP_CONFIG_IRQ_MAP
*/
if (!(reg & QINT_TQCTL_MSIX_INDX_M))
return;
wr32(hw, QINT_TQCTL(pfq), reg | QINT_TQCTL_CAUSE_ENA_M);
}
/**
* ice_vf_ena_rxq_interrupt - enable Tx queue interrupt via QINT_RQCTL
* @vsi: VSI of the VF to configure
* @q_idx: VF queue index used to determine the queue in the PF's space
*/
static void ice_vf_ena_rxq_interrupt(struct ice_vsi *vsi, u32 q_idx)
{
struct ice_hw *hw = &vsi->back->hw;
u32 pfq = vsi->rxq_map[q_idx];
u32 reg;
reg = rd32(hw, QINT_RQCTL(pfq));
/* MSI-X index 0 in the VF's space is always for the OICR, which means
* this is most likely a poll mode VF driver, so don't enable an
* interrupt that was never configured via VIRTCHNL_OP_CONFIG_IRQ_MAP
*/
if (!(reg & QINT_RQCTL_MSIX_INDX_M))
return;
wr32(hw, QINT_RQCTL(pfq), reg | QINT_RQCTL_CAUSE_ENA_M);
}
/**
* ice_vc_ena_qs_msg
* @vf: pointer to the VF info
@ -2376,6 +2422,7 @@ static int ice_vc_ena_qs_msg(struct ice_vf *vf, u8 *msg)
goto error_param;
}
ice_vf_ena_rxq_interrupt(vsi, vf_q_id);
set_bit(vf_q_id, vf->rxq_ena);
}
@ -2391,6 +2438,7 @@ static int ice_vc_ena_qs_msg(struct ice_vf *vf, u8 *msg)
if (test_bit(vf_q_id, vf->txq_ena))
continue;
ice_vf_ena_txq_interrupt(vsi, vf_q_id);
set_bit(vf_q_id, vf->txq_ena);
}
@ -3592,6 +3640,39 @@ ice_get_vf_cfg(struct net_device *netdev, int vf_id, struct ifla_vf_info *ivi)
return 0;
}
/**
* ice_unicast_mac_exists - check if the unicast MAC exists on the PF's switch
* @pf: PF used to reference the switch's rules
* @umac: unicast MAC to compare against existing switch rules
*
* Return true on the first/any match, else return false
*/
static bool ice_unicast_mac_exists(struct ice_pf *pf, u8 *umac)
{
struct ice_sw_recipe *mac_recipe_list =
&pf->hw.switch_info->recp_list[ICE_SW_LKUP_MAC];
struct ice_fltr_mgmt_list_entry *list_itr;
struct list_head *rule_head;
struct mutex *rule_lock; /* protect MAC filter list access */
rule_head = &mac_recipe_list->filt_rules;
rule_lock = &mac_recipe_list->filt_rule_lock;
mutex_lock(rule_lock);
list_for_each_entry(list_itr, rule_head, list_entry) {
u8 *existing_mac = &list_itr->fltr_info.l_data.mac.mac_addr[0];
if (ether_addr_equal(existing_mac, umac)) {
mutex_unlock(rule_lock);
return true;
}
}
mutex_unlock(rule_lock);
return false;
}
/**
* ice_set_vf_mac
* @netdev: network interface device structure
@ -3615,10 +3696,20 @@ int ice_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
}
vf = &pf->vf[vf_id];
/* nothing left to do, unicast MAC already set */
if (ether_addr_equal(vf->dflt_lan_addr.addr, mac))
return 0;
ret = ice_check_vf_ready_for_cfg(vf);
if (ret)
return ret;
if (ice_unicast_mac_exists(pf, mac)) {
netdev_err(netdev, "Unicast MAC %pM already exists on this PF. Preventing setting VF %u unicast MAC address to %pM\n",
mac, vf_id, mac);
return -EINVAL;
}
/* copy MAC into dflt_lan_addr and trigger a VF reset. The reset
* flow will use the updated dflt_lan_addr and add a MAC filter
* using ice_add_mac. Also set pf_set_mac to indicate that the PF has
@ -3756,6 +3847,24 @@ int ice_get_vf_stats(struct net_device *netdev, int vf_id,
return 0;
}
/**
* ice_print_vf_rx_mdd_event - print VF Rx malicious driver detect event
* @vf: pointer to the VF structure
*/
void ice_print_vf_rx_mdd_event(struct ice_vf *vf)
{
struct ice_pf *pf = vf->pf;
struct device *dev;
dev = ice_pf_to_dev(pf);
dev_info(dev, "%d Rx Malicious Driver Detection events detected on PF %d VF %d MAC %pM. mdd-auto-reset-vfs=%s\n",
vf->mdd_rx_events.count, pf->hw.pf_id, vf->vf_id,
vf->dflt_lan_addr.addr,
test_bit(ICE_FLAG_MDD_AUTO_RESET_VF, pf->flags)
? "on" : "off");
}
/**
* ice_print_vfs_mdd_event - print VFs malicious driver detect event
* @pf: pointer to the PF structure
@ -3785,12 +3894,7 @@ void ice_print_vfs_mdd_events(struct ice_pf *pf)
if (vf->mdd_rx_events.count != vf->mdd_rx_events.last_printed) {
vf->mdd_rx_events.last_printed =
vf->mdd_rx_events.count;
dev_info(dev, "%d Rx Malicious Driver Detection events detected on PF %d VF %d MAC %pM. mdd-auto-reset-vfs=%s\n",
vf->mdd_rx_events.count, hw->pf_id, i,
vf->dflt_lan_addr.addr,
test_bit(ICE_FLAG_MDD_AUTO_RESET_VF, pf->flags)
? "on" : "off");
ice_print_vf_rx_mdd_event(vf);
}
/* only print Tx MDD event message if there are new events */

2
drivers/net/ethernet/intel/ice/ice_virtchnl_pf.h
View File

@ -132,6 +132,7 @@ bool ice_is_any_vf_in_promisc(struct ice_pf *pf);
void
ice_vf_lan_overflow_event(struct ice_pf *pf, struct ice_rq_event_info *event);
void ice_print_vfs_mdd_events(struct ice_pf *pf);
void ice_print_vf_rx_mdd_event(struct ice_vf *vf);
#else /* CONFIG_PCI_IOV */
#define ice_process_vflr_event(pf) do {} while (0)
#define ice_free_vfs(pf) do {} while (0)
@ -141,6 +142,7 @@ void ice_print_vfs_mdd_events(struct ice_pf *pf);
#define ice_set_vf_state_qs_dis(vf) do {} while (0)
#define ice_vf_lan_overflow_event(pf, event) do {} while (0)
#define ice_print_vfs_mdd_events(pf) do {} while (0)
#define ice_print_vf_rx_mdd_event(vf) do {} while (0)
static inline bool
ice_reset_all_vfs(struct ice_pf __always_unused *pf,

5
include/linux/avf/virtchnl.h
View File

@ -476,6 +476,7 @@ struct virtchnl_rss_key {
u16 vsi_id;
u16 key_len;
u8 key[1]; /* RSS hash key, packed bytes */
u8 pad[1];
};
VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_rss_key);
@ -484,6 +485,7 @@ struct virtchnl_rss_lut {
u16 vsi_id;
u16 lut_entries;
u8 lut[1]; /* RSS lookup table */
u8 pad[1];
};
VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_rss_lut);
@ -572,6 +574,7 @@ struct virtchnl_filter {
enum virtchnl_action action;
u32 action_meta;
u8 field_flags;
u8 pad[3];
};
VIRTCHNL_CHECK_STRUCT_LEN(272, virtchnl_filter);
@ -610,6 +613,7 @@ struct virtchnl_pf_event {
/* link_speed provided in Mbps */
u32 link_speed;
u8 link_status;
u8 pad[3];
} link_event_adv;
} event_data;
@ -635,6 +639,7 @@ struct virtchnl_iwarp_qv_info {
u16 ceq_idx;
u16 aeq_idx;
u8 itr_idx;
u8 pad[3];
};
VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_iwarp_qv_info);